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openpowerwtf 2 years ago
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© IBM Corp. 2021
Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
repository except in compliance with the License as modified.
You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0

Modified Terms:

1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
the work of authorship in physical form.

Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
governing permissions and limitations under the License.

Brief explanation of modifications:

Modification 1: This modification extends the patent license to an implementation of the Work in physical form i.e.,
it unambiguously permits a user to make and use the physical chip.

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## Cells needed for the Skywater test site

We need to produce the necessary
* Schematic
* Layout
* Logic and timing models for



### Low level cells

1) 10T SRAM
a. WWL, RWL0, , RWL1
b. (WBL WBL_B), RBL0, RBL1
2) Local eval (NAND2 with 2 precharged inputs)

a. PC_Left, PC_Right, In_Left, In_Right -> Q (output)

3) LSDL state-holding latch (Latch with 2 dynamic inputs forming an 'Or')

a. In_Left, In_Right, CLK -> Q (output)


### Mid level cell

Partially decode 2R1W 64Rx24 bit array). (Includes early/late output latch)

Inputs:

1) Clock*A0,Clock*~A0
2) ~A1*~A2,~A1,*~A2, A1*~A2,A1*~A2,
3) A3 ,~A3
4) ~A4*~A5,~A4,*~A5, A14*~A5,A4*~A5,
5) DataIn0..DI23
6) Early and late Clock for LSDL state holding latch.

Outputs:

1) DataOut00..DO023
2) DO10..DO123
3) DO20..DO223
4) DO30..DO323

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## Cells needed for the Skywater test site

We need to produce the necessary
* Schematic
* Layout
* Logic and timing models for

### Low level cells

1) 10T SRAM
a. WWL, RWL0, , RWL1
b. (WBL WBL_B), RBL0, RBL1
2) Local eval (NAND2 with 2 precharged inputs)

a. PC_Left, PC_Right, In_Left, In_Right -> Q (output)

3) LSDL state-holding latch (Latch with 2 dynamic inputs forming an 'Or')

a. In_Left, In_Right, CLK -> Q (output)


### Mid level cell

Partially decode 2R1W 64Rx24 bit array). (Includes early/late output latch)

Inputs:

1) Clock*A0,Clock*~A0
2) ~A1*~A2,~A1,*~A2, A1*~A2,A1*~A2,
3) A3 ,~A3
4) ~A4*~A5,~A4,*~A5, A14*~A5,A4*~A5,
5) DataIn0..DI23
6) Early and late Clock for LSDL state holding latch.

Outputs:

1) DataOut00..DO023
2) DO10..DO123
3) DO20..DO223
4) DO30..DO323

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# General Notes

## SDR/DDR

* logical wrappers instantiate hard array
* SDR: use multiple hard array instances to add ports
* DDR: use early/late pulses to double read/write ports

### DDR Implementation

* strobes are generated from clk based on configurable delay parameters

## Test site arrays

* 2R1W, SDR - this is the sdr hard array and simple logical wrapper using single clock
* 4R2W, DDR - this is the ddr hard array and double-rate logical wrapper generating early/late pulses

### Configuration options

* SDR clock frequency (external to logical array)
* DDR clock frequency (external to logical array)

* SDR Pulse Control
* DDR Pulse Control

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<img align="right" src="doc/img/bob_64x64.jpg">

# ToySRAM

## A test site for a high-specific-bandwidth memory design

* We make high-specific-bandwidth multiport memories childs play
* We make 10T SRAM a first-class citizen, and use pumping and replication for high frequency and additional ports

![toy-sram](doc/slide2.png)

## Description

The goal is to demonstrate specific bandwidth results from 90nm to 2nm, and use
the basic design to grow as many ports as necessary through replication, to
produce more efficient processors and accelerators with *less circuit-design effort*.

What is specific bandwidth?

* It measures the read and write bandwidth per unit area
* Bandwidth per unit area is an analog to specific gravity, which is mass per unit volume
* It's more encompassing than bit density, which drives complexity to improve bandwidth

Why does Toy-SRAM do so well?

* It's enhanced by having a 10T SRAM/2 read ports/1 write port
* It supports low-cost super-pipelining (2x+ the system frequency, without latch overhead)
* It enables energy-efficient ultralow-voltage operation by avoiding read disturb

Specific bandwidth can be expressed with two metrics:

* Technology dependent “X TB/(sec * mm 2 )”
* Technology independent “Y 1/(FO4 delay * PC PITCH * min horizontal metal pitch)”

<img align="left" width="40%" src="/custom/layout/sram_sp.png">
<img align="right" width="40%" src="/custom/layout/sram_dp.png">
<br clear="all" />

## Links

* skywater-pdk.slack.com#toysram

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---
project:
description: "High-specific-bandwidth memory cell test site for 90nm"
foundry: "SkyWater"
git_url: "https://git.openpower.foundation/cores/toysram.git"
organization: "Open POWER"
organization_url: "http://openpowerfoundation.com"
owner: "Bob Montoya"
process: "SKY90"
project_name: "ToySRAM"
project_id: "00000000"
tags:
- "Open MPW"
- "Custom Cell"
- "Array"
category: "Custom Cell"
top_level_netlist: "verilog/gl/site.v"
user_level_netlist: "verilog/gl/user_project_wrapper.v"
version: "1.00"
cover_image: "docs/img/bob.jpg"

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// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0

`default_nettype none
/*
*-------------------------------------------------------------
*
* user_project_wrapper
*
* This wrapper enumerates all of the pins available to the
* user for the user project.
*
* An example user project is provided in this wrapper. The
* example should be removed and replaced with the actual
* user project.
*
*-------------------------------------------------------------
*/

module user_project_wrapper #(
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif

// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,

// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oen,

// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,

// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7.
inout [`MPRJ_IO_PADS-8:0] analog_io,

// Independent clock (on independent integer divider)
input user_clock2
);
endmodule // user_project_wrapper

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# design and tech

unit = test_sdr_2r1w_64x72_top

# top directory
export DESIGN_TOP = array
# unit directory (log, objects, reports, results)
export DESIGN_NICKNAME = array_$(unit)
# macro
export DESIGN_NAME = $(unit)
#tech
export PLATFORM = sky130hd

# sources
export VERILOG_FILES = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_TOP)/src/verilog/work/test_sdr_2r1w_64x72_top.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_TOP)/constraint_$(unit).sdc

$(info Source files:)
$(info $(VERILOG_FILES))
$(info ..................................................)

# parms
export PLACE_DENSITY ?= 0.50
export ABC_CLOCK_PERIOD_IN_PS ?= 10

# must be multiples of placement site (0.46 x 2.72)
export DIE_AREA = 0 0 3011.160 4022.880
export CORE_AREA = 5.520 10.880 3005.640 4012.000

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set clk_name clock
set clk_period 10
set input_delay_value 1
set output_delay_value 1

# define clock
# nclk[0]: clk
# nclk[1]: reset
# nclk[2]: clk2x (fpga)
# nclk[3]: clk4x (fpga)

#set clkPort [lindex [get_ports $clk_name] 0] ;#wtf IS SELECTING 0 ALWAYS CORRECT??? tritoncts doesnt like this
set clkPort [get_ports $clk_name]
create_clock $clkPort -name clock -period $clk_period

# apply clock to ins and outs
set clk_index [lsearch [all_inputs] $clkPort]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_index $clk_index]
set_input_delay $input_delay_value -clock [get_clocks clk] $all_inputs_wo_clk
set_output_delay $output_delay_value -clock [get_clocks clk] [all_outputs]

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## Logical Array Wrapper

* verilog is in rtl/src/array
* parameter determines sim vs tech during rtl compile

## Physical Array

* custom cell(s) to be designed
* custom/

## Test Site

* verilog is in rtl/src/site
* supporting logic for test and debug through available Caravel connections

## Verification

* rtl/sim/coco

## Caravel

* to be incorporated into https://github.com/efabless/caravel flow as a user project area

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__pycache__/
sim_build/
build_32x32/
build_site/

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# sdr ra
# make -f Makefile.icarus build # rebuild and sim and fst
# make -f Makefile.icarus run # sim and fst
# make -f Makefile.icarus # sim

#COCOTB_LOG_LEVEL=DEBUG
#GPI_EXTRA=vpi

#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM

SIM_BUILD ?= build_32x32
SIM ?= icarus

# options
#COCOTB_HDL_TIMEUNIT ?= 1ns
#COCOTB_HDL_TIMEPRECISION ?= 1ps
#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM

# icarus

VERILOG_ROOT = src

COMPILE_ARGS = -I$(VERILOG_ROOT) -y$(VERILOG_ROOT)

# other options

# rtl
TOPLEVEL_LANG = verilog
# top-level to enable trace, etc.
VERILOG_SOURCES = ./test_ra_sdr_32x32.v
TOPLEVEL = test_ra_sdr_32x32

# python test
MODULE = tb
TESTCASE = tb_32x32

# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim

build: clean sim fst

run: sim fst

fst:
vcd2fst test_ra_sdr_32x32.vcd test_ra_sdr_32x32.fst
#rm test_ra_sdr_32x32.vcd

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# sdr ra
# make -f Makefile.icarus build # rebuild and sim and fst
# make -f Makefile.icarus run # sim and fst
# make -f Makefile.icarus # sim

#COCOTB_LOG_LEVEL=DEBUG
#GPI_EXTRA=vpi

#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM

#SIM_BUILD ?= build
SIM ?= icarus

# options
#COCOTB_HDL_TIMEUNIT ?= 1ns
#COCOTB_HDL_TIMEPRECISION ?= 1ps
#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM

# icarus

VERILOG_ROOT = src

COMPILE_ARGS = -I$(VERILOG_ROOT) -y$(VERILOG_ROOT)

# other options

# rtl
TOPLEVEL_LANG = verilog
# top-level to enable trace, etc.
VERILOG_SOURCES = ./test_ra_sdr_64x72.v
TOPLEVEL = test_ra_sdr_64x72

# python test
MODULE = tb
TESTCASE = tb

# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim

build: clean sim fst

run: sim fst

fst:
vcd2fst test_ra_sdr_64x72.vcd test_ra_sdr_64x72.fst
rm test_ra_sdr_64x72.vcd

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# sdr ra
# make -f Makefile.icarus build # rebuild and sim and fst
# make -f Makefile.icarus run # sim and fst
# make -f Makefile.icarus # sim

#COCOTB_LOG_LEVEL=DEBUG
#GPI_EXTRA=vpi

#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM

SIM_BUILD ?= build_site
SIM ?= icarus

# options
#COCOTB_HDL_TIMEUNIT ?= 1ns
#COCOTB_HDL_TIMEPRECISION ?= 1ps
#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM

# icarus

VERILOG_ROOT = src

COMPILE_ARGS = -I$(VERILOG_ROOT)/../site -I$(VERILOG_ROOT)/../array -y$(VERILOG_ROOT)/../site -y$(VERILOG_ROOT)/../array

# other options

# rtl
TOPLEVEL_LANG = verilog
# top-level to enable trace, etc.
VERILOG_SOURCES = ./test_site.v
TOPLEVEL = test_site

# python test
MODULE = tb
TESTCASE = tb_site

# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim

build: clean sim fst

run: sim fst

fst:
vcd2fst test_site.vcd test_site.fst
rm test_site.vcd

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# OP Environment

import cocotb
from cocotb.triggers import Timer
from cocotb.handle import Force
from cocotb.handle import Release

from dotmap import DotMap

# ------------------------------------------------------------------------------------------------
# Classes

class Sim(DotMap):

def msg(self, m):
self.dut._log.info(f'[{self.cycle:08d}] {m}') #wtf do multiline if /n in m

def __init__(self, dut, cfg=None):
super().__init__()
self.dut = dut
# defaults
self.memFiles = [] #wtf cmdline parm
self.threads = 0
self.resetCycle = 10
self.hbCycles = 100
self.clk2x = True
self.clk4x = False
self.resetAddr = 0xFFFFFFFC
self.resetOp = 0x48000002
self.maxCycles = 150
self.memFiles = None
self.config = DotMap()
self.config.core = DotMap({
'creditsLd': 1,
'creditsSt': 1,
'creditsLdStSingle': False
})
self.config.a2l2 = DotMap({
'badAddr': [('E0','E0', 'IRW')]
})
# json
if cfg is not None:
pass

# runtime
self.cycle = 0
self.ok = True
self.fail = None
self.done = False

if self.threads is None:
try:
v = dut.an_ac_pm_thread_stop[1].value
self.threads = 2
except:
self.threads = 1
self.msg(f'Set threads={self.threads}.')

class TransQ(DotMap):
def __init__(self):
super().__init__()

class Memory(DotMap):

def __init__(self, sim, default=0, logStores=True):
super().__init__()
self.sim = sim
self.data = {}
self.le = False
self.default = default # default word data for unloaded
self.logStores = logStores

def loadFile(self, filename, format='ascii', addr=0, le=0):
# format # binary, ascii, ascii w/addr
# le: reverse bytes
try:
if format == 'ascii':
with open(filename, 'r') as f:
lines = f.readlines()
for line in lines:
self.data[addr] = int(line, 16) # key is int
addr += 4
elif format == 'binary':
pass
elif format == 'addrdata':
pass
except Exception as e:
self.sim.msg(f'Error reading {filename}:\n{e}')
raise IOError

# word-aligned byte address
def read(self, addr):
try:
addr = addr + 0
except:
addr = int(addr, 16)
if addr in self.data:
return self.data[addr]
else:
return self.default

# word-aligned byte address + data
def write(self, addr, data):
try:
addr = addr + 0
except:
addr = int(addr, 16)
try:
data = data + 0
except:
data = int(data, 16)
if self.logStores:
if addr not in self.data:
self.sim.msg(f'Mem Update: @{addr:08X} XXXXXXXX->{data:08X}')
else:
self.sim.msg(f'Mem Update: @{addr:08X} {self.data[addr]:08X}->{data:08X}')
self.data[addr] = data

File diff suppressed because it is too large Load Diff

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# Cocotb + Icarus Verilog Array Sim

Cocotb test created from original pyverilator version - run random commands using 64x72 logical array.

## Array Wrapper

* compile and run

```
make -f Makefile_sdr_32x32 build

```

* just run (tb.py changes, etc.)

```
make -f Makefile_sdr_32x32 run

```

* results

```
make -f Makefile_sdr_32x32 run >& sim_32x32.txt

MODULE=tb TESTCASE=tb_32x32 TOPLEVEL=test_ra_sdr_32x32 TOPLEVEL_LANG=verilog \
/usr/local/bin/vvp -M /home/wtf/.local/lib/python3.8/site-packages/cocotb/libs -m libcocotbvpi_icarus build_32x32/sim.vvp
-.--ns INFO cocotb.gpi ..mbed/gpi_embed.cpp:76 in set_program_name_in_venv Did not detect Python virtual environment. Using system-wide Python interpreter
-.--ns INFO cocotb.gpi ../gpi/GpiCommon.cpp:99 in gpi_print_registered_impl VPI registered
0.00ns INFO Running on Icarus Verilog version 12.0 (devel)
0.00ns INFO Running tests with cocotb v1.7.0.dev0 from /home/wtf/.local/lib/python3.8/site-packages/cocotb
0.00ns INFO Seeding Python random module with 1654704020
0.00ns INFO Found test tb.tb_32x32
0.00ns INFO running tb_32x32 (1/0)
ToySRAM 32x32 array test
0.00ns INFO [00000001] [00000001] Resetting...
9.00ns INFO [00000010] [00000010] Releasing reset.
25.00ns INFO [00000027] Initializing array...
25.00ns INFO [00000027] Port=0 WR @00=00555500
26.00ns INFO [00000028] Port=0 WR @01=01555501
27.00ns INFO [00000029] Port=0 WR @02=02555502
28.00ns INFO [00000030] Port=0 WR @03=03555503
29.00ns INFO [00000031] Port=0 WR @04=04555504
30.00ns INFO [00000032] Port=0 WR @05=05555505
31.00ns INFO [00000033] Port=0 WR @06=06555506
32.00ns INFO [00000034] Port=0 WR @07=07555507
33.00ns INFO [00000035] Port=0 WR @08=08555508
...
10037.50ns INFO [00010039] Port=0 WR @12=6C6FD11E
10038.50ns INFO [00010040] Port=0 WR @17=545B517F
10039.50ns INFO [00010041] Port=0 RD @08
10039.50ns INFO [00010041] Port=1 RD @0E
10041.50ns INFO [00010043] * RD COMPARE * port=0 adr=08 act=BE99B13E exp=BE99B13E
10041.50ns INFO [00010043] * RD COMPARE * port=1 adr=0E act=97A2D496 exp=97A2D496
10041.50ns INFO [00010043] Port=0 WR @1A=76434F37
10041.50ns INFO [00010043] Port=1 RD @0D
10042.50ns INFO [00010044] Port=0 WR @12=069ECCCE
10042.50ns INFO [00010044] Port=0 RD @13
10043.50ns INFO [00010045] * RD COMPARE * port=1 adr=0D act=C1C0D7D8 exp=C1C0D7D8
10043.50ns INFO [00010045] Port=0 WR @05=58E318E7
10043.50ns INFO [00010045] Port=0 RD @10
10043.50ns INFO [00010045] Port=1 RD @00
10044.50ns INFO [00010046] * RD COMPARE * port=0 adr=13 act=1D975E90 exp=1D975E90
10044.50ns INFO [00010046] Port=0 RD @14
10044.50ns INFO [00010046] Port=1 RD @1D
10045.50ns INFO [00010047] * RD COMPARE * port=0 adr=10 act=F82AB140 exp=F82AB140
10045.50ns INFO [00010047] * RD COMPARE * port=1 adr=00 act=3C2E724D exp=3C2E724D
10046.50ns INFO [00010048] * RD COMPARE * port=0 adr=14 act=1A27AA07 exp=1A27AA07
10046.50ns INFO [00010048] * RD COMPARE * port=1 adr=1D act=5B9AE71C exp=5B9AE71C
10047.50ns INFO [00010049] Quiescing...
10057.00ns INFO [00010059] Done.
10057.00ns INFO [00010059] Final State

Reads Port 0: 4005
Reads Port 1: 4052
Writes Port 0: 4055
10057.00ns INFO [00010059] [00010059] You has opulence.
10057.00ns INFO tb_32x32 passed
10057.00ns INFO **************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
**************************************************************************************
** tb.tb_32x32 PASS 10057.00 8.54 1177.70 **
**************************************************************************************
** TESTS=0 PASS=1 FAIL=0 SKIP=0 10057.00 8.56 1174.42 **
**************************************************************************************

VCD info: dumpfile test_ra_sdr_32x32.vcd opened for output.
VCD warning: $dumpvars: Package ($unit) is not dumpable with VCD.
make[1]: Leaving directory '/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco'
vcd2fst test_ra_sdr_32x32.vcd test_ra_sdr_32x32.fst
#rm test_ra_sdr_32x32.vcd

```

```
gtkwave test_ra_sdr_32x32.fst wtf_test_ra_sdr_32x32.gtkw
```

## Test Site

* compile and run

```
make -f Makefile_site build

```

* just run (tb.py changes, etc.)

```
make -f Makefile_site run

```

* results

```
0.00ns INFO Running on Icarus Verilog version 12.0 (devel)
0.00ns INFO Running tests with cocotb v1.7.0.dev0 from /home/wtf/.local/lib/python3.8/site-packages/cocotb
0.00ns INFO Seeding Python random module with 1655136638
0.00ns INFO Found test tb.tb_site
0.00ns INFO running tb_site (1/0)
ToySRAM site test
VCD info: dumpfile test_site.vcd opened for output.
VCD warning: $dumpvars: Package ($unit) is not dumpable with VCD.
0.00ns INFO [00000001] Resetting...
9.00ns INFO [00000010] Releasing reset.
15.00ns INFO [00000017] Writing Port 0 @00100000 00=633212F3
17.00ns INFO [00000019] Reading Port 0 @00100000 00
22.00ns INFO [00000024] Read Data: 633212F3
22.00ns INFO [00000024] Writing Port 0 @00100001 01=6A0278C9
24.00ns INFO [00000026] Reading Port 0 @00100001 01
29.00ns INFO [00000031] Read Data: 6A0278C9
...
1769.00ns INFO [00001770] Writing W0@15=08675309...
1769.00ns INFO [00001770] Scanning in...
1798.00ns INFO [00001800] ...tick...
1898.00ns INFO [00001900] ...tick...
1998.00ns INFO [00002000] ...tick...
2075.00ns INFO [00002076] Blipping RA0 clk...
2098.00ns INFO [00002100] ...tick...
2175.00ns INFO [00002176] Reading R0@15, R1@16...
2175.00ns INFO [00002176] Scanning in...
2198.00ns INFO [00002200] ...tick...
2298.00ns INFO [00002300] ...tick...
2398.00ns INFO [00002400] ...tick...
2481.00ns INFO [00002482] Blipping RA0 clk...
2498.00ns INFO [00002500] ...tick...
2581.00ns INFO [00002582] Blipping RA0 clk...
2598.00ns INFO [00002600] ...tick...
2681.00ns INFO [00002682] Blipping RA0 clk...
2698.00ns INFO [00002700] ...tick...
2781.00ns INFO [00002782] Scanning out...
2798.00ns INFO [00002800] ...tick...
2898.00ns INFO [00002900] ...tick...
2998.00ns INFO [00003000] ...tick...
3035.00ns INFO [00003036] ScanData=78433A984C075227A100000000000000
3035.00ns INFO [00003036] r0 adr:0F
3035.00ns INFO [00003036] r0 dat:08675309
3035.00ns INFO [00003036] r1 adr:10
3035.00ns INFO [00003036] r1 dat:1D489E84
3035.00ns INFO [00003036] w0 adr:00
3035.00ns INFO [00003036] w0 dat:00000000
3035.00ns INFO [00003036] cfg:00000
3035.00ns INFO [00003036] Done
3044.00ns INFO tb_site passed
3044.00ns INFO **************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
**************************************************************************************
** tb.tb_site PASS 3044.00 0.87 3517.25 **
**************************************************************************************
** TESTS=0 PASS=1 FAIL=0 SKIP=0 3044.00 0.89 3420.87 **
**************************************************************************************
```

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@ -0,0 +1 @@
../../src/array

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@ -0,0 +1,148 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Test array (SDR) wrapper for cocotb/icarus
// 32 word 32 bit array
// LCB for strobe generation
// Config, BIST, etc.

`timescale 1 ns / 1 ns

`include "toysram.vh"

module test_ra_sdr_32x32 (

clk,
reset,
cfg_wr,
cfg_dat,
bist_ctl,
bist_status,

rd_enb_0,
rd_adr_0,
rd_dat_0,

rd_enb_1,
rd_adr_1,
rd_dat_1,

wr_enb_0,
wr_adr_0,
wr_dat_0

);

input clk;
input reset;
input cfg_wr;
input [0:`LCBSDR_CONFIGWIDTH-1] cfg_dat;
input [0:31] bist_ctl;
output [0:31] bist_status;
input rd_enb_0;
input [0:4] rd_adr_0;
output [0:31] rd_dat_0;
input rd_enb_1;
input [0:4] rd_adr_1;
output [0:31] rd_dat_1;
input wr_enb_0;
input [0:4] wr_adr_0;
input [0:31] wr_dat_0;

wire strobe;
wire [0:`LCBSDR_CONFIGWIDTH-1] cfg;
wire mux_rd0_enb;
wire [0:4] mux_rd0_adr;
wire mux_rd1_enb;
wire [0:4] mux_rd1_adr;
wire mux_wr0_enb;
wire [0:4] mux_wr0_adr;
wire [0:31] mux_wr0_dat;


initial begin
$dumpfile ("test_ra_sdr_32x32.vcd");
$dumpvars;
#1;
end

ra_lcb_sdr lcb (

.clk (clk),
.reset (reset),
.cfg (cfg),
.strobe (strobe)

);

ra_cfg_sdr #(.INIT(-1)) cfig (

.clk (clk),
.reset (reset),
.cfg_wr (cfg_wr),
.cfg_dat (cfg_dat),
.cfg (cfg)

);

ra_bist_sdr_32x32 bist (

.clk (clk),
.reset (reset),
.ctl (bist_ctl),
.status (bist_status),
.rd0_enb_in (rd_enb_0),
.rd0_adr_in (rd_adr_0),
.rd0_dat (rd_dat_0),
.rd1_enb_in (rd_enb_1),
.rd1_adr_in (rd_adr_1),
.rd1_dat (rd_dat_1),
.wr0_enb_in (wr_enb_0),
.wr0_adr_in (wr_adr_0),
.wr0_dat_in (wr_dat_0),
.rd0_enb_out (mux_rd0_enb),
.rd0_adr_out (mux_rd0_adr),
.rd1_enb_out (mux_rd1_enb),
.rd1_adr_out (mux_rd1_adr),
.wr0_enb_out (mux_wr0_enb),
.wr0_adr_out (mux_wr0_adr),
.wr0_dat_out (mux_wr0_dat)

);

ra_2r1w_32x32_sdr ra (

.clk (clk),
.reset (reset),
.strobe (strobe),
.rd_enb_0 (mux_rd0_enb),
.rd_adr_0 (mux_rd0_adr),
.rd_dat_0 (rd_dat_0),
.rd_enb_1 (mux_rd1_enb),
.rd_adr_1 (mux_rd1_adr),
.rd_dat_1 (rd_dat_1),
.wr_enb_0 (mux_wr0_enb),
.wr_adr_0 (mux_wr0_adr),
.wr_dat_0 (mux_wr0_dat)

);

endmodule

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@ -0,0 +1,148 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Test array (SDR) wrapper for cocotb/icarus
// 64 word 72 bit array
// LCB for strobe generation
// Config, BIST, etc.

`timescale 1 ns / 1 ns

`include "toysram.vh"

module test_ra_sdr_64x72 (

clk,
reset,
cfg_wr,
cfg_dat,
bist_ctl,
bist_status,

rd_enb_0,
rd_adr_0,
rd_dat_0,

rd_enb_1,
rd_adr_1,
rd_dat_1,

wr_enb_0,
wr_adr_0,
wr_dat_0

);

input clk;
input reset;
input cfg_wr;
input [0:`LCBSDR_CONFIGWIDTH-1] cfg_dat;
input [0:31] bist_ctl;
output [0:31] bist_status;
input rd_enb_0;
input [0:5] rd_adr_0;
output [0:71] rd_dat_0;
input rd_enb_1;
input [0:5] rd_adr_1;
output [0:71] rd_dat_1;
input wr_enb_0;
input [0:5] wr_adr_0;
input [0:71] wr_dat_0;

wire strobe;
wire [0:`LCBSDR_CONFIGWIDTH-1] cfg;
wire mux_rd0_enb;
wire [0:5] mux_rd0_adr;
wire mux_rd1_enb;
wire [0:5] mux_rd1_adr;
wire mux_wr0_enb;
wire [0:5] mux_wr0_adr;
wire [0:71] mux_wr0_dat;


initial begin
$dumpfile ("test_ra_sdr_64x72.vcd");
$dumpvars;
#1;
end

ra_lcb_sdr lcb (

.clk (clk),
.reset (reset),
.cfg (cfg),
.strobe (strobe)

);

ra_cfg_sdr #(.INIT(-1)) cfig (

.clk (clk),
.reset (reset),
.cfg_wr (cfg_wr),
.cfg_dat (cfg_dat),
.cfg (cfg)

);

ra_bist_sdr bist (

.clk (clk),
.reset (reset),
.ctl (bist_ctl),
.status (bist_status),
.rd0_enb_in (rd_enb_0),
.rd0_adr_in (rd_adr_0),
.rd0_dat (rd_dat_0),
.rd1_enb_in (rd_enb_1),
.rd1_adr_in (rd_adr_1),
.rd1_dat (rd_dat_1),
.wr0_enb_in (wr_enb_0),
.wr0_adr_in (wr_adr_0),
.wr0_dat_in (wr_dat_0),
.rd0_enb_out (mux_rd0_enb),
.rd0_adr_out (mux_rd0_adr),
.rd1_enb_out (mux_rd1_enb),
.rd1_adr_out (mux_rd1_adr),
.wr0_enb_out (mux_wr0_enb),
.wr0_adr_out (mux_wr0_adr),
.wr0_dat_out (mux_wr0_dat)

);

ra_2r1w_64x72_sdr ra (

.clk (clk),
.reset (reset),
.strobe (strobe),
.rd_enb_0 (mux_rd0_enb),
.rd_adr_0 (mux_rd0_adr),
.rd_dat_0 (rd_dat_0),
.rd_enb_1 (mux_rd1_enb),
.rd_adr_1 (mux_rd1_adr),
.rd_dat_1 (rd_dat_1),
.wr_enb_0 (mux_wr0_enb),
.wr_adr_0 (mux_wr0_adr),
.wr_dat_0 (mux_wr0_dat)

);

endmodule

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@ -0,0 +1,106 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Test array (SDR) wrapper for cocotb/icarus
// 32 word 32 bit array
// LCB for strobe generation
// Config, BIST, etc.

`timescale 1 ns / 1 ns

`include "defines.v"
`include "toysram.vh"

module test_site (

`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif

// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,

// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,

// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,

// IRQ
output [2:0] irq

);

initial begin
$dumpfile ("test_site.vcd");
$dumpvars;
#1;
end

toysram_site site (

`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wbs_stb_i(wbs_stb_i),
.wbs_cyc_i(wbs_cyc_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_dat_i(wbs_dat_i),
.wbs_adr_i(wbs_adr_i),
.wbs_ack_o(wbs_ack_o),
.wbs_dat_o(wbs_dat_o),

// Logic Analyzer Signals
.la_data_in(la_data_in),
.la_data_out(la_data_out),
.la_oenb(la_oenb),


// IOs
.io_in(io_in),
.io_out(io_out),
.io_oeb(io_oeb),

// IRQ
.irq(irq)

);


endmodule

@ -0,0 +1,65 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Wed Jun 8 15:39:53 2022
[*]
[dumpfile] "/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco/test_ra_sdr_32x32.fst"
[dumpfile_mtime] "Wed Jun 8 15:03:44 2022"
[dumpfile_size] 4425
[savefile] "/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco/wtf_test_ra_sdr_32x32.gtkw"
[timestart] 19240
[size] 2088 1240
[pos] 218 58
*-12.000000 30000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] test_ra_sdr_32x32.
[treeopen] test_ra_sdr_32x32.ra.
[treeopen] test_ra_sdr_32x32.ra.array0.
[sst_width] 282
[signals_width] 312
[sst_expanded] 1
[sst_vpaned_height] 370
@28
test_ra_sdr_32x32.clk
@200
-WR 0
@28
test_ra_sdr_32x32.wr_enb_0
@22
test_ra_sdr_32x32.wr_adr_0[0:4]
test_ra_sdr_32x32.wr_dat_0[0:31]
@200
-RD 0
@28
test_ra_sdr_32x32.rd_enb_0
@22
test_ra_sdr_32x32.rd_adr_0[0:4]
test_ra_sdr_32x32.rd_dat_0[0:31]
@200
-RD 1
@28
test_ra_sdr_32x32.rd_enb_1
@22
test_ra_sdr_32x32.rd_adr_1[0:4]
test_ra_sdr_32x32.rd_dat_1[0:31]
@200
-RA
-RA[0]
@22
test_ra_sdr_32x32.ra.array0.ra[0].q[0:31]
test_ra_sdr_32x32.ra.array0.ra[1].q[0:31]
test_ra_sdr_32x32.ra.array0.ra[2].q[0:31]
test_ra_sdr_32x32.ra.array0.ra[3].q[0:31]
test_ra_sdr_32x32.ra.array0.ra[4].q[0:31]
test_ra_sdr_32x32.ra.array0.ra[5].q[0:31]
test_ra_sdr_32x32.ra.array0.ra[6].q[0:31]
@23
test_ra_sdr_32x32.ra.array0.ra[7].q[0:31]
@28
test_ra_sdr_32x32.ra.array0.wr0_a0
test_ra_sdr_32x32.ra.array0.wr0_a1
test_ra_sdr_32x32.ra.array0.wr0_a1_a2
test_ra_sdr_32x32.ra.array0.wr0_a1_na2
test_ra_sdr_32x32.ra.array0.wr0_a2
test_ra_sdr_32x32.ra.array0.wr0_a3
test_ra_sdr_32x32.ra.array0.wr0_a4
[pattern_trace] 1
[pattern_trace] 0

@ -0,0 +1,68 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Thu May 26 19:05:29 2022
[*]
[dumpfile] "/home/wtf/projects/toysram-opf/rtl/sim/coco/test_ra_sdr_64x72.fst"
[dumpfile_mtime] "Thu May 26 18:50:01 2022"
[dumpfile_size] 12003
[savefile] "/home/wtf/projects/toysram-opf/rtl/sim/coco/wtf_test_ra_sdr_64x72.gtkw"
[timestart] 89538
[size] 2088 1240
[pos] 218 58
*-10.000000 94187 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] test_ra_sdr_64x72.
[treeopen] test_ra_sdr_64x72.ra.
[treeopen] test_ra_sdr_64x72.ra.array2.
[sst_width] 282
[signals_width] 312
[sst_expanded] 1
[sst_vpaned_height] 370
@28
test_ra_sdr_64x72.clk
test_ra_sdr_64x72.reset
@200
-WR 0
@29
test_ra_sdr_64x72.wr_enb_0
@22
test_ra_sdr_64x72.wr_adr_0[0:5]
test_ra_sdr_64x72.wr_dat_0[0:71]
@200
-RD 0
@28
test_ra_sdr_64x72.rd_enb_0
@22
test_ra_sdr_64x72.rd_adr_0[0:5]
test_ra_sdr_64x72.rd_dat_0[0:71]
@200
-RD 1
@28
test_ra_sdr_64x72.rd_enb_1
@22
test_ra_sdr_64x72.rd_adr_1[0:5]
test_ra_sdr_64x72.rd_dat_1[0:71]
@200
-RA
@28
test_ra_sdr_64x72.ra.rd_enb_0_q
@22
test_ra_sdr_64x72.ra.rd_adr_0_q[0:5]
test_ra_sdr_64x72.ra.rd_dat_0_q[0:71]
@28
test_ra_sdr_64x72.ra.rd_enb_1_q
@22
test_ra_sdr_64x72.ra.rd_adr_1_q[0:5]
test_ra_sdr_64x72.ra.rd_dat_1_q[0:71]
@28
test_ra_sdr_64x72.ra.wr_enb_0_q
@22
test_ra_sdr_64x72.ra.wr_adr_0_q[0:5]
test_ra_sdr_64x72.ra.wr_dat_0_q[0:71]
@200
-RA[0]
@22
test_ra_sdr_64x72.ra.array0.ra[0].q[0:23]
test_ra_sdr_64x72.ra.array1.ra[0].q[0:23]
test_ra_sdr_64x72.ra.array2.ra[0].q[0:23]
[pattern_trace] 1
[pattern_trace] 0

@ -0,0 +1,138 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Mon Jun 13 17:02:24 2022
[*]
[dumpfile] "/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco/test_site.fst"
[dumpfile_mtime] "Mon Jun 13 16:51:29 2022"
[dumpfile_size] 408816
[savefile] "/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco/wtf_test_site.gtkw"
[timestart] 2034000
[size] 2048 1078
[pos] 206 125
*-18.000000 3035000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] test_site.
[treeopen] test_site.site.
[treeopen] test_site.site.ra_0.
[treeopen] test_site.site.ra_0.ra.
[sst_width] 204
[signals_width] 265
[sst_expanded] 1
[sst_vpaned_height] 314
@28
test_site.wb_clk_i
test_site.wb_rst_i
test_site.wbs_cyc_i
test_site.wbs_stb_i
test_site.wbs_we_i
@22
test_site.wbs_adr_i[31:0]
test_site.wbs_sel_i[3:0]
test_site.wbs_dat_i[31:0]
@28
test_site.wbs_ack_o
@22
test_site.wbs_dat_o[31:0]
test_site.la_data_in[127:0]
test_site.la_data_out[127:0]
test_site.la_oenb[127:0]
test_site.io_in[37:0]
test_site.io_oeb[37:0]
test_site.io_out[37:0]
@28
test_site.irq[2:0]
@200
-WB SLAVE
@22
test_site.site.wb.rd_dat[31:0]
@28
test_site.site.wb.rd_ack_q
@22
test_site.site.wb.rd_dat_q[31:0]
@200
-CFG
@22
test_site.site.cfg.cfg0_q[31:0]
@28
test_site.site.cfg.wb_cmd_val
test_site.site.cfg.cfg_cmd_val
test_site.site.cfg.ctl_cmd_val
test_site.site.cfg.ra0_cmd_val
@22
test_site.site.cfg.cmd_adr[31:0]
@28
test_site.site.cfg.cmd_we
@22
test_site.site.cfg.cmd_sel[3:0]
test_site.site.cfg.cmd_dat[31:0]
@200
-CTL
@22
test_site.site.ctl.io_in[37:0]
test_site.site.ctl.io_out[37:0]
test_site.site.ctl.io_oeb[37:0]
test_site.site.cfg.cfg0_q[31:0]
test_site.site.ctl.seq_q[4:0]
@28
test_site.site.ctl.ctl_cmd_val
test_site.site.ctl.ra0_cmd_val
test_site.site.ctl.adr_bist
test_site.site.ctl.adr_config
@22
test_site.site.ctl.cmd_adr[31:0]
@28
test_site.site.ctl.cmd_we
@22
test_site.site.ctl.cmd_sel[3:0]
test_site.site.ctl.cmd_dat[31:0]
@28
test_site.site.ctl.rd_ack
test_site.site.ctl.rdata_sel[2:0]
@22
test_site.site.ctl.rd_dat[31:0]
@28
test_site.site.ctl.ra0_r0_enb
@22
test_site.site.ctl.ra0_r0_adr[4:0]
test_site.site.ctl.ra0_r0_dat[31:0]
@28
test_site.site.ctl.ra0_r1_enb
@22
test_site.site.ctl.ra0_r1_adr[4:0]
test_site.site.ctl.ra0_r1_dat[31:0]
@28
test_site.site.ctl.ra0_w0_enb
@22
test_site.site.ctl.ra0_w0_adr[4:0]
test_site.site.ctl.ra0_w0_dat[31:0]
@28
test_site.site.ctl.test_enable
@22
test_site.site.ctl.scan_reg_q[127:0]
@28
test_site.site.ctl.scan_clk
@22
test_site.site.ctl.scan_config[16:0]
@28
test_site.site.ctl.scan_di
test_site.site.ctl.scan_do
test_site.site.ctl.io_ra0_clk
test_site.site.ctl.io_ra0_rst
@200
-RA0
@28
test_site.site.ra_0.clk
test_site.site.ra_0.ra.wr_enb_0_q
@22
test_site.site.ra_0.ra.wr_adr_0_q[0:4]
test_site.site.ra_0.ra.wr_dat_0_q[0:31]
@28
test_site.site.ra_0.ra.rd_enb_0_q
@22
test_site.site.ra_0.ra.rd_dat_0_q[0:31]
@28
test_site.site.ra_0.ra.rd_enb_1_q
@22
test_site.site.ra_0.ra.rd_dat_1_q[0:31]
test_site.site.ra_0.ra.array0.ra[0].q[0:31]
[pattern_trace] 1
[pattern_trace] 0

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# Utilities

import random

# printing

me = ' pys--. '
quiet = False
getSimTime = None

def msg(text='', lvl=0, name=None, init=None):
global me, quiet, getSimTime

if init is not None:
getSimTime = init
return

if quiet and lvl != 0:
return

if name is None:
name = me
if getSimTime is not None:
t,c = getSimTime()
else:
t,c = (0,0)
s = f'{t:08d}[{c:08d}] {name:>8}: '
pad = ' ' * len(s)

text = text + '\n'
lines = text.splitlines()
s = s + lines[0] + '\n'
for i in range(1, len(lines)):
s = s + pad
s = s + lines[i] + '\n'
print(s[0:-1])

# randoms

def intrandom(n):
return random.randint(0, n-1)

def hexrandom(w=16):
n = random.getrandbits(w*4)
return '{0:0{l}X}'.format(n, l=w)

def binrandom(w=32):
n = random.getrandbits(w)
return '{0:0>{l}b}'.format(n, l=w)

def randOK(freq):
v = random.randint(1,100) # 1 <= v <= 100
if freq == 0:
return False
else:
return v <= freq

# weights is either
# a simple list: return weighted index
# a list of tuple(val, weight): return weighted val
def randweighted(weights):

if len(weights) == 0:
return 0

if type(weights[0]) is tuple:
vals = []
tWeights = []
for i in range (0, len(weights)):
vals.append(weights[i][0])
tWeights.append(weights[i][1])
weights = tWeights
else:
vals = range(0, len(weights))

sum = 0
for i in range(0, len(weights)):
sum = sum + weights[i]
v = random.randint(0,sum-1)
weight = 0
for i in range(0, len(weights)):
weight = weight + weights[i]
if v < weight:
break

return vals[i]

# converters

def b2x(b, w=None):
if w is None:
rem = len(b) % 4
w = len(b)/4
if rem != 0:
w = w + 1
return '{0:0{l}X}'.format(int(b,2), l=w)

def x2b(x, w=None):
i = int(str(x),16)
if w is None:
return bin(i)[2:]
else:
return '{0:0>{l}s}'.format(bin(i)[2:], l=w)

def d2x(x, w=None):
#return hex(int(x)).split('x')[-1].upper()
if w is None:
return '{0:X}'.format(x)
else:
return '{0:0{l}X}'.format(x, l=w)

def x2d(i):
return int(i, 16)

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/home/wtf/projects/pyverilator_no_uart/pyverilator

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#!/usr/bin/python3

# pyverilator
# fixed internal sig parsing (cdata/wdata)
# 1. this should be based on init setting AND should be done even w/o trace on!!!
# in add_to_vcd_trace(self), time is bumped +5
# 2. should count cycs
# 3. add parm so clock can be set but NOT eval (for multiclock, only fastest evals)
# 4. how to access mem[][]??
# 5. not adding vectors to gtk - cuz 0:n?

import os, sys
import datetime
from optparse import OptionParser
from optparse import OptionGroup

import random
from random import randint

from pysutils import *

user = os.environ['USER']
binPath = os.path.dirname(os.path.realpath(__file__))

localPV = True
if localPV:
import os, sys
sys.path.append(os.path.join(binPath, 'pyverilator'))
import pyverilator

####################################################################
# Defaults

rtl = ['src']
model = 'sdr'

stopOnFail = True
verbose = False
vcd = False
seed = randint(1, int('8675309', 16))
runCycs = 100

#rangesRd = [(0,63), (0,63), (0,63), (0,63)]
rangesRd = [(0,7), (0,7), (0,7), (0,7)]
#rangesWr = [(0,63), (0,63)]
rangesWr = [(0,7), (0,7)]


####################################################################
# Process command line

usage = "Usage: %prog [options]"
parser = OptionParser(usage)

parser.add_option('-m', '--model', dest='model', help=f'sdr or ddr')
parser.add_option('-s', '--seed', dest='seed', help=f'initialize seed to n')
parser.add_option('-c', '--cycles', dest='runCycs', help=f'cycles to run, default={runCycs}')

parser.add_option('-t', '--trace', dest='trace', action='store_true', help=f'create wave file')