init
openpowerwtf
11 months ago
commit
f9d5f06f61
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## Cells needed for the Skywater test site
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We need to produce the necessary
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* Schematic
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* Layout
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* Logic and timing models for
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### Low level cells
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1) 10T SRAM
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a. WWL, RWL0, , RWL1
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b. (WBL WBL_B), RBL0, RBL1
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2) Local eval (NAND2 with 2 precharged inputs)
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a. PC_Left, PC_Right, In_Left, In_Right -> Q (output)
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3) LSDL state-holding latch (Latch with 2 dynamic inputs forming an 'Or')
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a. In_Left, In_Right, CLK -> Q (output)
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### Mid level cell
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Partially decode 2R1W 64Rx24 bit array). (Includes early/late output latch)
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Inputs:
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1) Clock*A0,Clock*~A0
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2) ~A1*~A2,~A1,*~A2, A1*~A2,A1*~A2,
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3) A3 ,~A3
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4) ~A4*~A5,~A4,*~A5, A14*~A5,A4*~A5,
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5) DataIn0..DI23
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6) Early and late Clock for LSDL state holding latch.
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Outputs:
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1) DataOut00..DO023
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2) DO10..DO123
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3) DO20..DO223
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4) DO30..DO323
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## Cells needed for the Skywater test site
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We need to produce the necessary
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* Schematic
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* Layout
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* Logic and timing models for
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### Low level cells
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1) 10T SRAM
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a. WWL, RWL0, , RWL1
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b. (WBL WBL_B), RBL0, RBL1
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2) Local eval (NAND2 with 2 precharged inputs)
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a. PC_Left, PC_Right, In_Left, In_Right -> Q (output)
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3) LSDL state-holding latch (Latch with 2 dynamic inputs forming an 'Or')
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a. In_Left, In_Right, CLK -> Q (output)
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### Mid level cell
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Partially decode 2R1W 64Rx24 bit array). (Includes early/late output latch)
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Inputs:
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1) Clock*A0,Clock*~A0
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2) ~A1*~A2,~A1,*~A2, A1*~A2,A1*~A2,
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3) A3 ,~A3
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4) ~A4*~A5,~A4,*~A5, A14*~A5,A4*~A5,
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5) DataIn0..DI23
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6) Early and late Clock for LSDL state holding latch.
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Outputs:
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1) DataOut00..DO023
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2) DO10..DO123
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3) DO20..DO223
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4) DO30..DO323
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# General Notes
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## SDR/DDR
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* logical wrappers instantiate hard array
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* SDR: use multiple hard array instances to add ports
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* DDR: use early/late pulses to double read/write ports
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### DDR Implementation
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* strobes are generated from clk based on configurable delay parameters
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## Test site arrays
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* 2R1W, SDR - this is the sdr hard array and simple logical wrapper using single clock
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* 4R2W, DDR - this is the ddr hard array and double-rate logical wrapper generating early/late pulses
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### Configuration options
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* SDR clock frequency (external to logical array)
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* DDR clock frequency (external to logical array)
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* SDR Pulse Control
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* DDR Pulse Control
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---
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project:
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description: "High-specific-bandwidth memory cell test site for 90nm"
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foundry: "SkyWater"
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git_url: "https://git.openpower.foundation/cores/toysram.git"
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organization: "Open POWER"
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organization_url: "http://openpowerfoundation.com"
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owner: "Bob Montoya"
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process: "SKY90"
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project_name: "ToySRAM"
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project_id: "00000000"
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tags:
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- "Open MPW"
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- "Custom Cell"
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- "Array"
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category: "Custom Cell"
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top_level_netlist: "verilog/gl/site.v"
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user_level_netlist: "verilog/gl/user_project_wrapper.v"
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version: "1.00"
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cover_image: "docs/img/bob.jpg"
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// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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/*
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*-------------------------------------------------------------
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*
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* user_project_wrapper
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*
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* This wrapper enumerates all of the pins available to the
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* user for the user project.
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*
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* An example user project is provided in this wrapper. The
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* example should be removed and replaced with the actual
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* user project.
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*
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*-------------------------------------------------------------
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*/
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module user_project_wrapper #(
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parameter BITS = 32
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)(
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`ifdef USE_POWER_PINS
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inout vdda1, // User area 1 3.3V supply
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inout vdda2, // User area 2 3.3V supply
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inout vssa1, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V supply
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inout vccd2, // User area 2 1.8v supply
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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`endif
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// Wishbone Slave ports (WB MI A)
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input wb_clk_i,
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input wb_rst_i,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output wbs_ack_o,
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output [31:0] wbs_dat_o,
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// Logic Analyzer Signals
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input [127:0] la_data_in,
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output [127:0] la_data_out,
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input [127:0] la_oen,
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// IOs
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input [`MPRJ_IO_PADS-1:0] io_in,
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output [`MPRJ_IO_PADS-1:0] io_out,
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output [`MPRJ_IO_PADS-1:0] io_oeb,
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// Analog (direct connection to GPIO pad---use with caution)
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// Note that analog I/O is not available on the 7 lowest-numbered
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// GPIO pads, and so the analog_io indexing is offset from the
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// GPIO indexing by 7.
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inout [`MPRJ_IO_PADS-8:0] analog_io,
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// Independent clock (on independent integer divider)
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input user_clock2
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);
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endmodule // user_project_wrapper
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# design and tech
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unit = test_sdr_2r1w_64x72_top
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# top directory
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export DESIGN_TOP = array
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# unit directory (log, objects, reports, results)
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export DESIGN_NICKNAME = array_$(unit)
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# macro
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export DESIGN_NAME = $(unit)
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#tech
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export PLATFORM = sky130hd
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# sources
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export VERILOG_FILES = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_TOP)/src/verilog/work/test_sdr_2r1w_64x72_top.v))
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export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_TOP)/constraint_$(unit).sdc
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$(info Source files:)
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$(info $(VERILOG_FILES))
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$(info ..................................................)
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# parms
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export PLACE_DENSITY ?= 0.50
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export ABC_CLOCK_PERIOD_IN_PS ?= 10
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# must be multiples of placement site (0.46 x 2.72)
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export DIE_AREA = 0 0 3011.160 4022.880
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export CORE_AREA = 5.520 10.880 3005.640 4012.000
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set clk_name clock
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set clk_period 10
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set input_delay_value 1
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set output_delay_value 1
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# define clock
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# nclk[0]: clk
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# nclk[1]: reset
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# nclk[2]: clk2x (fpga)
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# nclk[3]: clk4x (fpga)
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#set clkPort [lindex [get_ports $clk_name] 0] ;#wtf IS SELECTING 0 ALWAYS CORRECT??? tritoncts doesnt like this
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set clkPort [get_ports $clk_name]
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create_clock $clkPort -name clock -period $clk_period
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# apply clock to ins and outs
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set clk_index [lsearch [all_inputs] $clkPort]
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set all_inputs_wo_clk [lreplace [all_inputs] $clk_index $clk_index]
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set_input_delay $input_delay_value -clock [get_clocks clk] $all_inputs_wo_clk
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set_output_delay $output_delay_value -clock [get_clocks clk] [all_outputs]
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## Logical Array Wrapper
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* verilog is in rtl/src/array
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* parameter determines sim vs tech during rtl compile
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## Physical Array
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* custom cell(s) to be designed
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* custom/
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## Test Site
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* verilog is in rtl/src/site
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* supporting logic for test and debug through available Caravel connections
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## Verification
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* rtl/sim/coco
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## Caravel
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* to be incorporated into https://github.com/efabless/caravel flow as a user project area
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__pycache__/
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sim_build/
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build_32x32/
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build_site/
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# sdr ra
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# make -f Makefile.icarus build # rebuild and sim and fst
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# make -f Makefile.icarus run # sim and fst
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# make -f Makefile.icarus # sim
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#COCOTB_LOG_LEVEL=DEBUG
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#GPI_EXTRA=vpi
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#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM
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SIM_BUILD ?= build_32x32
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SIM ?= icarus
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# options
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#COCOTB_HDL_TIMEUNIT ?= 1ns
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#COCOTB_HDL_TIMEPRECISION ?= 1ps
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#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM
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# icarus
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VERILOG_ROOT = src
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COMPILE_ARGS = -I$(VERILOG_ROOT) -y$(VERILOG_ROOT)
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# other options
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# rtl
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TOPLEVEL_LANG = verilog
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# top-level to enable trace, etc.
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VERILOG_SOURCES = ./test_ra_sdr_32x32.v
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TOPLEVEL = test_ra_sdr_32x32
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# python test
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MODULE = tb
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TESTCASE = tb_32x32
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# cocotb make rules
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include $(shell cocotb-config --makefiles)/Makefile.sim
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build: clean sim fst
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run: sim fst
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fst:
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vcd2fst test_ra_sdr_32x32.vcd test_ra_sdr_32x32.fst
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#rm test_ra_sdr_32x32.vcd
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# sdr ra
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# make -f Makefile.icarus build # rebuild and sim and fst
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# make -f Makefile.icarus run # sim and fst
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# make -f Makefile.icarus # sim
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#COCOTB_LOG_LEVEL=DEBUG
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#GPI_EXTRA=vpi
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#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM
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#SIM_BUILD ?= build
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SIM ?= icarus
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# options
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#COCOTB_HDL_TIMEUNIT ?= 1ns
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#COCOTB_HDL_TIMEPRECISION ?= 1ps
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#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM
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# icarus
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VERILOG_ROOT = src
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COMPILE_ARGS = -I$(VERILOG_ROOT) -y$(VERILOG_ROOT)
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# other options
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# rtl
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TOPLEVEL_LANG = verilog
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# top-level to enable trace, etc.
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VERILOG_SOURCES = ./test_ra_sdr_64x72.v
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TOPLEVEL = test_ra_sdr_64x72
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# python test
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MODULE = tb
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TESTCASE = tb
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# cocotb make rules
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include $(shell cocotb-config --makefiles)/Makefile.sim
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||||
build: clean sim fst
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||||
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run: sim fst
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fst:
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vcd2fst test_ra_sdr_64x72.vcd test_ra_sdr_64x72.fst
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rm test_ra_sdr_64x72.vcd
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@ -0,0 +1,46 @@
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# sdr ra
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# make -f Makefile.icarus build # rebuild and sim and fst
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# make -f Makefile.icarus run # sim and fst
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||||
# make -f Makefile.icarus # sim
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||||
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||||
#COCOTB_LOG_LEVEL=DEBUG
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#GPI_EXTRA=vpi
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||||
|
||||
#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM
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||||
|
||||
SIM_BUILD ?= build_site
|
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SIM ?= icarus
|
||||
|
||||
# options
|
||||
#COCOTB_HDL_TIMEUNIT ?= 1ns
|
||||
#COCOTB_HDL_TIMEPRECISION ?= 1ps
|
||||
#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM
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||||
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||||
# icarus
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||||
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||||
VERILOG_ROOT = src
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||||
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||||
COMPILE_ARGS = -I$(VERILOG_ROOT)/../site -I$(VERILOG_ROOT)/../array -y$(VERILOG_ROOT)/../site -y$(VERILOG_ROOT)/../array
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||||
|
||||
# other options
|
||||
|
||||
# rtl
|
||||
TOPLEVEL_LANG = verilog
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||||
# top-level to enable trace, etc.
|
||||
VERILOG_SOURCES = ./test_site.v
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||||
TOPLEVEL = test_site
|
||||
|
||||
# python test
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||||
MODULE = tb
|
||||
TESTCASE = tb_site
|
||||
|
||||
# cocotb make rules
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
|
||||
build: clean sim fst
|
||||
|
||||
run: sim fst
|
||||
|
||||
fst:
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||||
vcd2fst test_site.vcd test_site.fst
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||||
rm test_site.vcd
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@ -0,0 +1,117 @@
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# OP Environment
|
||||
|
||||
import cocotb
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||||
from cocotb.triggers import Timer
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||||
from cocotb.handle import Force
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||||
from cocotb.handle import Release
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||||
|
||||
from dotmap import DotMap
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||||
|
||||
# ------------------------------------------------------------------------------------------------
|
||||
# Classes
|
||||
|
||||
class Sim(DotMap):
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||||
|
||||
def msg(self, m):
|
||||
self.dut._log.info(f'[{self.cycle:08d}] {m}') #wtf do multiline if /n in m
|
||||
|
||||
def __init__(self, dut, cfg=None):
|
||||
super().__init__()
|
||||
self.dut = dut
|
||||
# defaults
|
||||
self.memFiles = [] #wtf cmdline parm
|
||||
self.threads = 0
|
||||
self.resetCycle = 10
|
||||
self.hbCycles = 100
|
||||
self.clk2x = True
|
||||
self.clk4x = False
|
||||
self.resetAddr = 0xFFFFFFFC
|
||||
self.resetOp = 0x48000002
|
||||
self.maxCycles = 150
|
||||
self.memFiles = None
|
||||
self.config = DotMap()
|
||||
self.config.core = DotMap({
|
||||
'creditsLd': 1,
|
||||
'creditsSt': 1,
|
||||
'creditsLdStSingle': False
|
||||
})
|
||||
self.config.a2l2 = DotMap({
|
||||
'badAddr': [('E0','E0', 'IRW')]
|
||||
})
|
||||
# json
|
||||
if cfg is not None:
|
||||
pass
|
||||
|
||||
# runtime
|
||||
self.cycle = 0
|
||||
self.ok = True
|
||||
self.fail = None
|
||||
self.done = False
|
||||
|
||||
if self.threads is None:
|
||||
try:
|
||||
v = dut.an_ac_pm_thread_stop[1].value
|
||||
self.threads = 2
|
||||
except:
|
||||
self.threads = 1
|
||||
self.msg(f'Set threads={self.threads}.')
|
||||
|
||||
class TransQ(DotMap):
|
||||
def __init__(self):
|
||||
super().__init__()
|
||||
|
||||
class Memory(DotMap):
|
||||
|
||||
def __init__(self, sim, default=0, logStores=True):
|
||||
super().__init__()
|
||||
self.sim = sim
|
||||
self.data = {}
|
||||
self.le = False
|
||||
self.default = default # default word data for unloaded
|
||||
self.logStores = logStores
|
||||
|
||||
def loadFile(self, filename, format='ascii', addr=0, le=0):
|
||||
# format # binary, ascii, ascii w/addr
|
||||
# le: reverse bytes
|
||||
try:
|
||||
if format == 'ascii':
|
||||
with open(filename, 'r') as f:
|
||||
lines = f.readlines()
|
||||
for line in lines:
|
||||
self.data[addr] = int(line, 16) # key is int
|
||||
addr += 4
|
||||
elif format == 'binary':
|
||||
pass
|
||||
elif format == 'addrdata':
|
||||
pass
|
||||
except Exception as e:
|
||||
self.sim.msg(f'Error reading {filename}:\n{e}')
|
||||
raise IOError
|
||||
|
||||
# word-aligned byte address
|
||||
def read(self, addr):
|
||||
try:
|
||||
addr = addr + 0
|
||||
except:
|
||||
addr = int(addr, 16)
|
||||
if addr in self.data:
|
||||
return self.data[addr]
|
||||
else:
|
||||
return self.default
|
||||
|
||||
# word-aligned byte address + data
|
||||
def write(self, addr, data):
|
||||
try:
|
||||
addr = addr + 0
|
||||
except:
|
||||
addr = int(addr, 16)
|
||||
try:
|
||||
data = data + 0
|
||||
except:
|
||||
data = int(data, 16)
|
||||
if self.logStores:
|
||||
if addr not in self.data:
|
||||
self.sim.msg(f'Mem Update: @{addr:08X} XXXXXXXX->{data:08X}')
|
||||
else:
|
||||
self.sim.msg(f'Mem Update: @{addr:08X} {self.data[addr]:08X}->{data:08X}')
|
||||
self.data[addr] = data
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,174 @@
|
||||
# Cocotb + Icarus Verilog Array Sim
|
||||
|
||||
Cocotb test created from original pyverilator version - run random commands using 64x72 logical array.
|
||||
|
||||
## Array Wrapper
|
||||
|
||||
* compile and run
|
||||
|
||||
```
|
||||
make -f Makefile_sdr_32x32 build
|
||||
|
||||
```
|
||||
|
||||
* just run (tb.py changes, etc.)
|
||||
|
||||
```
|
||||
make -f Makefile_sdr_32x32 run
|
||||
|
||||
```
|
||||
|
||||
* results
|
||||
|
||||
```
|
||||
make -f Makefile_sdr_32x32 run >& sim_32x32.txt
|
||||
|
||||
MODULE=tb TESTCASE=tb_32x32 TOPLEVEL=test_ra_sdr_32x32 TOPLEVEL_LANG=verilog \
|
||||
/usr/local/bin/vvp -M /home/wtf/.local/lib/python3.8/site-packages/cocotb/libs -m libcocotbvpi_icarus build_32x32/sim.vvp
|
||||
-.--ns INFO cocotb.gpi ..mbed/gpi_embed.cpp:76 in set_program_name_in_venv Did not detect Python virtual environment. Using system-wide Python interpreter
|
||||
-.--ns INFO cocotb.gpi ../gpi/GpiCommon.cpp:99 in gpi_print_registered_impl VPI registered
|
||||
0.00ns INFO Running on Icarus Verilog version 12.0 (devel)
|
||||
0.00ns INFO Running tests with cocotb v1.7.0.dev0 from /home/wtf/.local/lib/python3.8/site-packages/cocotb
|
||||
0.00ns INFO Seeding Python random module with 1654704020
|
||||
0.00ns INFO Found test tb.tb_32x32
|
||||
0.00ns INFO running tb_32x32 (1/0)
|
||||
ToySRAM 32x32 array test
|
||||
0.00ns INFO [00000001] [00000001] Resetting...
|
||||
9.00ns INFO [00000010] [00000010] Releasing reset.
|
||||
25.00ns INFO [00000027] Initializing array...
|
||||
25.00ns INFO [00000027] Port=0 WR @00=00555500
|
||||
26.00ns INFO [00000028] Port=0 WR @01=01555501
|
||||
27.00ns INFO [00000029] Port=0 WR @02=02555502
|
||||
28.00ns INFO [00000030] Port=0 WR @03=03555503
|
||||
29.00ns INFO [00000031] Port=0 WR @04=04555504
|
||||
30.00ns INFO [00000032] Port=0 WR @05=05555505
|
||||
31.00ns INFO [00000033] Port=0 WR @06=06555506
|
||||
32.00ns INFO [00000034] Port=0 WR @07=07555507
|
||||
33.00ns INFO [00000035] Port=0 WR @08=08555508
|
||||
...
|
||||
10037.50ns INFO [00010039] Port=0 WR @12=6C6FD11E
|
||||
10038.50ns INFO [00010040] Port=0 WR @17=545B517F
|
||||
10039.50ns INFO [00010041] Port=0 RD @08
|
||||
10039.50ns INFO [00010041] Port=1 RD @0E
|
||||
10041.50ns INFO [00010043] * RD COMPARE * port=0 adr=08 act=BE99B13E exp=BE99B13E
|
||||
10041.50ns INFO [00010043] * RD COMPARE * port=1 adr=0E act=97A2D496 exp=97A2D496
|
||||
10041.50ns INFO [00010043] Port=0 WR @1A=76434F37
|
||||
10041.50ns INFO [00010043] Port=1 RD @0D
|
||||
10042.50ns INFO [00010044] Port=0 WR @12=069ECCCE
|
||||
10042.50ns INFO [00010044] Port=0 RD @13
|
||||
10043.50ns INFO [00010045] * RD COMPARE * port=1 adr=0D act=C1C0D7D8 exp=C1C0D7D8
|
||||
10043.50ns INFO [00010045] Port=0 WR @05=58E318E7
|
||||
10043.50ns INFO [00010045] Port=0 RD @10
|
||||
10043.50ns INFO [00010045] Port=1 RD @00
|
||||
10044.50ns INFO [00010046] * RD COMPARE * port=0 adr=13 act=1D975E90 exp=1D975E90
|
||||
10044.50ns INFO [00010046] Port=0 RD @14
|
||||
10044.50ns INFO [00010046] Port=1 RD @1D
|
||||
10045.50ns INFO [00010047] * RD COMPARE * port=0 adr=10 act=F82AB140 exp=F82AB140
|
||||
10045.50ns INFO [00010047] * RD COMPARE * port=1 adr=00 act=3C2E724D exp=3C2E724D
|
||||
10046.50ns INFO [00010048] * RD COMPARE * port=0 adr=14 act=1A27AA07 exp=1A27AA07
|
||||
10046.50ns INFO [00010048] * RD COMPARE * port=1 adr=1D act=5B9AE71C exp=5B9AE71C
|
||||
10047.50ns INFO [00010049] Quiescing...
|
||||
10057.00ns INFO [00010059] Done.
|
||||
10057.00ns INFO [00010059] Final State
|
||||
|
||||
Reads Port 0: 4005
|
||||
Reads Port 1: 4052
|
||||
Writes Port 0: 4055
|
||||
10057.00ns INFO [00010059] [00010059] You has opulence.
|
||||
10057.00ns INFO tb_32x32 passed
|
||||
10057.00ns INFO **************************************************************************************
|
||||
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
|
||||
**************************************************************************************
|
||||
** tb.tb_32x32 PASS 10057.00 8.54 1177.70 **
|
||||
**************************************************************************************
|
||||
** TESTS=0 PASS=1 FAIL=0 SKIP=0 10057.00 8.56 1174.42 **
|
||||
**************************************************************************************
|
||||
|
||||
VCD info: dumpfile test_ra_sdr_32x32.vcd opened for output.
|
||||
VCD warning: $dumpvars: Package ($unit) is not dumpable with VCD.
|
||||
make[1]: Leaving directory '/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco'
|
||||
vcd2fst test_ra_sdr_32x32.vcd test_ra_sdr_32x32.fst
|
||||
#rm test_ra_sdr_32x32.vcd
|
||||
|
||||
```
|
||||
|
||||
```
|
||||
gtkwave test_ra_sdr_32x32.fst wtf_test_ra_sdr_32x32.gtkw
|
||||
```
|
||||
|
||||
## Test Site
|
||||
|
||||
* compile and run
|
||||
|
||||
```
|
||||
make -f Makefile_site build
|
||||
|
||||
```
|
||||
|
||||
* just run (tb.py changes, etc.)
|
||||
|
||||
```
|
||||
make -f Makefile_site run
|
||||
|
||||
```
|
||||
|
||||
* results
|
||||
|
||||
```
|
||||
0.00ns INFO Running on Icarus Verilog version 12.0 (devel)
|
||||
0.00ns INFO Running tests with cocotb v1.7.0.dev0 from /home/wtf/.local/lib/python3.8/site-packages/cocotb
|
||||
0.00ns INFO Seeding Python random module with 1655136638
|
||||
0.00ns INFO Found test tb.tb_site
|
||||
0.00ns INFO running tb_site (1/0)
|
||||
ToySRAM site test
|
||||
VCD info: dumpfile test_site.vcd opened for output.
|
||||
VCD warning: $dumpvars: Package ($unit) is not dumpable with VCD.
|
||||
0.00ns INFO [00000001] Resetting...
|
||||
9.00ns INFO [00000010] Releasing reset.
|
||||
15.00ns INFO [00000017] Writing Port 0 @00100000 00=633212F3
|
||||
17.00ns INFO [00000019] Reading Port 0 @00100000 00
|
||||
22.00ns INFO [00000024] Read Data: 633212F3
|
||||
22.00ns INFO [00000024] Writing Port 0 @00100001 01=6A0278C9
|
||||
24.00ns INFO [00000026] Reading Port 0 @00100001 01
|
||||
29.00ns INFO [00000031] Read Data: 6A0278C9
|
||||
...
|
||||
1769.00ns INFO [00001770] Writing W0@15=08675309...
|
||||
1769.00ns INFO [00001770] Scanning in...
|
||||
1798.00ns INFO [00001800] ...tick...
|
||||
1898.00ns INFO [00001900] ...tick...
|
||||
1998.00ns INFO [00002000] ...tick...
|
||||
2075.00ns INFO [00002076] Blipping RA0 clk...
|
||||
2098.00ns INFO [00002100] ...tick...
|
||||
2175.00ns INFO [00002176] Reading R0@15, R1@16...
|
||||
2175.00ns INFO [00002176] Scanning in...
|
||||
2198.00ns INFO [00002200] ...tick...
|
||||
2298.00ns INFO [00002300] ...tick...
|
||||
2398.00ns INFO [00002400] ...tick...
|
||||
2481.00ns INFO [00002482] Blipping RA0 clk...
|
||||
2498.00ns INFO [00002500] ...tick...
|
||||
2581.00ns INFO [00002582] Blipping RA0 clk...
|
||||
2598.00ns INFO [00002600] ...tick...
|
||||
2681.00ns INFO [00002682] Blipping RA0 clk...
|
||||
2698.00ns INFO [00002700] ...tick...
|
||||
2781.00ns INFO [00002782] Scanning out...
|
||||
2798.00ns INFO [00002800] ...tick...
|
||||
2898.00ns INFO [00002900] ...tick...
|
||||
2998.00ns INFO [00003000] ...tick...
|
||||
3035.00ns INFO [00003036] ScanData=78433A984C075227A100000000000000
|
||||
3035.00ns INFO [00003036] r0 adr:0F
|
||||
3035.00ns INFO [00003036] r0 dat:08675309
|
||||
3035.00ns INFO [00003036] r1 adr:10
|
||||
3035.00ns INFO [00003036] r1 dat:1D489E84
|
||||
3035.00ns INFO [00003036] w0 adr:00
|
||||
3035.00ns INFO [00003036] w0 dat:00000000
|
||||
3035.00ns INFO [00003036] cfg:00000
|
||||
3035.00ns INFO [00003036] Done
|
||||
3044.00ns INFO tb_site passed
|
||||
3044.00ns INFO **************************************************************************************
|
||||
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
|
||||
**************************************************************************************
|
||||
** tb.tb_site PASS 3044.00 0.87 3517.25 **
|
||||
**************************************************************************************
|
||||
** TESTS=0 PASS=1 FAIL=0 SKIP=0 3044.00 0.89 3420.87 **
|
||||
**************************************************************************************
|
||||
```
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1 @@
|
||||
../../src/array
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
@ -0,0 +1,65 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
|
||||
[*] Wed Jun 8 15:39:53 2022
|
||||
[*]
|
||||
[dumpfile] "/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco/test_ra_sdr_32x32.fst"
|
||||
[dumpfile_mtime] "Wed Jun 8 15:03:44 2022"
|
||||
[dumpfile_size] 4425
|
||||
[savefile] "/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco/wtf_test_ra_sdr_32x32.gtkw"
|
||||
[timestart] 19240
|
||||
[size] 2088 1240
|
||||
[pos] 218 58
|
||||
*-12.000000 30000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] test_ra_sdr_32x32.
|
||||
[treeopen] test_ra_sdr_32x32.ra.
|
||||
[treeopen] test_ra_sdr_32x32.ra.array0.
|
||||
[sst_width] 282
|
||||
[signals_width] 312
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 370
|
||||
@28
|
||||
test_ra_sdr_32x32.clk
|
||||
@200
|
||||
-WR 0
|
||||
@28
|
||||
test_ra_sdr_32x32.wr_enb_0
|
||||
@22
|
||||
test_ra_sdr_32x32.wr_adr_0[0:4]
|
||||
test_ra_sdr_32x32.wr_dat_0[0:31]
|
||||
@200
|
||||
-RD 0
|
||||
@28
|
||||
test_ra_sdr_32x32.rd_enb_0
|
||||
@22
|
||||
test_ra_sdr_32x32.rd_adr_0[0:4]
|
||||
test_ra_sdr_32x32.rd_dat_0[0:31]
|
||||
@200
|
||||
-RD 1
|
||||
@28
|
||||
test_ra_sdr_32x32.rd_enb_1
|
||||
@22
|
||||
test_ra_sdr_32x32.rd_adr_1[0:4]
|
||||
test_ra_sdr_32x32.rd_dat_1[0:31]
|
||||
@200
|
||||
-RA
|
||||
-RA[0]
|
||||
@22
|
||||
test_ra_sdr_32x32.ra.array0.ra[0].q[0:31]
|
||||
test_ra_sdr_32x32.ra.array0.ra[1].q[0:31]
|
||||
test_ra_sdr_32x32.ra.array0.ra[2].q[0:31]
|
||||
test_ra_sdr_32x32.ra.array0.ra[3].q[0:31]
|
||||
test_ra_sdr_32x32.ra.array0.ra[4].q[0:31]
|
||||
test_ra_sdr_32x32.ra.array0.ra[5].q[0:31]
|
||||
test_ra_sdr_32x32.ra.array0.ra[6].q[0:31]
|
||||
@23
|
||||
test_ra_sdr_32x32.ra.array0.ra[7].q[0:31]
|
||||
@28
|
||||
test_ra_sdr_32x32.ra.array0.wr0_a0
|
||||
test_ra_sdr_32x32.ra.array0.wr0_a1
|
||||
test_ra_sdr_32x32.ra.array0.wr0_a1_a2
|
||||
test_ra_sdr_32x32.ra.array0.wr0_a1_na2
|
||||
test_ra_sdr_32x32.ra.array0.wr0_a2
|
||||
test_ra_sdr_32x32.ra.array0.wr0_a3
|
||||
test_ra_sdr_32x32.ra.array0.wr0_a4
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
@ -0,0 +1,68 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
|
||||
[*] Thu May 26 19:05:29 2022
|
||||
[*]
|
||||
[dumpfile] "/home/wtf/projects/toysram-opf/rtl/sim/coco/test_ra_sdr_64x72.fst"
|
||||
[dumpfile_mtime] "Thu May 26 18:50:01 2022"
|
||||
[dumpfile_size] 12003
|
||||
[savefile] "/home/wtf/projects/toysram-opf/rtl/sim/coco/wtf_test_ra_sdr_64x72.gtkw"
|
||||
[timestart] 89538
|
||||
[size] 2088 1240
|
||||
[pos] 218 58
|
||||
*-10.000000 94187 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] test_ra_sdr_64x72.
|
||||
[treeopen] test_ra_sdr_64x72.ra.
|
||||
[treeopen] test_ra_sdr_64x72.ra.array2.
|
||||
[sst_width] 282
|
||||
[signals_width] 312
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 370
|
||||
@28
|
||||
test_ra_sdr_64x72.clk
|
||||
test_ra_sdr_64x72.reset
|
||||
@200
|
||||
-WR 0
|
||||
@29
|
||||
test_ra_sdr_64x72.wr_enb_0
|
||||
@22
|
||||
test_ra_sdr_64x72.wr_adr_0[0:5]
|
||||
test_ra_sdr_64x72.wr_dat_0[0:71]
|
||||
@200
|
||||
-RD 0
|
||||
@28
|
||||
test_ra_sdr_64x72.rd_enb_0
|
||||
@22
|
||||
test_ra_sdr_64x72.rd_adr_0[0:5]
|
||||
test_ra_sdr_64x72.rd_dat_0[0:71]
|
||||
@200
|
||||
-RD 1
|
||||
@28
|
||||
test_ra_sdr_64x72.rd_enb_1
|
||||
@22
|
||||
test_ra_sdr_64x72.rd_adr_1[0:5]
|
||||
test_ra_sdr_64x72.rd_dat_1[0:71]
|
||||
@200
|
||||
-RA
|
||||
@28
|
||||
test_ra_sdr_64x72.ra.rd_enb_0_q
|
||||
@22
|
||||
test_ra_sdr_64x72.ra.rd_adr_0_q[0:5]
|
||||
test_ra_sdr_64x72.ra.rd_dat_0_q[0:71]
|
||||
@28
|
||||
test_ra_sdr_64x72.ra.rd_enb_1_q
|
||||
@22
|
||||
test_ra_sdr_64x72.ra.rd_adr_1_q[0:5]
|
||||
test_ra_sdr_64x72.ra.rd_dat_1_q[0:71]
|
||||
@28
|
||||
test_ra_sdr_64x72.ra.wr_enb_0_q
|
||||
@22
|
||||
test_ra_sdr_64x72.ra.wr_adr_0_q[0:5]
|
||||
test_ra_sdr_64x72.ra.wr_dat_0_q[0:71]
|
||||
@200
|
||||
-RA[0]
|
||||
@22
|
||||
test_ra_sdr_64x72.ra.array0.ra[0].q[0:23]
|
||||
test_ra_sdr_64x72.ra.array1.ra[0].q[0:23]
|
||||
test_ra_sdr_64x72.ra.array2.ra[0].q[0:23]
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
@ -0,0 +1,138 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
|
||||
[*] Mon Jun 13 17:02:24 2022
|
||||
[*]
|
||||
[dumpfile] "/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco/test_site.fst"
|
||||
[dumpfile_mtime] "Mon Jun 13 16:51:29 2022"
|
||||
[dumpfile_size] 408816
|
||||
[savefile] "/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco/wtf_test_site.gtkw"
|
||||
[timestart] 2034000
|
||||
[size] 2048 1078
|
||||
[pos] 206 125
|
||||
*-18.000000 3035000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] test_site.
|
||||
[treeopen] test_site.site.
|
||||
[treeopen] test_site.site.ra_0.
|
||||
[treeopen] test_site.site.ra_0.ra.
|
||||
[sst_width] 204
|
||||
[signals_width] 265
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 314
|
||||
@28
|
||||
test_site.wb_clk_i
|
||||
test_site.wb_rst_i
|
||||
test_site.wbs_cyc_i
|
||||
test_site.wbs_stb_i
|
||||
test_site.wbs_we_i
|
||||
@22
|
||||
test_site.wbs_adr_i[31:0]
|
||||
test_site.wbs_sel_i[3:0]
|
||||
test_site.wbs_dat_i[31:0]
|
||||
@28
|
||||
test_site.wbs_ack_o
|
||||
@22
|
||||
test_site.wbs_dat_o[31:0]
|
||||
test_site.la_data_in[127:0]
|
||||
test_site.la_data_out[127:0]
|
||||
test_site.la_oenb[127:0]
|
||||
test_site.io_in[37:0]
|
||||
test_site.io_oeb[37:0]
|
||||
test_site.io_out[37:0]
|
||||
@28
|
||||
test_site.irq[2:0]
|
||||
@200
|
||||
-WB SLAVE
|
||||
@22
|
||||
test_site.site.wb.rd_dat[31:0]
|
||||
@28
|
||||
test_site.site.wb.rd_ack_q
|
||||
@22
|
||||
test_site.site.wb.rd_dat_q[31:0]
|
||||
@200
|
||||
-CFG
|
||||
@22
|
||||
test_site.site.cfg.cfg0_q[31:0]
|
||||
@28
|
||||
test_site.site.cfg.wb_cmd_val
|
||||
test_site.site.cfg.cfg_cmd_val
|
||||
test_site.site.cfg.ctl_cmd_val
|
||||
test_site.site.cfg.ra0_cmd_val
|
||||
@22
|
||||
test_site.site.cfg.cmd_adr[31:0]
|
||||
@28
|
||||
test_site.site.cfg.cmd_we
|
||||
@22
|
||||
test_site.site.cfg.cmd_sel[3:0]
|
||||
test_site.site.cfg.cmd_dat[31:0]
|
||||
@200
|
||||
-CTL
|
||||
@22
|
||||
test_site.site.ctl.io_in[37:0]
|
||||
test_site.site.ctl.io_out[37:0]
|
||||
test_site.site.ctl.io_oeb[37:0]
|
||||
test_site.site.cfg.cfg0_q[31:0]
|
||||
test_site.site.ctl.seq_q[4:0]
|
||||
@28
|
||||
test_site.site.ctl.ctl_cmd_val
|
||||
test_site.site.ctl.ra0_cmd_val
|
||||
test_site.site.ctl.adr_bist
|
||||
test_site.site.ctl.adr_config
|
||||
@22
|
||||
test_site.site.ctl.cmd_adr[31:0]
|
||||
@28
|
||||
test_site.site.ctl.cmd_we
|
||||
@22
|
||||
test_site.site.ctl.cmd_sel[3:0]
|
||||
test_site.site.ctl.cmd_dat[31:0]
|
||||
@28
|
||||
test_site.site.ctl.rd_ack
|
||||
test_site.site.ctl.rdata_sel[2:0]
|
||||
@22
|
||||
test_site.site.ctl.rd_dat[31:0]
|
||||
@28
|
||||
test_site.site.ctl.ra0_r0_enb
|
||||
@22
|
||||
test_site.site.ctl.ra0_r0_adr[4:0]
|
||||
test_site.site.ctl.ra0_r0_dat[31:0]
|
||||
@28
|
||||
test_site.site.ctl.ra0_r1_enb
|
||||
@22
|
||||
test_site.site.ctl.ra0_r1_adr[4:0]
|
||||
test_site.site.ctl.ra0_r1_dat[31:0]
|
||||
@28
|
||||
test_site.site.ctl.ra0_w0_enb
|
||||
@22
|
||||
test_site.site.ctl.ra0_w0_adr[4:0]
|
||||
test_site.site.ctl.ra0_w0_dat[31:0]
|
||||
@28
|
||||
test_site.site.ctl.test_enable
|
||||
@22
|
||||
test_site.site.ctl.scan_reg_q[127:0]
|
||||
@28
|
||||
test_site.site.ctl.scan_clk
|
||||
@22
|
||||
test_site.site.ctl.scan_config[16:0]
|
||||
@28
|
||||
test_site.site.ctl.scan_di
|
||||
test_site.site.ctl.scan_do
|
||||
test_site.site.ctl.io_ra0_clk
|
||||
test_site.site.ctl.io_ra0_rst
|
||||
@200
|
||||
-RA0
|
||||
@28
|
||||
test_site.site.ra_0.clk
|
||||
test_site.site.ra_0.ra.wr_enb_0_q
|
||||
@22
|
||||
test_site.site.ra_0.ra.wr_adr_0_q[0:4]
|
||||
test_site.site.ra_0.ra.wr_dat_0_q[0:31]
|
||||
@28
|
||||
test_site.site.ra_0.ra.rd_enb_0_q
|
||||
@22
|
||||
test_site.site.ra_0.ra.rd_dat_0_q[0:31]
|
||||
@28
|
||||
test_site.site.ra_0.ra.rd_enb_1_q
|
||||
@22
|
||||
test_site.site.ra_0.ra.rd_dat_1_q[0:31]
|
||||
test_site.site.ra_0.ra.array0.ra[0].q[0:31]
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,113 @@
|
||||
# Utilities
|
||||
|
||||
import random
|
||||
|
||||
# printing
|
||||
|
||||
me = ' pys--. '
|
||||
quiet = False
|
||||
getSimTime = None
|
||||
|
||||
def msg(text='', lvl=0, name=None, init=None):
|
||||
global me, quiet, getSimTime
|
||||
|
||||
if init is not None:
|
||||
getSimTime = init
|
||||
return
|
||||
|
||||
if quiet and lvl != 0:
|
||||
return
|
||||
|
||||
if name is None:
|
||||
name = me
|
||||
if getSimTime is not None:
|
||||
t,c = getSimTime()
|
||||
else:
|
||||
t,c = (0,0)
|
||||
s = f'{t:08d}[{c:08d}] {name:>8}: '
|
||||
pad = ' ' * len(s)
|
||||
|
||||
text = text + '\n'
|
||||
lines = text.splitlines()
|
||||
s = s + lines[0] + '\n'
|
||||
for i in range(1, len(lines)):
|
||||
s = s + pad
|
||||
s = s + lines[i] + '\n'
|
||||
print(s[0:-1])
|
||||
|
||||
# randoms
|
||||
|
||||
def intrandom(n):
|
||||
return random.randint(0, n-1)
|
||||
|
||||
def hexrandom(w=16):
|
||||
n = random.getrandbits(w*4)
|
||||
return '{0:0{l}X}'.format(n, l=w)
|
||||
|
||||
def binrandom(w=32):
|
||||
n = random.getrandbits(w)
|
||||
return '{0:0>{l}b}'.format(n, l=w)
|
||||
|
||||
def randOK(freq):
|
||||
v = random.randint(1,100) # 1 <= v <= 100
|
||||
if freq == 0:
|
||||
return False
|
||||
else:
|
||||
return v <= freq
|
||||
|
||||
# weights is either
|
||||
# a simple list: return weighted index
|
||||
# a list of tuple(val, weight): return weighted val
|
||||
def randweighted(weights):
|
||||
|
||||
if len(weights) == 0:
|
||||
return 0
|
||||
|
||||
if type(weights[0]) is tuple:
|
||||
vals = []
|
||||
tWeights = []
|
||||
for i in range (0, len(weights)):
|
||||
vals.append(weights[i][0])
|
||||
tWeights.append(weights[i][1])
|
||||
weights = tWeights
|
||||
else:
|
||||
vals = range(0, len(weights))
|
||||
|
||||
sum = 0
|
||||
for i in range(0, len(weights)):
|
||||
sum = sum + weights[i]
|
||||
v = random.randint(0,sum-1)
|
||||
weight = 0
|
||||
for i in range(0, len(weights)):
|
||||
weight = weight + weights[i]
|
||||
if v < weight:
|
||||
break
|
||||
|
||||
return vals[i]
|
||||
|
||||
# converters
|
||||
|
||||
def b2x(b, w=None):
|
||||
if w is None:
|
||||
rem = len(b) % 4
|
||||
w = len(b)/4
|
||||
if rem != 0:
|
||||
w = w + 1
|
||||
return '{0:0{l}X}'.format(int(b,2), l=w)
|
||||
|
||||
def x2b(x, w=None):
|
||||
i = int(str(x),16)
|
||||
if w is None:
|
||||
return bin(i)[2:]
|
||||
else:
|
||||
return '{0:0>{l}s}'.format(bin(i)[2:], l=w)
|
||||
|
||||
def d2x(x, w=None):
|
||||
#return hex(int(x)).split('x')[-1].upper()
|
||||
if w is None:
|
||||
return '{0:X}'.format(x)
|
||||
else:
|
||||
return '{0:0{l}X}'.format(x, l=w)
|
||||
|
||||
def x2d(i):
|
||||
return int(i, 16)
|
||||
@ -0,0 +1 @@
|
||||
/home/wtf/projects/pyverilator_no_uart/pyverilator
|
||||
@ -0,0 +1,444 @@
|
||||
#!/usr/bin/python3
|
||||
|
||||
# pyverilator
|
||||
# fixed internal sig parsing (cdata/wdata)
|
||||
# 1. this should be based on init setting AND should be done even w/o trace on!!!
|
||||
# in add_to_vcd_trace(self), time is bumped +5
|
||||
# 2. should count cycs
|
||||
# 3. add parm so clock can be set but NOT eval (for multiclock, only fastest evals)
|
||||
# 4. how to access mem[][]??
|
||||
# 5. not adding vectors to gtk - cuz 0:n?
|
||||
|
||||
import os, sys
|
||||
import datetime
|
||||
from optparse import OptionParser
|
||||
from optparse import OptionGroup
|
||||
|
||||
import random
|
||||
from random import randint
|
||||
|
||||
from pysutils import *
|
||||
|
||||
user = os.environ['USER']
|
||||
binPath = os.path.dirname(os.path.realpath(__file__))
|
||||
|
||||
localPV = True
|
||||
if localPV:
|
||||
import os, sys
|
||||
sys.path.append(os.path.join(binPath, 'pyverilator'))
|
||||
import pyverilator
|
||||
|
||||
####################################################################
|
||||
# Defaults
|
||||
|
||||
rtl = ['src']
|
||||
model = 'sdr'
|
||||
|
||||
stopOnFail = True
|
||||
verbose = False
|
||||
vcd = False
|
||||
seed = randint(1, int('8675309', 16))
|
||||
runCycs = 100
|
||||
|
||||
#rangesRd = [(0,63), (0,63), (0,63), (0,63)]
|
||||
rangesRd = [(0,7), (0,7), (0,7), (0,7)]
|
||||
#rangesWr = [(0,63), (0,63)]
|
||||
rangesWr = [(0,7), (0,7)]
|
||||
|
||||
|
||||
####################################################################
|
||||
# Process command line
|
||||
|
||||
usage = "Usage: %prog [options]"
|
||||
parser = OptionParser(usage)
|
||||
|
||||
parser.add_option('-m', '--model', dest='model', help=f'sdr or ddr')
|
||||
parser.add_option('-s', '--seed', dest='seed', help=f'initialize seed to n')
|
||||
parser.add_option('-c', '--cycles', dest='runCycs', help=f'cycles to run, default={runCycs}')
|
||||
|
||||
parser.add_option('-t', '--trace', dest='trace', action='store_true', help=f'create wave file')
|
||||