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21 lines
687 B
Plaintext
21 lines
687 B
Plaintext
set clk_name clock
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set clk_period 10
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set input_delay_value 1
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set output_delay_value 1
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# define clock
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# nclk[0]: clk
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# nclk[1]: reset
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# nclk[2]: clk2x (fpga)
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# nclk[3]: clk4x (fpga)
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#set clkPort [lindex [get_ports $clk_name] 0] ;#wtf IS SELECTING 0 ALWAYS CORRECT??? tritoncts doesnt like this
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set clkPort [get_ports $clk_name]
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create_clock $clkPort -name clock -period $clk_period
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# apply clock to ins and outs
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set clk_index [lsearch [all_inputs] $clkPort]
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set all_inputs_wo_clk [lreplace [all_inputs] $clk_index $clk_index]
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set_input_delay $input_delay_value -clock [get_clocks clk] $all_inputs_wo_clk
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set_output_delay $output_delay_value -clock [get_clocks clk] [all_outputs]
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