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// © IBM Corp. 2021
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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`timescale 1 ns / 1 ns
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`include "../toysram.vh"
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// configuration macro
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// Manages config registers and routes cmd val
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module cfg #(
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parameter CFG0_INIT = 'h00000000,
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parameter ADDR_MASK = 'hFFFF0000,
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parameter CFG_ADDR = 'h00000000,
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parameter CTL_ADDR = 'h00010000,
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parameter RA0_ADDR = 'h00100000
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)(
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`ifdef USE_POWER_PINS
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inout vccd1, // User area 1 1.8V supply
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inout vssd1, // User area 1 digital ground
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`endif
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input clk,
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input rst,
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input wb_cmd_val,
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input [31:0] wb_cmd_adr,
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input wb_cmd_we,
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input [3:0] wb_cmd_sel,
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input [31:0] wb_cmd_dat,
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output wb_rd_ack,
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output [31:0] wb_rd_dat,
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output [31:0] cmd_adr,
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output cmd_we,
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output [3:0] cmd_sel,
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output [31:0] cmd_dat,
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output ctl_cmd_val,
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output cfg_cmd_val,
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output ra0_cmd_val,
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input ctl_rd_ack,
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input [31:0] ctl_rd_dat
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);
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reg [7:0] seq_q;
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wire [7:0] seq_d;
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reg [31:0] cfg0_q;
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wire [31:0] cfg0_d;
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// FF
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always @(posedge clk) begin
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if (rst) begin
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seq_q <= 'hFF;
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cfg0_q <= CFG0_INIT;
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end else begin
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seq_q <= seq_d;
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cfg0_q <= cfg0_d;
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end
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end
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// Common
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assign cmd_adr = wb_cmd_adr;
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assign cmd_we = wb_cmd_we;
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assign cmd_sel = wb_cmd_sel;
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assign cmd_dat = wb_cmd_dat;
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// Macro Routing
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assign cfg_cmd_val = wb_cmd_val & ((wb_cmd_adr & ADDR_MASK) == (CFG_ADDR & ADDR_MASK));
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assign cfg0_d = cfg_cmd_val & cmd_we ? cmd_dat : cfg0_q;
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assign ctl_cmd_val = wb_cmd_val & ((wb_cmd_adr & ADDR_MASK) == (CTL_ADDR & ADDR_MASK));
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assign ra0_cmd_val = wb_cmd_val & ((wb_cmd_adr & ADDR_MASK) == (RA0_ADDR & ADDR_MASK));
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assign wb_rd_ack = ctl_rd_ack;
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assign wb_rd_dat = ctl_rd_dat;
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endmodule
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