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47 lines
923 B
Plaintext
47 lines
923 B
Plaintext
# sdr ra
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# make -f Makefile.icarus build # rebuild and sim and fst
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# make -f Makefile.icarus run # sim and fst
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# make -f Makefile.icarus # sim
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#COCOTB_LOG_LEVEL=DEBUG
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#GPI_EXTRA=vpi
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#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM
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SIM_BUILD ?= build_site
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SIM ?= icarus
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# options
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#COCOTB_HDL_TIMEUNIT ?= 1ns
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#COCOTB_HDL_TIMEPRECISION ?= 1ps
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#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM
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# icarus
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VERILOG_ROOT = src
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COMPILE_ARGS = -I$(VERILOG_ROOT)/../site -I$(VERILOG_ROOT)/../array -y$(VERILOG_ROOT)/../site -y$(VERILOG_ROOT)/../array
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# other options
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# rtl
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TOPLEVEL_LANG = verilog
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# top-level to enable trace, etc.
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VERILOG_SOURCES = ./test_site.v
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TOPLEVEL = test_site
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# python test
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MODULE = tb
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TESTCASE = tb_site
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# cocotb make rules
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include $(shell cocotb-config --makefiles)/Makefile.sim
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build: clean sim fst
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run: sim fst
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fst:
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vcd2fst test_site.vcd test_site.fst
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rm test_site.vcd
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