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// © IBM Corp. 2021
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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`timescale 1 ns / 1 ns
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`include "../toysram.vh"
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// Wishbone slave macro
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// Bridges internal read/write commands to/from Wishbone.
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module wb_slave (
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`ifdef USE_POWER_PINS
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inout vccd1,
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inout vssd1,
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`endif
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input clk,
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input rst,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output wbs_ack_o,
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output [31:0] wbs_dat_o,
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output cmd_val,
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output [31:0] cmd_adr,
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output cmd_we,
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output [3:0] cmd_sel,
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output [31:0] cmd_dat,
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input rd_ack,
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input [31:0] rd_dat
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);
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reg cmd_val_q;
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wire cmd_val_d;
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reg [31:0] cmd_adr_q;
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wire [31:0] cmd_adr_d;
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reg cmd_we_q;
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wire cmd_we_d;
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reg [3:0] cmd_sel_q;
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wire [3:0] cmd_sel_d;
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reg [31:0] cmd_dat_q;
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wire [31:0] cmd_dat_d;
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reg rd_ack_q;
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wire rd_ack_d;
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reg [31:0] rd_dat_q;
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wire [31:0] rd_dat_d;
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wire stall;
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wire base_match;
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// FF
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always @(posedge clk) begin
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if (rst) begin
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cmd_val_q <= 1'b0;
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cmd_adr_q <= 31'h0;
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cmd_we_q <= 1'b0;
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cmd_sel_q <= 4'b0;
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cmd_dat_q <= 32'h0;
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rd_ack_q <= 1'b0;
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rd_dat_q <= 32'h0;
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end else begin
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cmd_val_q <= cmd_val_d;
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cmd_adr_q <= cmd_adr_d;
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cmd_we_q <= cmd_we_d;
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cmd_sel_q <= cmd_sel_d;
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cmd_dat_q <= cmd_dat_d;
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rd_ack_q <= rd_ack_d;
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rd_dat_q <= rd_dat_d;
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end
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end
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// WB
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assign stall = 'b0;
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assign base_match = 'b1;
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assign cmd_val_d = base_match & wbs_stb_i & ~stall;
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assign cmd_adr_d = wbs_adr_i[27:0];
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assign cmd_we_d = wbs_we_i;
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assign cmd_sel_d = wbs_sel_i;
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assign cmd_dat_d = wbs_dat_i;
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assign wbs_ack_o = rd_ack_q | (cmd_val_q & cmd_we_q); // block with reset?
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assign wbs_dat_o = rd_dat_q;
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// Outputs
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assign cmd_val = cmd_val_q;
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assign cmd_adr = cmd_adr_q;
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assign cmd_we = cmd_we_q;
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assign cmd_sel = cmd_sel_q;
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assign cmd_dat = cmd_dat_q;
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// Inputs
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assign rd_ack_d = rd_ack;
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assign rd_dat_d = rd_dat;
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endmodule |