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// © IBM Corp. 2021
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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// Test array (DDR)
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// 64 word 72 bit array
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// LCB for strobe generation
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// Config, BIST, etc.
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`timescale 1 ns / 1 ns
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`include "toysram.vh"
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module test_ra_ddr (
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clk,
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clk2x,
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reset,
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cfg_wr,
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cfg_dat,
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bist_ctl,
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bist_status,
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rd_enb_0,
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rd_adr_0,
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rd_dat_0,
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rd_enb_1,
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rd_adr_1,
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rd_dat_1,
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rd_enb_2,
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rd_adr_2,
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rd_dat_2,
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rd_enb_3,
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rd_adr_3,
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rd_dat_3,
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wr_enb_0,
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wr_adr_0,
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wr_dat_0,
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wr_enb_1,
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wr_adr_1,
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wr_dat_1
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);
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input clk;
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input clk2x;
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input reset;
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input cfg_wr;
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input [0:`LCBDDR_CONFIGWIDTH-1] cfg_dat;
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input [0:31] bist_ctl;
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output [0:31] bist_status;
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input rd_enb_0;
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input [0:5] rd_adr_0;
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output [0:71] rd_dat_0;
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input rd_enb_1;
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input [0:5] rd_adr_1;
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output [0:71] rd_dat_1;
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input rd_enb_2;
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input [0:5] rd_adr_2;
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output [0:71] rd_dat_2;
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input rd_enb_3;
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input [0:5] rd_adr_3;
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output [0:71] rd_dat_3;
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input wr_enb_0;
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input [0:5] wr_adr_0;
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input [0:71] wr_dat_0;
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input wr_enb_1;
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input [0:5] wr_adr_1;
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input [0:71] wr_dat_1;
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wire strobe;
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wire el_sel;
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wire [0:`LCBDDR_CONFIGWIDTH-1] cfg;
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wire mux_rd0_enb;
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wire [0:5] mux_rd0_adr;
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wire mux_rd1_enb;
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wire [0:5] mux_rd1_adr;
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wire mux_rd2_enb;
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wire [0:5] mux_rd2_adr;
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wire mux_rd3_enb;
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wire [0:5] mux_rd3_adr;
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wire mux_wr0_enb;
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wire [0:5] mux_wr0_adr;
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wire [0:71] mux_wr0_dat;
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wire mux_wr1_enb;
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wire [0:5] mux_wr1_adr;
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wire [0:71] mux_wr1_dat;
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ra_lcb_ddr lcb (
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.clk (clk2x),
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.reset (reset),
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.cfg (cfg),
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.strobe (strobe),
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.el_sel (el_sel)
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);
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ra_cfg_ddr #(.INIT(-1)) cfig (
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.clk (clk),
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.reset (reset),
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.cfg_wr (cfg_wr),
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.cfg_dat (cfg_dat),
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.cfg (cfg)
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);
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ra_bist_ddr bist (
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.clk (clk),
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.reset (reset),
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.ctl (bist_ctl),
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.status (bist_status),
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.rd0_enb_in (rd_enb_0),
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.rd0_adr_in (rd_adr_0),
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.rd0_dat (rd_dat_0),
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.rd1_enb_in (rd_enb_1),
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.rd1_adr_in (rd_adr_1),
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.rd1_dat (rd_dat_1),
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.rd2_enb_in (rd_enb_2),
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.rd2_adr_in (rd_adr_2),
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.rd2_dat (rd_dat_2),
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.rd3_enb_in (rd_enb_3),
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.rd3_adr_in (rd_adr_3),
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.rd3_dat (rd_dat_3),
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.wr0_enb_in (wr_enb_0),
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.wr0_adr_in (wr_adr_0),
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.wr0_dat_in (wr_dat_0),
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.wr1_enb_in (wr_enb_1),
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.wr1_adr_in (wr_adr_1),
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.wr1_dat_in (wr_dat_1),
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.rd0_enb_out (mux_rd0_enb),
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.rd0_adr_out (mux_rd0_adr),
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.rd1_enb_out (mux_rd1_enb),
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.rd1_adr_out (mux_rd1_adr),
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.rd2_enb_out (mux_rd2_enb),
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.rd2_adr_out (mux_rd2_adr),
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.rd3_enb_out (mux_rd3_enb),
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.rd3_adr_out (mux_rd3_adr),
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.wr0_enb_out (mux_wr0_enb),
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.wr0_adr_out (mux_wr0_adr),
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.wr0_dat_out (mux_wr0_dat),
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.wr1_enb_out (mux_wr1_enb),
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.wr1_adr_out (mux_wr1_adr),
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.wr1_dat_out (mux_wr1_dat)
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);
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ra_4r2w_64x72_ddr ra (
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.clk (clk),
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.reset (reset),
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.strobe (strobe),
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.el_sel (el_sel),
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.rd_enb_0 (mux_rd0_enb),
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.rd_adr_0 (mux_rd0_adr),
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.rd_dat_0 (rd_dat_0),
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.rd_enb_1 (mux_rd1_enb),
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.rd_adr_1 (mux_rd1_adr),
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.rd_dat_1 (rd_dat_1),
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.rd_enb_2 (mux_rd2_enb),
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.rd_adr_2 (mux_rd2_adr),
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.rd_dat_2 (rd_dat_2),
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.rd_enb_3 (mux_rd3_enb),
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.rd_adr_3 (mux_rd3_adr),
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.rd_dat_3 (rd_dat_3),
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.wr_enb_0 (mux_wr0_enb),
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.wr_adr_0 (mux_wr0_adr),
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.wr_dat_0 (mux_wr0_dat),
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.wr_enb_1 (mux_wr1_enb),
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.wr_adr_1 (mux_wr1_adr),
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.wr_dat_1 (mux_wr1_dat)
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);
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endmodule
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