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288 lines
7.3 KiB
Verilog
288 lines
7.3 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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/*
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* toysram_site
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* user_project for custom toysram cell/array
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*-------------------------------------------------------------
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*
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* user_proj_example
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*
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* This is an example of a (trivially simple) user project,
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* showing how the user project can connect to the logic
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* analyzer, the wishbone bus, and the I/O pads.
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*
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* This project generates an integer count, which is output
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* on the user area GPIO pads (digital output only). The
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* wishbone connection allows the project to be controlled
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* (start and stop) from the management SoC program.
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*
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* See the testbenches in directory "mprj_counter" for the
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* example programs that drive this user project. The three
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* testbenches are "io_ports", "la_test1", and "la_test2".
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*
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*-------------------------------------------------------------
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*/
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module toysram_site #(
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parameter BITS = 32
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/*
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.CFG_ADDR('h00000000),
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.CTL_ADDR('h00000100),
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.RA0_ADDR('h00001000),
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.ADDR_MASK
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CFG_ADDR = 'h0000E000, // offset within RAx_ADDR
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BIST_ADDR = 'h0000F000 // offset within RAx_ADDR
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*/
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)(
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`ifdef USE_POWER_PINS
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inout vccd1, // User area 1 1.8V supply
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inout vssd1, // User area 1 digital ground
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`endif
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// Wishbone Slave ports (WB MI A)
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input wb_clk_i,
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input wb_rst_i,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output wbs_ack_o,
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output [31:0] wbs_dat_o,
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// Logic Analyzer Signals
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input [127:0] la_data_in,
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output [127:0] la_data_out,
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input [127:0] la_oenb,
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// IOs
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input [`MPRJ_IO_PADS-1:0] io_in,
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output [`MPRJ_IO_PADS-1:0] io_out,
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output [`MPRJ_IO_PADS-1:0] io_oeb,
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// IRQ
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output [2:0] irq
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);
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wire clk;
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wire rst;
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wire [31:0] rdata;
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wire [31:0] wdata;
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wire [31:0] count;
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wire valid;
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wire [3:0] wstrb;
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wire [31:0] la_write;
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wire wb_cmd_val;
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wire [31:0] wb_cmd_adr;
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wire wb_cmd_we;
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wire [3:0] wb_cmd_sel;
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wire [31:0] wb_cmd_dat;
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wire wb_rd_ack;
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wire [31:0] wb_rd_dat;
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wire [31:0] cmd_adr;
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wire cmd_we;
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wire [3:0] cmd_sel;
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wire [31:0] cmd_dat;
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wire ctl_cmd_val;
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wire cfg_cmd_val;
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wire ra0_cmd_val;
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wire ctl_rd_ack;
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wire [31:0] ctl_rd_dat;
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wire ra0_clk;
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wire ra0_rst;
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wire ra0_cfg_wr;
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wire [31:0] ra0_cfg_rdat;
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wire [31:0] ra0_cfg_wdat;
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wire [31:0] ra0_bist_ctl;
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wire [31:0] ra0_bist_status;
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wire ra0_r0_enb;
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wire [4:0] ra0_r0_adr;
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wire [31:0] ra0_r0_dat;
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wire ra0_r1_enb;
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wire [4:0] ra0_r1_adr;
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wire [31:0] ra0_r1_dat;
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wire ra0_w0_enb;
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wire [4:0] ra0_w0_adr;
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wire [31:0] ra0_w0_dat;
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// WB MI A
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assign valid = wbs_cyc_i && wbs_stb_i;
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assign wstrb = wbs_sel_i & {4{wbs_we_i}};
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assign wbs_dat_o = rdata;
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assign wdata = wbs_dat_i;
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// IRQ
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assign irq = 3'b000; // Unused
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//wtf connect these to the array sigs?
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// LA
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//assign la_data_out = {{(127-BITS){1'b0}}, count};
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assign la_data_out = 0;
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// Assuming LA probes [63:32] are for controlling the count register
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//assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
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assign la_write = 0;
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// Assuming LA probes [65:64] are for controlling the count clk & reset
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//assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
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//assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
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assign clk = wb_clk_i;
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assign rst = wb_rst_i;
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// WB slave
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// convert rd/wr commands to/from WB and route to:
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// 1. config space
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// 2. array space
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wb_slave wb (
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`ifdef USE_POWER_PINS
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.vccd1(vccd1),
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.vssd1(vssd1),
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`endif
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.clk(clk),
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.rst(rst),
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.wbs_stb_i(wbs_stb_i),
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.wbs_cyc_i(wbs_cyc_i),
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.wbs_we_i(wbs_we_i),
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.wbs_sel_i(wbs_sel_i),
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.wbs_dat_i(wbs_dat_i),
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.wbs_adr_i(wbs_adr_i),
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.wbs_ack_o(wbs_ack_o),
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.wbs_dat_o(wbs_dat_o),
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.cmd_val(wb_cmd_val),
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.cmd_adr(wb_cmd_adr),
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.cmd_we(wb_cmd_we),
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.cmd_sel(wb_cmd_sel),
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.cmd_dat(wb_cmd_dat),
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.rd_ack(wb_rd_ack),
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.rd_dat(wb_rd_dat)
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);
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// register/config space
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cfg #(
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.CFG_ADDR('h00000000),
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.CTL_ADDR('h00010000),
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.RA0_ADDR('h00100000)
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) cfg (
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`ifdef USE_POWER_PINS
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.vccd1(vccd1),
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.vssd1(vssd1),
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`endif
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.clk(clk),
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.rst(rst),
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.wb_cmd_val(wb_cmd_val),
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.wb_cmd_adr(wb_cmd_adr),
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.wb_cmd_we(wb_cmd_we),
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.wb_cmd_sel(wb_cmd_sel),
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.wb_cmd_dat(wb_cmd_dat),
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.wb_rd_ack(wb_rd_ack),
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.wb_rd_dat(wb_rd_dat),
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.cmd_adr(cmd_adr),
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.cmd_we(cmd_we),
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.cmd_sel(cmd_sel),
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.cmd_dat(cmd_dat),
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.ctl_cmd_val(ctl_cmd_val),
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.cfg_cmd_val(cfg_cmd_val),
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.ra0_cmd_val(ra0_cmd_val),
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.ctl_rd_ack(ctl_rd_ack),
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.ctl_rd_dat(ctl_rd_dat)
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);
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/*
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// I/O interface
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io_intf io (
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`ifdef USE_POWER_PINS
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.vccd1(vccd1),
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.vssd1(vssd1),
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`endif
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.clk(clk),
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.rst(rst)
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);
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*/
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// array interfaces
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control #(
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) ctl (
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`ifdef USE_POWER_PINS
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.vccd1(vccd1),
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.vssd1(vssd1),
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`endif
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.clk(clk),
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.rst(rst),
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.io_in(io_in),
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.io_out(io_out),
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.io_oeb(io_oeb),
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.ctl_cmd_val(ctl_cmd_val),
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.ra0_cmd_val(ra0_cmd_val),
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.cmd_we(cmd_we),
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.cmd_adr(cmd_adr),
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.cmd_sel(cmd_sel),
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.cmd_dat(cmd_dat),
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.rd_ack(ctl_rd_ack),
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.rd_dat(ctl_rd_dat),
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.ra0_clk(ra0_clk),
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.ra0_rst(ra0_rst),
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.ra0_cfg_wr(ra0_cfg_wr),
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.ra0_cfg_rdat(), //'hFFFFFFFF'), //wtf need to add to ra for read
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.ra0_cfg_wdat(ra0_cfg_wdat),
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.ra0_bist_ctl(ra0_bist_ctl),
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.ra0_bist_status(ra0_bist_status),
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.ra0_r0_enb(ra0_r0_enb),
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.ra0_r0_adr(ra0_r0_adr),
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.ra0_r0_dat(ra0_r0_dat),
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.ra0_r1_enb(ra0_r1_enb),
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.ra0_r1_adr(ra0_r1_adr),
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.ra0_r1_dat(ra0_r1_dat),
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.ra0_w0_enb(ra0_w0_enb),
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.ra0_w0_adr(ra0_w0_adr),
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.ra0_w0_dat(ra0_w0_dat)
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);
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// arrays
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test_ra_sdr_32x32 ra_0 (
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.clk(ra0_clk),
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.reset(ra0_rst),
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.cfg_wr(ra0_cfg_wr),
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.cfg_dat(ra0_cfg_wdat),
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.bist_ctl(ra0_bist_ctl),
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.bist_status(ra0_bist_status),
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.rd_enb_0(ra0_r0_enb),
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.rd_adr_0(ra0_r0_adr),
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.rd_dat_0(ra0_r0_dat),
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.rd_enb_1(ra0_r1_enb),
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.rd_adr_1(ra0_r1_adr),
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.rd_dat_1(ra0_r1_dat),
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.wr_enb_0(ra0_w0_enb),
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.wr_adr_0(ra0_w0_adr),
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.wr_dat_0(ra0_w0_dat)
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);
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endmodule
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`default_nettype wire
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