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131 lines
6.9 KiB
Plaintext
131 lines
6.9 KiB
Plaintext
# // Questa Sim-64
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# // Version 2020.3_1 linux_x86_64 Aug 25 2020
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# //
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# // Copyright 1991-2020 Mentor Graphics Corporation
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# // All Rights Reserved.
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# //
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# // QuestaSim and its associated documentation contain trade
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# // secrets and commercial or financial information that are the property of
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# // Mentor Graphics Corporation and are privileged, confidential,
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# // and exempt from disclosure under the Freedom of Information Act,
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# // 5 U.S.C. Section 552. Furthermore, this information
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# // is prohibited from disclosure under the Trade Secrets Act,
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# // 18 U.S.C. Section 1905.
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# //
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pwd
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# /home/ptikals/IBM/osu-toy-sram/src
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do top.do
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# Cannot open macro file: top.do
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cd ../sim
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do top.do
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# QuestaSim-64 vlog 2020.3_1 Compiler 2020.08 Aug 25 2020
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# Start time: 11:20:19 on Dec 14,2021
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# vlog -reportprogress 300 -lint ../src/address_clock_sdr_2r1w_64.v ../src/ra_bist_ddr.v ../src/predecode_sdr_64.v ../src/ra_bist_sdr.v ../src/ra_2r1w_64x72_sdr.v ../src/ra_cfg_ddr.v ../src/regfile_2r1w_64x24.v ../src/toysram.vh ../src/ra_4r2w_64x72_ddr_1x.v ../src/ra_cfg_sdr.v ../src/regfile_4r2w_64x24.v ../src/ra_4r2w_64x72_ddr.v ../src/ra_delay.v ../src/ra_lcb_sdr.v ../src/ra_lcb_ddr.v ../src/test_ra_ddr.v ../src/test_ra_sdr.sv ../src/test_ra_ddr_1x.v
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# -- Compiling module address_clock_sdr_2r1w_64
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# -- Compiling module ra_bist_ddr
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# -- Compiling module predecode_sdr_64
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# -- Compiling module ra_bist_sdr
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# -- Compiling module ra_2r1w_64x72_sdr
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# -- Compiling module ra_cfg_ddr
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# -- Compiling module regfile_2r1w_64x24
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# -- Compiling module ra_4r2w_64x72_ddr_1x
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# -- Compiling module ra_cfg_sdr
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# -- Compiling module regfile_4r2w_64x24
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# -- Compiling module ra_4r2w_64x72_ddr
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# -- Compiling module ra_delay
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# -- Compiling module ra_lcb_sdr
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# ** Warning: ../src/ra_lcb_sdr.v(61): (vlog-2623) Undefined variable: i.
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# -- Compiling module ra_lcb_ddr
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# -- Compiling module test_ra_ddr
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# -- Compiling module test_ra_sdr
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# ** Warning: ../src/test_ra_sdr.sv(28): (vlog-2605) empty port name in port list.
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# -- Compiling module test_ra_ddr_1x
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#
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# Top level modules:
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# ra_bist_sdr
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# test_ra_ddr
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# test_ra_sdr
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# test_ra_ddr_1x
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# End time: 11:20:19 on Dec 14,2021, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 2
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# vsim -debugdb -voptargs="+acc" work.test_ra_sdr
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# Start time: 11:20:19 on Dec 14,2021
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# ** Note: (vsim-3812) Design is being optimized...
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# ** Note: (vsim-8611) Generating debug db.
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# ** Error: ../src/test_ra_sdr.sv(85): Module 'ra_bist_sdr_osu' is not defined.
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# Optimization failed
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# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=1, Warnings=0.
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# Error loading design
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# Error: Error loading design
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# Pausing macro execution
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# MACRO ./top.do PAUSED at line 33
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do top.do
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# QuestaSim-64 vlog 2020.3_1 Compiler 2020.08 Aug 25 2020
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# Start time: 11:29:26 on Dec 14,2021
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# vlog -reportprogress 300 -lint ../src/address_clock_sdr_2r1w_64.v ../src/ra_bist_ddr.v ../src/predecode_sdr_64.v ../src/ra_bist_sdr_osu.v ../src/ra_2r1w_64x72_sdr.v ../src/ra_cfg_ddr.v ../src/regfile_2r1w_64x24.v ../src/toysram.vh ../src/ra_4r2w_64x72_ddr_1x.v ../src/ra_cfg_sdr.v ../src/regfile_4r2w_64x24.v ../src/ra_4r2w_64x72_ddr.v ../src/ra_delay.v ../src/ra_lcb_sdr.v ../src/ra_lcb_ddr.v ../src/test_ra_ddr.v ../src/test_ra_sdr.sv ../src/test_ra_ddr_1x.v
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# -- Compiling module address_clock_sdr_2r1w_64
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# -- Compiling module ra_bist_ddr
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# -- Compiling module predecode_sdr_64
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# -- Compiling module ra_bist_sdr
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# ** Error: ../src/ra_bist_sdr_osu.v(88): (vlog-2730) Undefined variable: 'int'.
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# ** Error: (vlog-13069) ../src/ra_bist_sdr_osu.v(88): near "i": syntax error, unexpected IDENTIFIER, expecting '='.
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# ** Error: (vlog-13036) ../src/ra_bist_sdr_osu.v(88): near "++": Operator only allowed in SystemVerilog.
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# ** Error: ../src/ra_bist_sdr_osu.v(88): (vlog-13205) Syntax error found in the scope following 'i'. Is there a missing '::'?
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# -- Compiling module ra_2r1w_64x72_sdr
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# -- Compiling module ra_cfg_ddr
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# -- Compiling module regfile_2r1w_64x24
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# -- Compiling module ra_4r2w_64x72_ddr_1x
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# -- Compiling module ra_cfg_sdr
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# -- Compiling module regfile_4r2w_64x24
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# -- Compiling module ra_4r2w_64x72_ddr
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# -- Compiling module ra_delay
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# -- Compiling module ra_lcb_sdr
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# ** Warning: ../src/ra_lcb_sdr.v(61): (vlog-2623) Undefined variable: i.
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# -- Compiling module ra_lcb_ddr
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# -- Compiling module test_ra_ddr
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# -- Compiling module test_ra_sdr
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# ** Warning: ../src/test_ra_sdr.sv(28): (vlog-2605) empty port name in port list.
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# -- Compiling module test_ra_ddr_1x
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# End time: 11:29:26 on Dec 14,2021, Elapsed time: 0:00:00
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# Errors: 4, Warnings: 2
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# ** Error: /opt/Mentor/questasim/linux_x86_64/vlog failed.
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# Error in macro ./top.do line 30
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# /opt/Mentor/questasim/linux_x86_64/vlog failed.
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# while executing
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# "vlog -lint ../src/address_clock_sdr_2r1w_64.v ../src/ra_bist_ddr.v ../src/predecode_sdr_64.v ../src/ra_bist_sdr_osu.v ../src/ra_2r1w_64x72_sdr.v ../sr..."
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do top.do
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# QuestaSim-64 vlog 2020.3_1 Compiler 2020.08 Aug 25 2020
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# Start time: 11:49:53 on Dec 14,2021
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# vlog -reportprogress 300 -lint ../src/address_clock_sdr_2r1w_64.v ../src/ra_bist_ddr.v ../src/predecode_sdr_64.v ../src/ra_bist_sdr_osu.v ../src/ra_2r1w_64x72_sdr.v ../src/ra_cfg_ddr.v ../src/regfile_2r1w_64x24.v ../src/toysram.vh ../src/ra_4r2w_64x72_ddr_1x.v ../src/ra_cfg_sdr.v ../src/regfile_4r2w_64x24.v ../src/ra_4r2w_64x72_ddr.v ../src/ra_delay.v ../src/ra_lcb_sdr.v ../src/ra_lcb_ddr.v ../src/test_ra_ddr.v ../src/test_ra_sdr.sv ../src/test_ra_ddr_1x.v
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# -- Compiling module address_clock_sdr_2r1w_64
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# -- Compiling module ra_bist_ddr
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# -- Compiling module predecode_sdr_64
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# -- Compiling module ra_bist_sdr
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# ** Error: ../src/ra_bist_sdr_osu.v(88): (vlog-2730) Undefined variable: 'int'.
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# ** Error: (vlog-13069) ../src/ra_bist_sdr_osu.v(88): near "i": syntax error, unexpected IDENTIFIER, expecting '='.
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# ** Error: ../src/ra_bist_sdr_osu.v(88): (vlog-13205) Syntax error found in the scope following 'i'. Is there a missing '::'?
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# -- Compiling module ra_2r1w_64x72_sdr
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# -- Compiling module ra_cfg_ddr
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# -- Compiling module regfile_2r1w_64x24
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# -- Compiling module ra_4r2w_64x72_ddr_1x
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# -- Compiling module ra_cfg_sdr
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# -- Compiling module regfile_4r2w_64x24
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# -- Compiling module ra_4r2w_64x72_ddr
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# -- Compiling module ra_delay
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# -- Compiling module ra_lcb_sdr
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# ** Warning: ../src/ra_lcb_sdr.v(61): (vlog-2623) Undefined variable: i.
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# -- Compiling module ra_lcb_ddr
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# -- Compiling module test_ra_ddr
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# -- Compiling module test_ra_sdr
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# ** Warning: ../src/test_ra_sdr.sv(28): (vlog-2605) empty port name in port list.
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# -- Compiling module test_ra_ddr_1x
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# End time: 11:49:53 on Dec 14,2021, Elapsed time: 0:00:00
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# Errors: 3, Warnings: 2
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# ** Error: /opt/Mentor/questasim/linux_x86_64/vlog failed.
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# Error in macro ./top.do line 30
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# /opt/Mentor/questasim/linux_x86_64/vlog failed.
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# while executing
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# "vlog -lint ../src/address_clock_sdr_2r1w_64.v ../src/ra_bist_ddr.v ../src/predecode_sdr_64.v ../src/ra_bist_sdr_osu.v ../src/ra_2r1w_64x72_sdr.v ../sr..."
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# End time: 12:39:15 on Dec 14,2021, Elapsed time: 1:18:56
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# Errors: 3, Warnings: 0
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