microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Benjamin Herrenschmidt bf1b98b958 litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		4 years ago
constraints	…
fpga	litedram: Add support for booting without BRAM	4 years ago
hello_world	…
include	litedram: Add support for booting without BRAM	4 years ago
lib	litedram: Update to new LiteX/LiteDRAM version	5 years ago
litedram	litedram: Add support for booting without BRAM	4 years ago
media	…
micropython	…
openocd	flash-arty: Add support for specifying the file type	4 years ago
rust_lib_demo	…
scripts	bin2hex: Make sure to generate little endian files	5 years ago
sim-unisim	…
tests	soc: Rework interconnect	5 years ago
verilator	Pass clock frequency to UART sim wrapper	5 years ago
.gitignore	…
.travis.yml	…
LICENSE	…
Makefile	litedram: Add simulation support	4 years ago
README.md	Add Makefile command line variables to enable docker and podman	5 years ago
cache_ram.vhdl	dcache: Rework RAM wrapper to synthetize better on Xilinx	5 years ago
common.vhdl	irq: Simplify xics->core irq input	5 years ago
control.vhdl	…
core.vhdl	irq: Simplify xics->core irq input	5 years ago
core_debug.vhdl	…
core_dram_tb.vhdl	litedram: Add support for booting without BRAM	4 years ago
core_tb.vhdl	soc: Rework interconnect	5 years ago
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countzero_tb.vhdl	Exit cleanly from testbench on success	5 years ago
cr_file.vhdl	…
cr_hazard.vhdl	…
crhelpers.vhdl	…
dcache.vhdl	dcache: Rework RAM wrapper to synthetize better on Xilinx	5 years ago
dcache_tb.vhdl	Exit cleanly from testbench on success	5 years ago
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divider.vhdl	…
divider_tb.vhdl	Exit cleanly from testbench on success	5 years ago
dmi_dtm_dummy.vhdl	…
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dmi_dtm_xilinx.vhdl	…
execute1.vhdl	irq: Simplify xics->core irq input	5 years ago
fetch1.vhdl	…
fetch2.vhdl	…
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
gpr_hazard.vhdl	…
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icache.vhdl	dcache: Rework RAM wrapper to synthetize better on Xilinx	5 years ago
icache_tb.vhdl	Exit cleanly from testbench on success	5 years ago
icache_test.bin	…
insn_helpers.vhdl	…
loadstore1.vhdl	…
logical.vhdl	…
microwatt.core	litedram: Add support for booting without BRAM	4 years ago
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multiply.vhdl	…
multiply_tb.vhdl	Exit cleanly from testbench on success	5 years ago
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plru_tb.vhdl	Exit cleanly from testbench on success	5 years ago
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rotator_tb.vhdl	Exit cleanly from testbench on success	5 years ago
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sim_vhpi_c.c	…
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soc.vhdl	litedram: Add support for booting without BRAM	4 years ago
syscon.vhdl	litedram: Add support for booting without BRAM	4 years ago
utils.vhdl	litedram: Add support for booting without BRAM	4 years ago
wishbone_arbiter.vhdl	…
wishbone_bram_tb.bin	…
wishbone_bram_tb.vhdl	Exit cleanly from testbench on success	5 years ago
wishbone_bram_wrapper.vhdl	…
wishbone_debug_master.vhdl	…
wishbone_types.vhdl	soc: Rework interconnect	5 years ago
writeback.vhdl	…
xics.vhdl	irq: Simplify xics->core irq input	5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)