ram: Rework main RAM interface
This replaces the simple_ram_behavioural and mw_soc_memory modules with a common wishbone_bram_wrapper.vhdl that interfaces the pipelined WB with a lower-level RAM module, along with an FPGA and a sim variants of the latter. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>pull/118/head
Benjamin Herrenschmidt
5 years ago
parent
9a63c098a5
commit
8e0389b973
@ -0,0 +1,83 @@
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-- Single port Block RAM with one cycle output buffer
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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entity main_bram is
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generic(
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WIDTH : natural := 64;
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HEIGHT_BITS : natural := 1024;
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MEMORY_SIZE : natural := 65536;
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RAM_INIT_FILE : string
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);
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port(
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clk : in std_logic;
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addr : in std_logic_vector(HEIGHT_BITS - 1 downto 0) ;
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di : in std_logic_vector(WIDTH-1 downto 0);
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do : out std_logic_vector(WIDTH-1 downto 0);
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sel : in std_logic_vector((WIDTH/8)-1 downto 0);
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re : in std_ulogic;
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we : in std_ulogic
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);
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end entity main_bram;
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architecture behaviour of main_bram is
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constant WIDTH_BYTES : natural := WIDTH / 8;
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-- RAM type definition
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type ram_t is array(0 to (MEMORY_SIZE / WIDTH_BYTES) - 1) of std_logic_vector(WIDTH-1 downto 0);
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-- RAM loading
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impure function init_ram(name : STRING) return ram_t is
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file ram_file : text open read_mode is name;
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variable ram_line : line;
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variable temp_word : std_logic_vector(WIDTH-1 downto 0);
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variable temp_ram : ram_t := (others => (others => '0'));
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begin
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for i in 0 to (MEMORY_SIZE / WIDTH_BYTES) - 1 loop
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exit when endfile(ram_file);
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readline(ram_file, ram_line);
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hread(ram_line, temp_word);
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temp_ram(i) := temp_word;
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end loop;
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return temp_ram;
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end function;
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-- RAM instance
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signal memory : ram_t := init_ram(RAM_INIT_FILE);
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attribute ram_style : string;
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attribute ram_style of memory : signal is "block";
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attribute ram_decomp : string;
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attribute ram_decomp of memory : signal is "power";
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-- Others
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signal obuf : std_logic_vector(WIDTH-1 downto 0);
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begin
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-- Actual RAM template
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memory_0: process(clk)
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begin
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if rising_edge(clk) then
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if we = '1' then
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for i in 0 to 7 loop
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if sel(i) = '1' then
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memory(conv_integer(addr))((i + 1) * 8 - 1 downto i * 8) <=
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di((i + 1) * 8 - 1 downto i * 8);
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end if;
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end loop;
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end if;
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if re = '1' then
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obuf <= memory(conv_integer(addr));
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end if;
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do <= obuf;
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end if;
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end process;
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end architecture behaviour;
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@ -1,112 +0,0 @@
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-- Based on:
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.wishbone_types.all;
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use work.pp_utilities.all;
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--! @brief Simple memory module for use in Wishbone-based systems.
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entity mw_soc_memory is
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generic(
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MEMORY_SIZE : natural := 4096; --! Memory size in bytes.
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RAM_INIT_FILE : string
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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-- Wishbone interface:
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wishbone_in : in wishbone_master_out;
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wishbone_out : out wishbone_slave_out
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);
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end entity mw_soc_memory;
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architecture behaviour of mw_soc_memory is
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-- RAM type definition
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type ram_t is array(0 to (MEMORY_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
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-- RAM loading
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impure function init_ram(name : STRING) return ram_t is
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file ram_file : text open read_mode is name;
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variable ram_line : line;
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variable temp_word : std_logic_vector(63 downto 0);
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variable temp_ram : ram_t := (others => (others => '0'));
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begin
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for i in 0 to (MEMORY_SIZE/8)-1 loop
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exit when endfile(ram_file);
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readline(ram_file, ram_line);
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hread(ram_line, temp_word);
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temp_ram(i) := temp_word;
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end loop;
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return temp_ram;
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end function;
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-- RAM instance
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signal memory : ram_t := init_ram(RAM_INIT_FILE);
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attribute ram_style : string;
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attribute ram_style of memory : signal is "block";
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attribute ram_decomp : string;
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attribute ram_decomp of memory : signal is "power";
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-- RAM interface
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constant ram_addr_bits : integer := log2(MEMORY_SIZE) - 3;
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signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);
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signal ram_di : std_logic_vector(63 downto 0);
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signal ram_do : std_logic_vector(63 downto 0);
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signal ram_sel : std_logic_vector(7 downto 0);
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signal ram_we : std_ulogic;
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-- Others
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signal ram_obuf : std_logic_vector(63 downto 0);
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signal ack, ack_obuf : std_ulogic;
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begin
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-- Actual RAM template
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memory_0: process(clk)
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begin
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if rising_edge(clk) then
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if ram_we = '1' then
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for i in 0 to 7 loop
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if ram_sel(i) = '1' then
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memory(conv_integer(ram_addr))((i + 1) * 8 - 1 downto i * 8) <=
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ram_di((i + 1) * 8 - 1 downto i * 8);
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end if;
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end loop;
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end if;
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ram_do <= memory(conv_integer(ram_addr));
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ram_obuf <= ram_do;
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end if;
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end process;
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-- Wishbone interface
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ram_addr <= wishbone_in.adr(ram_addr_bits + 2 downto 3);
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ram_di <= wishbone_in.dat;
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ram_sel <= wishbone_in.sel;
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ram_we <= wishbone_in.we and wishbone_in.stb and wishbone_in.cyc;
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wishbone_out.stall <= '0';
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wishbone_out.ack <= ack_obuf;
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wishbone_out.dat <= ram_obuf;
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wb_0: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' or wishbone_in.cyc = '0' then
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ack_obuf <= '0';
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ack <= '0';
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else
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ack <= wishbone_in.stb;
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ack_obuf <= ack;
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end if;
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end if;
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end process;
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end architecture behaviour;
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@ -0,0 +1,67 @@
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-- Single port Block RAM with one cycle output buffer
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--
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-- Simulated via C helpers
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.utils.all;
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use work.sim_bram_helpers.all;
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entity main_bram is
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generic(
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WIDTH : natural := 64;
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HEIGHT_BITS : natural := 1024;
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MEMORY_SIZE : natural := 65536;
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RAM_INIT_FILE : string
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);
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port(
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clk : in std_logic;
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addr : in std_logic_vector(HEIGHT_BITS - 1 downto 0) ;
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di : in std_logic_vector(WIDTH-1 downto 0);
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do : out std_logic_vector(WIDTH-1 downto 0);
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sel : in std_logic_vector((WIDTH/8)-1 downto 0);
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re : in std_ulogic;
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we : in std_ulogic
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);
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end entity main_bram;
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architecture sim of main_bram is
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constant WIDTH_BYTES : natural := WIDTH / 8;
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constant pad_zeros : std_ulogic_vector(log2(WIDTH_BYTES)-1 downto 0)
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:= (others => '0');
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signal identifier : integer := behavioural_initialize(filename => RAM_INIT_FILE,
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size => MEMORY_SIZE);
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-- Others
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signal obuf : std_logic_vector(WIDTH-1 downto 0);
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begin
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-- Actual RAM template
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memory_0: process(clk)
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variable ret_dat_v : std_ulogic_vector(63 downto 0);
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variable addr64 : std_ulogic_vector(63 downto 0);
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begin
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if rising_edge(clk) then
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addr64 := (others => '0');
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addr64(HEIGHT_BITS + 2 downto 3) := addr;
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if we = '1' then
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report "RAM writing " & to_hstring(di) & " to " &
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to_hstring(addr & pad_zeros) & " sel:" & to_hstring(sel);
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behavioural_write(di, addr64, to_integer(unsigned(sel)), identifier);
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end if;
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if re = '1' then
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behavioural_read(ret_dat_v, addr64, to_integer(unsigned(sel)), identifier);
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report "RAM reading from " & to_hstring(addr & pad_zeros) &
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" returns " & to_hstring(ret_dat_v);
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obuf <= ret_dat_v(obuf'left downto 0);
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end if;
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do <= obuf;
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end if;
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end process;
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end architecture sim;
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@ -1,133 +0,0 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.wishbone_types.all;
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use work.simple_ram_behavioural_helpers.all;
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entity mw_soc_memory is
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generic (
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RAM_INIT_FILE : string;
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MEMORY_SIZE : integer;
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PIPELINE_DEPTH : integer := 1
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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wishbone_in : in wishbone_master_out;
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wishbone_out : out wishbone_slave_out
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);
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end mw_soc_memory;
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architecture behave of mw_soc_memory is
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type wishbone_state_t is (IDLE, ACK);
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signal state : wishbone_state_t := IDLE;
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signal ret_ack : std_ulogic := '0';
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signal identifier : integer := behavioural_initialize(filename => RAM_INIT_FILE, size => MEMORY_SIZE);
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signal reload : integer := 0;
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signal ret_dat : wishbone_data_type;
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subtype pipe_idx_t is integer range 0 to PIPELINE_DEPTH-1;
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type pipe_ack_t is array(pipe_idx_t) of std_ulogic;
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type pipe_dat_t is array(pipe_idx_t) of wishbone_data_type;
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begin
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pipe_big: if PIPELINE_DEPTH > 1 generate
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signal pipe_ack : pipe_ack_t;
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signal pipe_dat : pipe_dat_t;
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begin
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wishbone_out.stall <= '0';
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wishbone_out.ack <= pipe_ack(0);
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wishbone_out.dat <= pipe_dat(0);
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pipe_big_sync: process(clk)
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begin
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if rising_edge(clk) then
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pipe_stages: for i in 0 to PIPELINE_DEPTH-2 loop
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pipe_ack(i) <= pipe_ack(i+1);
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pipe_dat(i) <= pipe_dat(i+1);
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end loop;
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pipe_ack(PIPELINE_DEPTH-1) <= ret_ack;
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pipe_dat(PIPELINE_DEPTH-1) <= ret_dat;
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end if;
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end process;
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end generate;
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pipe_one: if PIPELINE_DEPTH = 1 generate
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signal pipe_ack : std_ulogic;
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signal pipe_dat : wishbone_data_type;
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begin
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wishbone_out.stall <= '0';
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wishbone_out.ack <= pipe_ack;
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wishbone_out.dat <= pipe_dat;
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pipe_one_sync: process(clk)
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begin
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if rising_edge(clk) then
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pipe_ack <= ret_ack;
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pipe_dat <= ret_dat;
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end if;
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end process;
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end generate;
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pipe_none: if PIPELINE_DEPTH = 0 generate
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begin
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wishbone_out.ack <= ret_ack;
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wishbone_out.dat <= ret_dat;
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wishbone_out.stall <= wishbone_in.cyc and not ret_ack;
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end generate;
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wishbone_process: process(clk)
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variable ret_dat_v : wishbone_data_type;
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variable adr : std_ulogic_vector(63 downto 0);
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begin
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if rising_edge(clk) then
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if rst = '1' then
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state <= IDLE;
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ret_ack <= '0';
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else
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ret_dat <= x"FFFFFFFFFFFFFFFF";
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ret_ack <= '0';
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-- Active
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if wishbone_in.cyc = '1' then
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case state is
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when IDLE =>
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if wishbone_in.stb = '1' then
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adr := (wishbone_in.adr'left downto 0 => wishbone_in.adr,
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others => '0');
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-- write
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if wishbone_in.we = '1' then
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assert not(is_x(wishbone_in.dat)) and not(is_x(wishbone_in.adr)) severity failure;
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report "RAM writing " & to_hstring(wishbone_in.dat) & " to " & to_hstring(wishbone_in.adr);
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behavioural_write(wishbone_in.dat, adr, to_integer(unsigned(wishbone_in.sel)), identifier);
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reload <= reload + 1;
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ret_ack <= '1';
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if PIPELINE_DEPTH = 0 then
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state <= ACK;
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end if;
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else
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behavioural_read(ret_dat_v, adr, to_integer(unsigned(wishbone_in.sel)), identifier, reload);
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report "RAM reading from " & to_hstring(wishbone_in.adr) & " returns " & to_hstring(ret_dat_v);
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ret_dat <= ret_dat_v;
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ret_ack <= '1';
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if PIPELINE_DEPTH = 0 then
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state <= ACK;
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end if;
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end if;
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end if;
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when ACK =>
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state <= IDLE;
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end case;
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else
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state <= IDLE;
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end if;
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end if;
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end if;
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end process;
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end behave;
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@ -1,246 +0,0 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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entity simple_ram_behavioural_tb is
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end simple_ram_behavioural_tb;
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architecture behave of simple_ram_behavioural_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic := '1';
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constant clk_period : time := 10 ns;
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signal w_in : wishbone_slave_out;
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signal w_out : wishbone_master_out;
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impure function to_adr(a: integer) return std_ulogic_vector is
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begin
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return std_ulogic_vector(to_unsigned(a, w_out.adr'length));
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end;
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begin
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simple_ram_0: entity work.mw_soc_memory
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generic map (
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RAM_INIT_FILE => "simple_ram_behavioural_tb.bin",
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MEMORY_SIZE => 16
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)
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port map (
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clk => clk,
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rst => rst,
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wishbone_out => w_in,
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wishbone_in => w_out
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);
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clock: process
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begin
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clk <= '1';
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wait for clk_period / 2;
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clk <= '0';
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wait for clk_period / 2;
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end process clock;
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stim: process
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begin
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w_out.adr <= (others => '0');
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w_out.dat <= (others => '0');
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w_out.cyc <= '0';
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w_out.stb <= '0';
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w_out.sel <= (others => '0');
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w_out.we <= '0';
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wait for clk_period;
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rst <= '0';
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wait for clk_period;
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w_out.cyc <= '1';
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-- test various read lengths and alignments
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= to_adr(0);
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(7 downto 0) = x"00" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= to_adr(1);
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assert w_in.ack = '0';
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wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(7 downto 0) = x"01" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00000001";
|
||||
w_out.adr <= to_adr(7);
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(7 downto 0) = x"07" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00000011";
|
||||
w_out.adr <= to_adr(0);
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(15 downto 0) = x"0100" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00000011";
|
||||
w_out.adr <= to_adr(1);
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(15 downto 0) = x"0201" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00000011";
|
||||
w_out.adr <= to_adr(7);
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(15 downto 0) = x"0807" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00001111";
|
||||
w_out.adr <= to_adr(0);
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(31 downto 0) = x"03020100" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00001111";
|
||||
w_out.adr <= to_adr(1);
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(31 downto 0) = x"04030201" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00001111";
|
||||
w_out.adr <= to_adr(7);
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(31 downto 0) = x"0A090807" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= to_adr(0);
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"0706050403020100" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= to_adr(1);
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"0807060504030201" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= to_adr(7);
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"0E0D0C0B0A090807" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
-- test various write lengths and alignments
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00000001";
|
||||
w_out.adr <= to_adr(0);
|
||||
w_out.we <= '1';
|
||||
w_out.dat(7 downto 0) <= x"0F";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00000001";
|
||||
w_out.adr <= to_adr(0);
|
||||
w_out.we <= '0';
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(7 downto 0) = x"0F" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= to_adr(7);
|
||||
w_out.we <= '1';
|
||||
w_out.dat <= x"BADC0FFEBADC0FFE";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= to_adr(7);
|
||||
w_out.we <= '0';
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat = x"BADC0FFEBADC0FFE" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
assert false report "end of test" severity failure;
|
||||
wait;
|
||||
end process;
|
||||
end behave;
|
||||
@ -0,0 +1,175 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
|
||||
entity wishbone_bram_tb is
|
||||
end wishbone_bram_tb;
|
||||
|
||||
architecture behave of wishbone_bram_tb is
|
||||
signal clk : std_ulogic;
|
||||
signal rst : std_ulogic := '1';
|
||||
|
||||
constant clk_period : time := 10 ns;
|
||||
|
||||
signal w_in : wishbone_slave_out;
|
||||
signal w_out : wishbone_master_out;
|
||||
|
||||
impure function to_adr(a: integer) return std_ulogic_vector is
|
||||
begin
|
||||
return std_ulogic_vector(to_unsigned(a, w_out.adr'length));
|
||||
end;
|
||||
begin
|
||||
simple_ram_0: entity work.wishbone_bram_wrapper
|
||||
generic map (
|
||||
RAM_INIT_FILE => "wishbone_bram_tb.bin",
|
||||
MEMORY_SIZE => 16
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
wishbone_out => w_in,
|
||||
wishbone_in => w_out
|
||||
);
|
||||
|
||||
clock: process
|
||||
begin
|
||||
clk <= '1';
|
||||
wait for clk_period / 2;
|
||||
clk <= '0';
|
||||
wait for clk_period / 2;
|
||||
end process clock;
|
||||
|
||||
stim: process
|
||||
begin
|
||||
w_out.adr <= (others => '0');
|
||||
w_out.dat <= (others => '0');
|
||||
w_out.cyc <= '0';
|
||||
w_out.stb <= '0';
|
||||
w_out.sel <= (others => '0');
|
||||
w_out.we <= '0';
|
||||
|
||||
wait until rising_edge(clk);
|
||||
rst <= '0';
|
||||
wait until rising_edge(clk);
|
||||
|
||||
w_out.cyc <= '1';
|
||||
|
||||
-- Test read 0
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= to_adr(0);
|
||||
assert w_in.ack = '0';
|
||||
wait until rising_edge(clk);
|
||||
w_out.stb <= '0';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"0706050403020100" report to_hstring(w_in.dat);
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '0';
|
||||
|
||||
-- Test read 8
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= to_adr(8);
|
||||
assert w_in.ack = '0';
|
||||
wait until rising_edge(clk);
|
||||
w_out.stb <= '0';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"0F0E0D0C0B0A0908" report to_hstring(w_in.dat);
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '0';
|
||||
|
||||
-- Test write byte at 0
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00000001";
|
||||
w_out.adr <= to_adr(0);
|
||||
w_out.we <= '1';
|
||||
w_out.dat(7 downto 0) <= x"0F";
|
||||
assert w_in.ack = '0';
|
||||
wait until rising_edge(clk);
|
||||
w_out.stb <= '0';
|
||||
wait until rising_edge(clk) and w_in.ack = '1';
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '0';
|
||||
|
||||
-- Test read back
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= to_adr(0);
|
||||
w_out.we <= '0';
|
||||
assert w_in.ack = '0';
|
||||
wait until rising_edge(clk);
|
||||
w_out.stb <= '0';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"070605040302010F" report to_hstring(w_in.dat);
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '0';
|
||||
|
||||
-- Test write dword at 4
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11110000";
|
||||
w_out.adr <= to_adr(0);
|
||||
w_out.we <= '1';
|
||||
w_out.dat(63 downto 32) <= x"BAADFEED";
|
||||
assert w_in.ack = '0';
|
||||
wait until rising_edge(clk);
|
||||
w_out.stb <= '0';
|
||||
wait until rising_edge(clk) and w_in.ack = '1';
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '0';
|
||||
|
||||
-- Test read back
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= to_adr(0);
|
||||
w_out.we <= '0';
|
||||
assert w_in.ack = '0';
|
||||
wait until rising_edge(clk);
|
||||
w_out.stb <= '0';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"BAADFEED0302010F" report to_hstring(w_in.dat);
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '0';
|
||||
|
||||
-- Test write qword at 8
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= to_adr(8);
|
||||
w_out.we <= '1';
|
||||
w_out.dat(63 downto 0) <= x"0001020304050607";
|
||||
assert w_in.ack = '0';
|
||||
wait until rising_edge(clk);
|
||||
w_out.stb <= '0';
|
||||
wait until rising_edge(clk) and w_in.ack = '1';
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '0';
|
||||
|
||||
-- Test read back
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= to_adr(8);
|
||||
w_out.we <= '0';
|
||||
assert w_in.ack = '0';
|
||||
wait until rising_edge(clk);
|
||||
w_out.stb <= '0';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"0001020304050607" report to_hstring(w_in.dat);
|
||||
wait until rising_edge(clk);
|
||||
assert w_in.ack = '0';
|
||||
|
||||
assert false report "end of test" severity failure;
|
||||
wait;
|
||||
end process;
|
||||
end behave;
|
||||
@ -0,0 +1,76 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use std.textio.all;
|
||||
|
||||
library work;
|
||||
use work.utils.all;
|
||||
use work.wishbone_types.all;
|
||||
|
||||
--! @brief Simple memory module for use in Wishbone-based systems.
|
||||
entity wishbone_bram_wrapper is
|
||||
generic(
|
||||
MEMORY_SIZE : natural := 4096; --! Memory size in bytes.
|
||||
RAM_INIT_FILE : string
|
||||
);
|
||||
port(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
-- Wishbone interface:
|
||||
wishbone_in : in wishbone_master_out;
|
||||
wishbone_out : out wishbone_slave_out
|
||||
);
|
||||
end entity wishbone_bram_wrapper;
|
||||
|
||||
architecture behaviour of wishbone_bram_wrapper is
|
||||
constant ram_addr_bits : integer := log2(MEMORY_SIZE) - 3;
|
||||
|
||||
-- RAM interface
|
||||
signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);
|
||||
signal ram_we : std_ulogic;
|
||||
signal ram_re : std_ulogic;
|
||||
|
||||
-- Others
|
||||
signal ack, ack_buf : std_ulogic;
|
||||
begin
|
||||
|
||||
-- Actual RAM template
|
||||
ram_0: entity work.main_bram
|
||||
generic map(
|
||||
WIDTH => 64,
|
||||
HEIGHT_BITS => ram_addr_bits,
|
||||
MEMORY_SIZE => MEMORY_SIZE,
|
||||
RAM_INIT_FILE => RAM_INIT_FILE
|
||||
)
|
||||
port map(
|
||||
clk => clk,
|
||||
addr => ram_addr,
|
||||
di => wishbone_in.dat,
|
||||
do => wishbone_out.dat,
|
||||
sel => wishbone_in.sel,
|
||||
re => ram_re,
|
||||
we => ram_we
|
||||
);
|
||||
|
||||
-- Wishbone interface
|
||||
ram_addr <= wishbone_in.adr(ram_addr_bits + 2 downto 3);
|
||||
ram_we <= wishbone_in.stb and wishbone_in.cyc and wishbone_in.we;
|
||||
ram_re <= wishbone_in.stb and wishbone_in.cyc and not wishbone_in.we;
|
||||
wishbone_out.stall <= '0';
|
||||
wishbone_out.ack <= ack_buf;
|
||||
|
||||
wb_0: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' or wishbone_in.cyc = '0' then
|
||||
ack_buf <= '0';
|
||||
ack <= '0';
|
||||
else
|
||||
ack <= wishbone_in.stb;
|
||||
ack_buf <= ack;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture behaviour;
|
||||
Loading…
Reference in New Issue