A tiny Open POWER ISA softcore written in VHDL 2008
 
 
 
 
 
 
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Paul Mackerras 30f6574135 predecode: Work around apparent yosys/nextpnr bug
This rearranges the synchronous process here to avoid setting fields
of pred(i) to zero or INSN_illegal when valid_in is '0'.
Experimentally, on ECP5 this acts like an asynchronous reset rather
than a synchronous reset.

Instead, handle possible indeterminate input for simulation by making
the maj_predecode and row_predecode fields of predec_t be unsigned
rather than insn_code (an enumerated type), and setting them to X when
the input word is indeterminate.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
.github/workflows ci: Add new Orange Crab build
constraints orangecrab: add Orange Crab r0.2 target
fpga Extend LiteDRAM VHDL wrapper to allow more than one clock line
hello_world Zero BSS in hello world test
include arty_a7: Add litesdcard interface
lib console: Add support for the 16550 UART
litedram litedram: Regenerate
liteeth Regenerate litedram and liteeth
litesdcard litesdcard: Fix and regenerate Verilog
media Add title image
micropython tests: Add updated micropython build with 16550 support
openocd flash-arty: Add cable argument
rust_lib_demo console: Cleanup console API
scripts FPU: Simplify IDLE state code
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
tests test: Add test for metavalues
uart16550 Add uart16550 files from fusesoc
verilator verilator: Specify top level module
.gitignore Add litesdcard/build to gitignore
LICENSE Initial import of microwatt
Makefile Pre-decode instructions when writing them to icache
README.md README: Add Linux on Microwatt instructions
cache_ram.vhdl Pre-decode instructions when writing them to icache
common.vhdl Pre-decode instructions when writing them to icache
control.vhdl Track hazards explicitly for XER overflow bits
core.vhdl Pre-decode instructions when writing them to icache
core_debug.vhdl Metavalue cleanup for common.vhdl
core_dram_tb.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line
core_flash_tb.vhdl Reformat testbenches
core_tb.vhdl Reformat testbenches
countbits.vhdl Allow integer instructions and load/store instructions to execute together
countbits_tb.vhdl Add a second execute stage to the pipeline
cr_file.vhdl execute1: Restructure to separate out execution of side effects
crhelpers.vhdl crhelpers: Constraint "crnum" integer
dcache.vhdl Remove leftover logic for 16-byte loads and stores
dcache_tb.vhdl Reformat testbenches
decode1.vhdl Pre-decode instructions when writing them to icache
decode2.vhdl Eliminate use of primary opcode outside of decode1
decode_types.vhdl Eliminate use of primary opcode outside of decode1
divider.vhdl Add a second execute stage to the pipeline
divider_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl
dmi_dtm_ecp5.vhdl dmi_dtm_ecp5: Use ECP5 JTAGG for DMI
dmi_dtm_tb.vhdl Reformat testbenches
dmi_dtm_xilinx.vhdl Fix some whitespace issues
dram_tb.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line
execute1.vhdl Eliminate use of primary opcode outside of decode1
fetch1.vhdl Metavalue cleanup for fetch1.vhdl
foreign_random.vhdl Make core testbenches recognized by VUnit
fpu.vhdl FPU: Set sign of 0 result of subtraction in pack_dp
glibc_random.vhdl Reformat glibc_random
glibc_random_helpers.vhdl Reformat glibc_random
gpio.vhdl Remove some FPGA style signal inits
helpers.vhdl Metavalue cleanup for helpers.vhdl
icache.vhdl Pre-decode instructions when writing them to icache
icache_tb.vhdl fix: fix icache_tb not finishing correctly
icache_test.bin icache_tb: Improve test and include test file
insn_helpers.vhdl core: Implement quadword loads and stores
loadstore1.vhdl loadstore1: Simplify address generation in OP_FETCH_FAILED case
logical.vhdl Finish off taking SPRs out of register file
microwatt.core Pre-decode instructions when writing them to icache
mmu.vhdl Metavalue cleanup for mmu.vhdl
multiply.vhdl core: Add a short multiplier
multiply_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging
nonrandom.vhdl Add random number generator and implement the darn instruction
plru.vhdl Reformat plru
plru_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging
pmu.vhdl Metavalue cleanup for pmu.vhdl
ppc_fx_insns.vhdl Fix some whitespace issues
predecode.vhdl predecode: Work around apparent yosys/nextpnr bug
random.vhdl Make core testbenches recognized by VUnit
register_file.vhdl Metavalue cleanup for register_file.vhdl
rotator.vhdl Metavalue cleanup for rotator.vhdl
rotator_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging
run.py VUnit: style
sim_16550_uart.vhdl uart: Add a simulation model for the 16550 compatible UART
sim_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning
sim_bram_helpers.vhdl ram: Rework main RAM interface
sim_bram_helpers_c.c Consolidate VHPI code
sim_console.vhdl Reformat sim_console
sim_console_c.c sim_console: Fix polling to check for POLLIN
sim_jtag.vhdl Add jtag support in simulation via a socket
sim_jtag_socket.vhdl Add jtag support in simulation via a socket
sim_jtag_socket_c.c Consolidate VHPI code
sim_no_flash.vhdl spi: Add simulation support
sim_pp_uart.vhdl uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
sim_vhpi_c.c Consolidate VHPI code
sim_vhpi_c.h Consolidate VHPI code
soc.vhdl soc: Fix -Whide warning
spi_flash_ctrl.vhdl Remove some FPGA style signal inits
spi_rxtx.vhdl Remove some FPGA style signal inits
sync_fifo.vhdl litedram: Add an L2 cache with store queue
syscon.vhdl Make wishbone addresses be in units of doublewords or words
utils.vhdl litedram: Add support for booting without BRAM
wishbone_arbiter.vhdl wb_arbiter: Early master selection
wishbone_bram_tb.bin ram: Rework main RAM interface
wishbone_bram_tb.vhdl Make wishbone addresses be in units of doublewords or words
wishbone_bram_wrapper.vhdl wishbone_bram_wrapper ram_addr_bits is 1 bit off
wishbone_debug_master.vhdl Make wishbone addresses be in units of doublewords or words
wishbone_types.vhdl Introduce addr_to_wb() and wb_to_addr() helpers
writeback.vhdl writeback: Eliminate unintentional inferred latch
xics.vhdl xics: Fix -Whide warnings
xilinx-mult.vhdl core: Add a short multiplier

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
fusesoc fetch uart16550
fusesoc library add microwatt /path/to/microwatt
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Linux on Microwatt

Mainline Linux supports Microwatt as of v5.14. The Arty A7 is the best tested platform, but it's also been tested on the OrangeCrab and ButterStick.

  1. Use buildroot to create a userspace

    A small change is required to glibc in order to support the VMX/AltiVec-less Microwatt, as float128 support is mandiatory and for this in GCC requires VSX/AltiVec. This change is included in Joel's buildroot fork, along with a defconfig:

    git clone -b microwatt https://github.com/shenki/buildroot
    cd buildroot
    make ppc64le_microwatt_defconfig
    make
    

    The output is output/images/rootfs.cpio.

  2. Build the Linux kernel

    git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
    cd linux
    make ARCH=powerpc microwatt_defconfig
    make ARCH=powerpc CROSS_COMPILE=powerpc64le-linux-gnu- \
      CONFIG_INITRAMFS_SOURCE=/buildroot/output/images/rootfs.cpio -j`nproc`
    

    The output is arch/powerpc/boot/dtbImage.microwatt.elf.

  3. Build gateware using FuseSoC

    First configure FuseSoC as above.

    fusesoc run --build --target=arty_a7-100 microwatt --no_bram --memory_size=0
    

    The output is build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit.

  4. Program the flash

    This operation will overwrite the contents of your flash.

    For the Arty A7 A100, set FLASH_ADDRESS to 0x400000 and pass -f a100.

    For the Arty A7 A35, set FLASH_ADDRESS to 0x300000 and pass -f a35.

    microwatt/openocd/flash-arty -f a100 build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit
    microwatt/openocd/flash-arty -f a100 dtbImage.microwatt.elf -t bin -a $FLASH_ADDRESS
    
  5. Connect to the second USB TTY device exposed by the FPGA

    minicom -D /dev/ttyUSB1
    

    The gateware has firmware that will look at FLASH_ADDRESS and attempt to parse an ELF there, loading it to the address specified in the ELF header and jumping to it.

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

  • There are a few instructions still to be implemented:
    • Vector/VMX/VSX