Regenerate litedram and liteeth

Note: There are a few patches to upstream to fix an upstream breakage
of litedram standalone generator, and fix some issues with liteeth
in the way it's used on Wukong. All these have pending pull requests.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
pull/333/head
Benjamin Herrenschmidt 3 years ago
parent da0189af1e
commit d564672a82

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File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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@ -1,5 +1,5 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:12
// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:33
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
@ -4587,10 +4587,10 @@ end
reg dummy_d_103;
// synthesis translate_on
always @(*) begin
main_litedramcore_inti_p3_rddata <= 32'd0;
main_litedramcore_slave_p3_rddata <= 32'd0;
if (main_litedramcore_sel) begin
main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
end else begin
main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
end
// synthesis translate_off
dummy_d_103 = dummy_s;
@ -4616,10 +4616,10 @@ end
reg dummy_d_105;
// synthesis translate_on
always @(*) begin
main_litedramcore_inti_p3_rddata_valid <= 1'd0;
main_litedramcore_inti_p3_rddata <= 32'd0;
if (main_litedramcore_sel) begin
end else begin
main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
end
// synthesis translate_off
dummy_d_105 = dummy_s;
@ -4645,11 +4645,10 @@ end
reg dummy_d_107;
// synthesis translate_on
always @(*) begin
main_litedramcore_master_p2_rddata_en <= 1'd0;
main_litedramcore_inti_p3_rddata_valid <= 1'd0;
if (main_litedramcore_sel) begin
main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
end else begin
main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
end
// synthesis translate_off
dummy_d_107 = dummy_s;
@ -4660,11 +4659,11 @@ end
reg dummy_d_108;
// synthesis translate_on
always @(*) begin
main_litedramcore_master_p3_address <= 15'd0;
main_litedramcore_master_p2_rddata_en <= 1'd0;
if (main_litedramcore_sel) begin
main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
end else begin
main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
end
// synthesis translate_off
dummy_d_108 = dummy_s;
@ -4675,10 +4674,11 @@ end
reg dummy_d_109;
// synthesis translate_on
always @(*) begin
main_litedramcore_slave_p3_rddata <= 32'd0;
main_litedramcore_master_p3_address <= 15'd0;
if (main_litedramcore_sel) begin
main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
end else begin
main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
end
// synthesis translate_off
dummy_d_109 = dummy_s;
@ -11032,10 +11032,14 @@ end
reg dummy_d_288;
// synthesis translate_on
always @(*) begin
main_litedramcore_en1 <= 1'd0;
main_litedramcore_choose_req_cmd_ready <= 1'd0;
case (builder_multiplexer_state)
1'd1: begin
main_litedramcore_en1 <= 1'd1;
if (1'd0) begin
main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
end else begin
main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
end
end
2'd2: begin
end
@ -11056,6 +11060,11 @@ always @(*) begin
4'd10: begin
end
default: begin
if (1'd0) begin
main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
end else begin
main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
end
end
endcase
// synthesis translate_off
@ -11066,6 +11075,41 @@ end
// synthesis translate_off
reg dummy_d_289;
// synthesis translate_on
always @(*) begin
main_litedramcore_en1 <= 1'd0;
case (builder_multiplexer_state)
1'd1: begin
main_litedramcore_en1 <= 1'd1;
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
end
endcase
// synthesis translate_off
dummy_d_289 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_290;
// synthesis translate_on
always @(*) begin
main_litedramcore_steerer_sel0 <= 2'd0;
case (builder_multiplexer_state)
@ -11108,12 +11152,12 @@ always @(*) begin
end
endcase
// synthesis translate_off
dummy_d_289 = dummy_s;
dummy_d_290 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_290;
reg dummy_d_291;
// synthesis translate_on
always @(*) begin
main_litedramcore_steerer_sel1 <= 2'd0;
@ -11156,12 +11200,12 @@ always @(*) begin
end
endcase
// synthesis translate_off
dummy_d_290 = dummy_s;
dummy_d_291 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_291;
reg dummy_d_292;
// synthesis translate_on
always @(*) begin
main_litedramcore_cmd_ready <= 1'd0;
@ -11191,12 +11235,12 @@ always @(*) begin
end
endcase
// synthesis translate_off
dummy_d_291 = dummy_s;
dummy_d_292 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_292;
reg dummy_d_293;
// synthesis translate_on
always @(*) begin
main_litedramcore_steerer_sel2 <= 2'd0;
@ -11239,12 +11283,12 @@ always @(*) begin
end
endcase
// synthesis translate_off
dummy_d_292 = dummy_s;
dummy_d_293 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_293;
reg dummy_d_294;
// synthesis translate_on
always @(*) begin
main_litedramcore_choose_cmd_want_activates <= 1'd0;
@ -11281,12 +11325,12 @@ always @(*) begin
end
endcase
// synthesis translate_off
dummy_d_293 = dummy_s;
dummy_d_294 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_294;
reg dummy_d_295;
// synthesis translate_on
always @(*) begin
main_litedramcore_steerer_sel3 <= 2'd0;
@ -11329,12 +11373,12 @@ always @(*) begin
end
endcase
// synthesis translate_off
dummy_d_294 = dummy_s;
dummy_d_295 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_295;
reg dummy_d_296;
// synthesis translate_on
always @(*) begin
main_litedramcore_en0 <= 1'd0;
@ -11364,12 +11408,12 @@ always @(*) begin
end
endcase
// synthesis translate_off
dummy_d_295 = dummy_s;
dummy_d_296 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_296;
reg dummy_d_297;
// synthesis translate_on
always @(*) begin
main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
@ -11405,41 +11449,6 @@ always @(*) begin
end
end
endcase
// synthesis translate_off
dummy_d_296 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_297;
// synthesis translate_on
always @(*) begin
main_litedramcore_choose_req_want_reads <= 1'd0;
case (builder_multiplexer_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
main_litedramcore_choose_req_want_reads <= 1'd1;
end
endcase
// synthesis translate_off
dummy_d_297 = dummy_s;
// synthesis translate_on
@ -11449,10 +11458,9 @@ end
reg dummy_d_298;
// synthesis translate_on
always @(*) begin
main_litedramcore_choose_req_want_writes <= 1'd0;
main_litedramcore_choose_req_want_reads <= 1'd0;
case (builder_multiplexer_state)
1'd1: begin
main_litedramcore_choose_req_want_writes <= 1'd1;
end
2'd2: begin
end
@ -11473,6 +11481,7 @@ always @(*) begin
4'd10: begin
end
default: begin
main_litedramcore_choose_req_want_reads <= 1'd1;
end
endcase
// synthesis translate_off
@ -11484,14 +11493,10 @@ end
reg dummy_d_299;
// synthesis translate_on
always @(*) begin
main_litedramcore_choose_req_cmd_ready <= 1'd0;
main_litedramcore_choose_req_want_writes <= 1'd0;
case (builder_multiplexer_state)
1'd1: begin
if (1'd0) begin
main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
end else begin
main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
end
main_litedramcore_choose_req_want_writes <= 1'd1;
end
2'd2: begin
end
@ -11512,11 +11517,6 @@ always @(*) begin
4'd10: begin
end
default: begin
if (1'd0) begin
main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
end else begin
main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
end
end
endcase
// synthesis translate_off
@ -11571,13 +11571,13 @@ assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
reg dummy_d_300;
// synthesis translate_on
always @(*) begin
main_litedramcore_interface_wdata_we <= 16'd0;
main_litedramcore_interface_wdata <= 128'd0;
case ({builder_new_master_wdata_ready1})
1'd1: begin
main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
end
default: begin
main_litedramcore_interface_wdata_we <= 1'd0;
main_litedramcore_interface_wdata <= 1'd0;
end
endcase
// synthesis translate_off
@ -11589,13 +11589,13 @@ end
reg dummy_d_301;
// synthesis translate_on
always @(*) begin
main_litedramcore_interface_wdata <= 128'd0;
main_litedramcore_interface_wdata_we <= 16'd0;
case ({builder_new_master_wdata_ready1})
1'd1: begin
main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
end
default: begin
main_litedramcore_interface_wdata <= 1'd0;
main_litedramcore_interface_wdata_we <= 1'd0;
end
endcase
// synthesis translate_off
@ -11810,7 +11810,7 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we;
assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
assign main_wb_bus_err = builder_litedramcore_wishbone_err;
assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1);
assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];

// synthesis translate_off
@ -11867,7 +11867,7 @@ always @(*) begin
end
assign builder_csrbank0_init_done0_w = main_init_done_storage;
assign builder_csrbank0_init_error0_w = main_init_error_storage;
assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2);
assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];

// synthesis translate_off
@ -11928,9 +11928,9 @@ assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
reg dummy_d_319;
// synthesis translate_on
always @(*) begin
builder_csrbank1_wlevel_en0_re <= 1'd0;
builder_csrbank1_wlevel_en0_we <= 1'd0;
if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
end
// synthesis translate_off
dummy_d_319 = dummy_s;
@ -11941,9 +11941,9 @@ end
reg dummy_d_320;
// synthesis translate_on
always @(*) begin
builder_csrbank1_wlevel_en0_we <= 1'd0;
builder_csrbank1_wlevel_en0_re <= 1'd0;
if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
end
// synthesis translate_off
dummy_d_320 = dummy_s;
@ -11955,9 +11955,9 @@ assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
reg dummy_d_321;
// synthesis translate_on
always @(*) begin
main_a7ddrphy_wlevel_strobe_re <= 1'd0;
main_a7ddrphy_wlevel_strobe_we <= 1'd0;
if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
end
// synthesis translate_off
dummy_d_321 = dummy_s;
@ -11968,9 +11968,9 @@ end
reg dummy_d_322;
// synthesis translate_on
always @(*) begin
main_a7ddrphy_wlevel_strobe_we <= 1'd0;
main_a7ddrphy_wlevel_strobe_re <= 1'd0;
if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
end
// synthesis translate_off
dummy_d_322 = dummy_s;
@ -12063,9 +12063,9 @@ assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0
reg dummy_d_329;
// synthesis translate_on
always @(*) begin
main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
end
// synthesis translate_off
dummy_d_329 = dummy_s;
@ -12076,9 +12076,9 @@ end
reg dummy_d_330;
// synthesis translate_on
always @(*) begin
main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
end
// synthesis translate_off
dummy_d_330 = dummy_s;
@ -12225,7 +12225,7 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];

// synthesis translate_off
@ -12313,9 +12313,9 @@ assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[
reg dummy_d_347;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
end
// synthesis translate_off
dummy_d_347 = dummy_s;
@ -12326,9 +12326,9 @@ end
reg dummy_d_348;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
end
// synthesis translate_off
dummy_d_348 = dummy_s;
@ -12421,9 +12421,9 @@ assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7
reg dummy_d_355;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
end
// synthesis translate_off
dummy_d_355 = dummy_s;
@ -12434,9 +12434,9 @@ end
reg dummy_d_356;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
end
// synthesis translate_off
dummy_d_356 = dummy_s;
@ -12664,9 +12664,9 @@ assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[
reg dummy_d_373;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
end
// synthesis translate_off
dummy_d_373 = dummy_s;
@ -12677,9 +12677,9 @@ end
reg dummy_d_374;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
end
// synthesis translate_off
dummy_d_374 = dummy_s;
@ -12772,9 +12772,9 @@ assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7
reg dummy_d_381;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
end
// synthesis translate_off
dummy_d_381 = dummy_s;
@ -12785,9 +12785,9 @@ end
reg dummy_d_382;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
end
// synthesis translate_off
dummy_d_382 = dummy_s;
@ -12988,9 +12988,9 @@ assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_ban
reg dummy_d_397;
// synthesis translate_on
always @(*) begin
main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
end
// synthesis translate_off
dummy_d_397 = dummy_s;
@ -13001,9 +13001,9 @@ end
reg dummy_d_398;
// synthesis translate_on
always @(*) begin
main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
end
// synthesis translate_off
dummy_d_398 = dummy_s;
@ -13015,9 +13015,9 @@ assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[
reg dummy_d_399;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
end
// synthesis translate_off
dummy_d_399 = dummy_s;
@ -13028,9 +13028,9 @@ end
reg dummy_d_400;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
end
// synthesis translate_off
dummy_d_400 = dummy_s;
@ -13123,9 +13123,9 @@ assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7
reg dummy_d_407;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
end
// synthesis translate_off
dummy_d_407 = dummy_s;
@ -13136,9 +13136,9 @@ end
reg dummy_d_408;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
end
// synthesis translate_off
dummy_d_408 = dummy_s;
@ -13366,9 +13366,9 @@ assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[
reg dummy_d_425;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
end
// synthesis translate_off
dummy_d_425 = dummy_s;
@ -13379,9 +13379,9 @@ end
reg dummy_d_426;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
end
// synthesis translate_off
dummy_d_426 = dummy_s;
@ -13474,9 +13474,9 @@ assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7
reg dummy_d_433;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
end
// synthesis translate_off
dummy_d_433 = dummy_s;
@ -13487,9 +13487,9 @@ end
reg dummy_d_434;
// synthesis translate_on
always @(*) begin
builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
end
// synthesis translate_off
dummy_d_434 = dummy_s;

File diff suppressed because it is too large Load Diff

@ -1,5 +1,5 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:19
// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:42
//--------------------------------------------------------------------------------
module litedram_core(
input wire sim_trace,
@ -2124,36 +2124,36 @@ always @(*) begin
soc_ddrphy_activates1[3] = soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
soc_ddrphy_bankmodel1_activate = 1'd0;
soc_ddrphy_bankmodel1_activate_row = 14'd0;
case (soc_ddrphy_activates1)
1'd1: begin
soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p0_bank == 1'd1);
soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p1_bank == 1'd1);
soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p2_bank == 1'd1);
soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p3_bank == 1'd1);
soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel1_activate_row = 14'd0;
soc_ddrphy_bankmodel1_activate = 1'd0;
case (soc_ddrphy_activates1)
1'd1: begin
soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p0_address;
soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p0_bank == 1'd1);
end
2'd2: begin
soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p1_address;
soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p1_bank == 1'd1);
end
3'd4: begin
soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p2_address;
soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p2_bank == 1'd1);
end
4'd8: begin
soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p3_address;
soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p3_bank == 1'd1);
end
endcase
end
@ -2838,36 +2838,36 @@ always @(*) begin
soc_ddrphy_reads5[3] = soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
soc_ddrphy_bankmodel5_read_col = 10'd0;
soc_ddrphy_bankmodel5_read = 1'd0;
case (soc_ddrphy_reads5)
1'd1: begin
soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p0_address;
soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p0_bank == 3'd5);
end
2'd2: begin
soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p1_address;
soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p1_bank == 3'd5);
end
3'd4: begin
soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p2_address;
soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p2_bank == 3'd5);
end
4'd8: begin
soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p3_address;
soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p3_bank == 3'd5);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel5_read = 1'd0;
soc_ddrphy_bankmodel5_read_col = 10'd0;
case (soc_ddrphy_reads5)
1'd1: begin
soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p0_bank == 3'd5);
soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p1_bank == 3'd5);
soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p2_bank == 3'd5);
soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p3_bank == 3'd5);
soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p3_address;
end
endcase
end
@ -3030,36 +3030,36 @@ always @(*) begin
soc_ddrphy_activates7[3] = soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
soc_ddrphy_bankmodel7_activate_row = 14'd0;
soc_ddrphy_bankmodel7_activate = 1'd0;
case (soc_ddrphy_activates7)
1'd1: begin
soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p0_address;
soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p0_bank == 3'd7);
end
2'd2: begin
soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p1_address;
soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p1_bank == 3'd7);
end
3'd4: begin
soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p2_address;
soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p2_bank == 3'd7);
end
4'd8: begin
soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p3_address;
soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p3_bank == 3'd7);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel7_activate = 1'd0;
soc_ddrphy_bankmodel7_activate_row = 14'd0;
case (soc_ddrphy_activates7)
1'd1: begin
soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p0_bank == 3'd7);
soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p1_bank == 3'd7);
soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p2_bank == 3'd7);
soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p3_bank == 3'd7);
soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p3_address;
end
endcase
end
@ -3140,36 +3140,36 @@ always @(*) begin
soc_ddrphy_reads7[3] = soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
soc_ddrphy_bankmodel7_read = 1'd0;
soc_ddrphy_bankmodel7_read_col = 10'd0;
case (soc_ddrphy_reads7)
1'd1: begin
soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p0_bank == 3'd7);
soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p1_bank == 3'd7);
soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p2_bank == 3'd7);
soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p3_bank == 3'd7);
soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel7_read_col = 10'd0;
soc_ddrphy_bankmodel7_read = 1'd0;
case (soc_ddrphy_reads7)
1'd1: begin
soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p0_address;
soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p0_bank == 3'd7);
end
2'd2: begin
soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p1_address;
soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p1_bank == 3'd7);
end
3'd4: begin
soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p2_address;
soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p2_bank == 3'd7);
end
4'd8: begin
soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p3_address;
soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p3_bank == 3'd7);
end
endcase
end
@ -3321,6 +3321,14 @@ always @(*) begin
end
assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[24:3];
assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3];
always @(*) begin
soc_ddrphy_bankmodel1_read_data = 128'd0;
if (soc_ddrphy_bankmodel1_active) begin
if (soc_ddrphy_bankmodel1_read) begin
soc_ddrphy_bankmodel1_read_data = soc_ddrphy_bankmodel1_read_port_dat_r;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
if (soc_ddrphy_bankmodel1_active) begin
@ -3351,14 +3359,6 @@ always @(*) begin
end
end
end
always @(*) begin
soc_ddrphy_bankmodel1_read_data = 128'd0;
if (soc_ddrphy_bankmodel1_active) begin
if (soc_ddrphy_bankmodel1_read) begin
soc_ddrphy_bankmodel1_read_data = soc_ddrphy_bankmodel1_read_port_dat_r;
end
end
end
assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[24:3];
assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3];
always @(*) begin
@ -3441,6 +3441,12 @@ always @(*) begin
end
assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3];
assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3];
always @(*) begin
soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
if (soc_ddrphy_bankmodel4_active) begin
soc_ddrphy_bankmodel4_write_port_dat_w = soc_ddrphy_bankmodel4_write_data;
end
end
always @(*) begin
soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
if (soc_ddrphy_bankmodel4_active) begin
@ -3473,12 +3479,6 @@ always @(*) begin
end
end
end
always @(*) begin
soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
if (soc_ddrphy_bankmodel4_active) begin
soc_ddrphy_bankmodel4_write_port_dat_w = soc_ddrphy_bankmodel4_write_data;
end
end
assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
always @(*) begin
@ -3944,14 +3944,6 @@ always @(*) begin
soc_litedramcore_inti_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid;
end
end
always @(*) begin
soc_litedramcore_master_p0_ras_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_ras_n = soc_litedramcore_slave_p0_ras_n;
end else begin
soc_litedramcore_master_p0_ras_n = soc_litedramcore_inti_p0_ras_n;
end
end
always @(*) begin
soc_litedramcore_master_p1_wrdata_mask = 4'd0;
if (soc_litedramcore_sel) begin
@ -3968,6 +3960,14 @@ always @(*) begin
soc_litedramcore_master_p1_rddata_en = soc_litedramcore_inti_p1_rddata_en;
end
end
always @(*) begin
soc_litedramcore_master_p0_ras_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_ras_n = soc_litedramcore_slave_p0_ras_n;
end else begin
soc_litedramcore_master_p0_ras_n = soc_litedramcore_inti_p0_ras_n;
end
end
always @(*) begin
soc_litedramcore_master_p2_address = 14'd0;
if (soc_litedramcore_sel) begin
@ -9670,10 +9670,10 @@ always @(*) begin
endcase
end
always @(*) begin
soc_litedramcore_en1 = 1'd0;
soc_litedramcore_choose_req_want_writes = 1'd0;
case (multiplexer_state)
1'd1: begin
soc_litedramcore_en1 = 1'd1;
soc_litedramcore_choose_req_want_writes = 1'd1;
end
2'd2: begin
end
@ -9698,10 +9698,10 @@ always @(*) begin
endcase
end
always @(*) begin
soc_litedramcore_choose_req_want_writes = 1'd0;
soc_litedramcore_en1 = 1'd0;
case (multiplexer_state)
1'd1: begin
soc_litedramcore_choose_req_want_writes = 1'd1;
soc_litedramcore_en1 = 1'd1;
end
2'd2: begin
end
@ -9806,24 +9806,24 @@ assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) &
assign soc_user_port_wdata_ready = new_master_wdata_ready1;
assign soc_user_port_rdata_valid = new_master_rdata_valid8;
always @(*) begin
soc_litedramcore_interface_wdata_we = 16'd0;
soc_litedramcore_interface_wdata = 128'd0;
case ({new_master_wdata_ready1})
1'd1: begin
soc_litedramcore_interface_wdata_we = soc_user_port_wdata_payload_we;
soc_litedramcore_interface_wdata = soc_user_port_wdata_payload_data;
end
default: begin
soc_litedramcore_interface_wdata_we = 1'd0;
soc_litedramcore_interface_wdata = 1'd0;
end
endcase
end
always @(*) begin
soc_litedramcore_interface_wdata = 128'd0;
soc_litedramcore_interface_wdata_we = 16'd0;
case ({new_master_wdata_ready1})
1'd1: begin
soc_litedramcore_interface_wdata = soc_user_port_wdata_payload_data;
soc_litedramcore_interface_wdata_we = soc_user_port_wdata_payload_we;
end
default: begin
soc_litedramcore_interface_wdata = 1'd0;
soc_litedramcore_interface_wdata_we = 1'd0;
end
endcase
end
@ -9853,6 +9853,21 @@ always @(*) begin
end
endcase
end
always @(*) begin
litedramcore_adr_next_value1 = 14'd0;
case (state)
1'd1: begin
litedramcore_adr_next_value1 = 1'd0;
end
2'd2: begin
end
default: begin
if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
litedramcore_adr_next_value1 = litedramcore_wishbone_adr;
end
end
endcase
end
always @(*) begin
litedramcore_adr_next_value_ce1 = 1'd0;
case (state)
@ -9946,21 +9961,6 @@ always @(*) begin
end
endcase
end
always @(*) begin
litedramcore_adr_next_value1 = 14'd0;
case (state)
1'd1: begin
litedramcore_adr_next_value1 = 1'd0;
end
2'd2: begin
end
default: begin
if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
litedramcore_adr_next_value1 = litedramcore_wishbone_adr;
end
end
endcase
end
assign litedramcore_wishbone_adr = soc_wb_bus_adr;
assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w;
assign soc_wb_bus_dat_r = litedramcore_wishbone_dat_r;
@ -9972,7 +9972,7 @@ assign litedramcore_wishbone_we = soc_wb_bus_we;
assign litedramcore_wishbone_cti = soc_wb_bus_cti;
assign litedramcore_wishbone_bte = soc_wb_bus_bte;
assign soc_wb_bus_err = litedramcore_wishbone_err;
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd1);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
csrbank0_init_done0_we = 1'd0;
@ -10001,7 +10001,7 @@ always @(*) begin
end
assign csrbank0_init_done0_w = soc_init_done_storage;
assign csrbank0_init_error0_w = soc_init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0);
assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
always @(*) begin
csrbank1_dfii_control0_re = 1'd0;
@ -10017,15 +10017,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
csrbank1_dfii_pi0_command0_re = 1'd0;
csrbank1_dfii_pi0_command0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
csrbank1_dfii_pi0_command0_re = interface1_bank_bus_we;
csrbank1_dfii_pi0_command0_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi0_command0_we = 1'd0;
csrbank1_dfii_pi0_command0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
csrbank1_dfii_pi0_command0_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi0_command0_re = interface1_bank_bus_we;
end
end
assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
@ -10082,15 +10082,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi0_wrdata3_we = 1'd0;
csrbank1_dfii_pi0_wrdata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
csrbank1_dfii_pi0_wrdata3_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi0_wrdata3_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi0_wrdata3_re = 1'd0;
csrbank1_dfii_pi0_wrdata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
csrbank1_dfii_pi0_wrdata3_re = interface1_bank_bus_we;
csrbank1_dfii_pi0_wrdata3_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0];
@ -10134,15 +10134,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi0_rddata3_re = 1'd0;
csrbank1_dfii_pi0_rddata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
csrbank1_dfii_pi0_rddata3_re = interface1_bank_bus_we;
csrbank1_dfii_pi0_rddata3_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi0_rddata3_we = 1'd0;
csrbank1_dfii_pi0_rddata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
csrbank1_dfii_pi0_rddata3_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi0_rddata3_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0];
@ -10160,15 +10160,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi0_rddata1_we = 1'd0;
csrbank1_dfii_pi0_rddata1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
csrbank1_dfii_pi0_rddata1_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi0_rddata1_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi0_rddata1_re = 1'd0;
csrbank1_dfii_pi0_rddata1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
csrbank1_dfii_pi0_rddata1_re = interface1_bank_bus_we;
csrbank1_dfii_pi0_rddata1_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0];
@ -10186,15 +10186,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
csrbank1_dfii_pi1_command0_re = 1'd0;
csrbank1_dfii_pi1_command0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
csrbank1_dfii_pi1_command0_re = interface1_bank_bus_we;
csrbank1_dfii_pi1_command0_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi1_command0_we = 1'd0;
csrbank1_dfii_pi1_command0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
csrbank1_dfii_pi1_command0_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi1_command0_re = interface1_bank_bus_we;
end
end
assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
@ -10251,15 +10251,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi1_wrdata3_we = 1'd0;
csrbank1_dfii_pi1_wrdata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
csrbank1_dfii_pi1_wrdata3_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi1_wrdata3_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi1_wrdata3_re = 1'd0;
csrbank1_dfii_pi1_wrdata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
csrbank1_dfii_pi1_wrdata3_re = interface1_bank_bus_we;
csrbank1_dfii_pi1_wrdata3_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0];
@ -10303,15 +10303,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi1_rddata3_re = 1'd0;
csrbank1_dfii_pi1_rddata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
csrbank1_dfii_pi1_rddata3_re = interface1_bank_bus_we;
csrbank1_dfii_pi1_rddata3_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi1_rddata3_we = 1'd0;
csrbank1_dfii_pi1_rddata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
csrbank1_dfii_pi1_rddata3_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi1_rddata3_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0];
@ -10329,15 +10329,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi1_rddata1_we = 1'd0;
csrbank1_dfii_pi1_rddata1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin
csrbank1_dfii_pi1_rddata1_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi1_rddata1_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi1_rddata1_re = 1'd0;
csrbank1_dfii_pi1_rddata1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin
csrbank1_dfii_pi1_rddata1_re = interface1_bank_bus_we;
csrbank1_dfii_pi1_rddata1_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0];
@ -10355,28 +10355,28 @@ always @(*) begin
end
assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
csrbank1_dfii_pi2_command0_re = 1'd0;
csrbank1_dfii_pi2_command0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin
csrbank1_dfii_pi2_command0_re = interface1_bank_bus_we;
csrbank1_dfii_pi2_command0_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi2_command0_we = 1'd0;
csrbank1_dfii_pi2_command0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin
csrbank1_dfii_pi2_command0_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi2_command0_re = interface1_bank_bus_we;
end
end
assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin
soc_litedramcore_phaseinjector2_command_issue_we = (~interface1_bank_bus_we);
soc_litedramcore_phaseinjector2_command_issue_re = interface1_bank_bus_we;
end
end
always @(*) begin
soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin
soc_litedramcore_phaseinjector2_command_issue_re = interface1_bank_bus_we;
soc_litedramcore_phaseinjector2_command_issue_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0];
@ -10420,15 +10420,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi2_wrdata3_we = 1'd0;
csrbank1_dfii_pi2_wrdata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin
csrbank1_dfii_pi2_wrdata3_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi2_wrdata3_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi2_wrdata3_re = 1'd0;
csrbank1_dfii_pi2_wrdata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin
csrbank1_dfii_pi2_wrdata3_re = interface1_bank_bus_we;
csrbank1_dfii_pi2_wrdata3_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0];
@ -10472,15 +10472,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi2_rddata3_re = 1'd0;
csrbank1_dfii_pi2_rddata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin
csrbank1_dfii_pi2_rddata3_re = interface1_bank_bus_we;
csrbank1_dfii_pi2_rddata3_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi2_rddata3_we = 1'd0;
csrbank1_dfii_pi2_rddata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin
csrbank1_dfii_pi2_rddata3_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi2_rddata3_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0];
@ -10498,15 +10498,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi2_rddata1_we = 1'd0;
csrbank1_dfii_pi2_rddata1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin
csrbank1_dfii_pi2_rddata1_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi2_rddata1_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi2_rddata1_re = 1'd0;
csrbank1_dfii_pi2_rddata1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin
csrbank1_dfii_pi2_rddata1_re = interface1_bank_bus_we;
csrbank1_dfii_pi2_rddata1_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0];
@ -10524,15 +10524,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
csrbank1_dfii_pi3_command0_re = 1'd0;
csrbank1_dfii_pi3_command0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin
csrbank1_dfii_pi3_command0_re = interface1_bank_bus_we;
csrbank1_dfii_pi3_command0_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi3_command0_we = 1'd0;
csrbank1_dfii_pi3_command0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin
csrbank1_dfii_pi3_command0_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi3_command0_re = interface1_bank_bus_we;
end
end
assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
@ -10589,15 +10589,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi3_wrdata3_we = 1'd0;
csrbank1_dfii_pi3_wrdata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin
csrbank1_dfii_pi3_wrdata3_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi3_wrdata3_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi3_wrdata3_re = 1'd0;
csrbank1_dfii_pi3_wrdata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin
csrbank1_dfii_pi3_wrdata3_re = interface1_bank_bus_we;
csrbank1_dfii_pi3_wrdata3_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0];
@ -10641,15 +10641,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi3_rddata3_re = 1'd0;
csrbank1_dfii_pi3_rddata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin
csrbank1_dfii_pi3_rddata3_re = interface1_bank_bus_we;
csrbank1_dfii_pi3_rddata3_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi3_rddata3_we = 1'd0;
csrbank1_dfii_pi3_rddata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin
csrbank1_dfii_pi3_rddata3_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi3_rddata3_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0];
@ -10667,15 +10667,15 @@ always @(*) begin
end
assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi3_rddata1_we = 1'd0;
csrbank1_dfii_pi3_rddata1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin
csrbank1_dfii_pi3_rddata1_we = (~interface1_bank_bus_we);
csrbank1_dfii_pi3_rddata1_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi3_rddata1_re = 1'd0;
csrbank1_dfii_pi3_rddata1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin
csrbank1_dfii_pi3_rddata1_re = interface1_bank_bus_we;
csrbank1_dfii_pi3_rddata1_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0];

@ -0,0 +1,123 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

library work;
use work.wishbone_types.all;
use work.utils.all;

entity dram_init_mem is
generic (
EXTRA_PAYLOAD_FILE : string := "";
EXTRA_PAYLOAD_SIZE : integer := 0
);
port (
clk : in std_ulogic;
wb_in : in wb_io_master_out;
wb_out : out wb_io_slave_out
);
end entity dram_init_mem;

architecture rtl of dram_init_mem is

constant INIT_RAM_SIZE : integer := 24576;
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
constant INIT_RAM_FILE : string := "litedram_core.init";

type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);

-- XXX FIXME: Have a single init function called twice with
-- an offset as argument
procedure init_load_payload(ram: inout ram_t; filename: string) is
file payload_file : text open read_mode is filename;
variable ram_line : line;
variable temp_word : std_logic_vector(63 downto 0);
begin
for i in 0 to RND_PAYLOAD_SIZE-1 loop
exit when endfile(payload_file);
readline(payload_file, ram_line);
hread(ram_line, temp_word);
ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0);
ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32);
end loop;
assert endfile(payload_file) report "Payload too big !" severity failure;
end procedure;

impure function init_load_ram(name : string) return ram_t is
file ram_file : text open read_mode is name;
variable temp_word : std_logic_vector(63 downto 0);
variable temp_ram : ram_t := (others => (others => '0'));
variable ram_line : line;
begin
report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) &
" rounded to:" & integer'image(RND_PAYLOAD_SIZE);
report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) &
" bytes using " & integer'image(INIT_RAM_ABITS) &
" address bits";
for i in 0 to (INIT_RAM_SIZE/8)-1 loop
exit when endfile(ram_file);
readline(ram_file, ram_line);
hread(ram_line, temp_word);
temp_ram(i*2) := temp_word(31 downto 0);
temp_ram(i*2+1) := temp_word(63 downto 32);
end loop;
if RND_PAYLOAD_SIZE /= 0 then
init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE);
end if;
return temp_ram;
end function;

impure function init_zero return ram_t is
variable temp_ram : ram_t := (others => (others => '0'));
begin
return temp_ram;
end function;

impure function initialize_ram(filename: string) return ram_t is
begin
report "Opening file " & filename;
if filename'length = 0 then
return init_zero;
else
return init_load_ram(filename);
end if;
end function;
signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE);

attribute ram_style : string;
attribute ram_style of init_ram: signal is "block";

signal obuf : std_ulogic_vector(31 downto 0);
signal oack : std_ulogic;
<