Commit Graph

1213 Commits (64997811a8b7933afbb545675ea5a33952e445c1)
 

Author SHA1 Message Date
Anton Blanchard 64997811a8 Fix power plumbing in execute unit 2 years ago
Anton Blanchard 2663326f2c ASIC: Register file updates
The register file is down from 96 entries to 64, and reads
are synchronous.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard b48bf83772 ASIC: Update PVR for MPW7
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 68495c9b4b ASIC: Switch to ghdl --synth
Use ghdl --synth to convert to verilog directly instead of going
through Yosys.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 82c8f48f77 ASIC: Fix multiplier power
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 795d57249f ASIC: Reduce multiplier from 4 to 2 cycles
Our sky130 gate level multiply/adder now makes timing with a single
register stage.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 4fc321cd41 Move register stage back after the RAM
The 512x64 DFFRAM has quite big hold violations that we can hopefully
work around by removing the register stage before the RAM.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 2b47de30c4 Add a script to post process the Microwatt verilog for caravel
To produce verilog suitable for caravel:

make DOCKER=1 FPGA_TARGET=caravel microwatt_asic.v
./caravel/process-microwatt-verilog.sh

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 7e4f627ea4 Add simplebus verilog
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard d2cc31cde4 Add simplebus
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 6745d9dd5f Hook up JTAG to ASIC top level
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 5e025b5b15 Set a unique PVR for caravel MPW5
Set a unique PVR for the caravel MPW5 version of Microwatt

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 26828f6208 Update JTAG TAP controller for Microwatt
Make a few changes to match what mw_debug expects:

- 6 byte instructions
- IDCODE at 001001
- microwatt debug at 000011

Also change IDCODE to be an IBM ID.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 0745cca670 First pass at an external JTAG port
The verilator simulation interface uses the remote_bitbang
protocol from openocd. I have a simple implementation for
urjtag too.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 28debecf1a Add ASIC target
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 01f8ad55ef Move register stage from after RAM to before RAM
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 52f2462232 Add arrays for ASIC flow
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard d8ba6a78d2 Cut down hello_world to fit in 4kB
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Michael Neuling 0073d23e73
Merge pull request #392 from paulusmack/fix-branch-alias
fetch1: Fix bug where BTC entries don't match on MSR[IR]
2 years ago
Michael Neuling f093e30a64 Merge branch 'fix-branch-alias' into branch-alias
Merging Anton's test case for this.

Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling b9efc9a608
Merge pull request #388 from antonblanchard/trace-test
tests/trace: Test trace vs system call interrupt
2 years ago
Paul Mackerras 769f5c3a53 fetch1: Fix bug where BTC entries don't match on MSR[IR]
This fixes a bug in the BTC where entries created for a given address
when MSR[IR] = 0 are used when MSR[IR] = 1 and vice-versa.  The fix is
to include r.virt_mode (which mirrors MSR[IR]) in the tag portion of
the BTC.

Fixes: 0fb207be60 ("fetch1: Implement a simple branch target cache", 2020-12-19)
Reported-by: Anton Blanchard <anton@linux.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Anton Blanchard 25f93fc17e Add branch alias test
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Michael Neuling 2562053af3
Merge pull request #390 from shenki/fix-whide-warnings
Fix -Whide warnings
2 years ago
Anton Blanchard 3c9b3c39ae
Merge pull request #389 from paulusmack/fix-sc
execute1: Fix trace interrupt on sc instruction
2 years ago
Anton Blanchard 3c27abcc40 tests/trace: Test trace vs system call interrupt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Paul Mackerras 939c7e39dd execute1: Fix trace interrupt on sc instruction
This fixes a bug which causes a trace interrupt to store the wrong
value in SRR0 in the case where the instruction that has just
completed is followed by a sc (system call) instruction.  What happens
is that first the traced instruction sets ex1.trace_next.  Then, when
the sc instruction following it comes in, the execute1_actions process
sets v.e.last_nia to next_nia because it is an sc instruction, even
though it is not going to be executed -- we are going to take the
trace interrupt instead.  Then when the trace interrupt is taken, we
incorrectly set SRR0 to the incremented address (the address of the
instruction following the sc).

To fix this, we have execute1_actions set a new flag if the current
instruction is sc, and only set v.e.last_nia to next_nia if we
actually execute the sc (in the "if go = '1'" case).

Fixes: 813e2317bf ("execute1: Restructure to separate out execution of side effects", 2022-06-18)
Reported-by: Anton Blanchard <anton@linux.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Joel Stanley dc6a4b1406 soc: Fix -Whide warning
soc.vhdl:847:9⚠️ declaration of "uart1" hides if generate statement [-Whide]
        uart1: uart_top
        ^

Signed-off-by: Joel Stanley <joel@jms.id.au>
2 years ago
Joel Stanley c6ca844c88 xics: Fix -Whide warnings
xics.vhdl:83:25⚠️ declaration of "v" hides variable "v" [-Whide]
        function  bswap(v : in std_ulogic_vector(31 downto 0)) return std_ulogic_vector is

xics.vhdl:84:22⚠️ declaration of "r" hides signal "r" [-Whide]
            variable r : std_ulogic_vector(31 downto 0);

Signed-off-by: Joel Stanley <joel@jms.id.au>
2 years ago
Joel Stanley 60c54fb959 fpu: Fix -Whide warnings
fpu.vhdl:513:18⚠️ declaration of "result" hides signal "result" [-Whide]
         variable result : std_ulogic_vector(63 downto 0);

Signed-off-by: Joel Stanley <joel@jms.id.au>
2 years ago
Michael Neuling 2641e6d5cd
Merge pull request #387 from antonblanchard/gitignore
Add litesdcard/build to gitignore
2 years ago
Anton Blanchard ad37b2e07c Add litesdcard/build to gitignore
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Paul Mackerras a2c9c9b3cf
Merge pull request #384 from antonblanchard/litedram-update
Litedram update
2 years ago
Anton Blanchard aa1d2b16d7 litedram: Regenerate
Regenerate from upstream litex. Something in the update has improved
memory read and write performance quite a lot on my Nexys Video:

Before:

  Write speed: 83.2MiB/s
   Read speed: 140.4MiB/s

After:

  Write speed: 352.1MiB/s
   Read speed: 218.5MiB/s

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard e0bf743d7a litedram: MIGEN_GIT_SHA1 no longer defined
MIGEN_GIT_SHA1 is no longer defined in upstream litex, so remove it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Paul Mackerras 2ca21ebcae
Merge pull request #383 from antonblanchard/fix-sdcard
litesdcard: Fix and regenerate Verilog
2 years ago
Anton Blanchard 83fe8b629c litesdcard: Fix and regenerate Verilog
Fix the litex generate script to pass frequencies in Hz. Regenerate
the litesdcard Verilog for both Xilinx and Lattice. This fixes
litesdcard on my Nexys Video.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Paul Mackerras 76a7b98840
Merge pull request #381 from shingarov/gitignore-artifacts
Gitignore build artifacts
2 years ago
Paul Mackerras de8fd492c8
Merge pull request #378 from mikey/ux-cleanup
Metavalue cleanup
2 years ago
Boris Shingarov 8e234ddb5a Gitignore build artifacts
Building the mw_debug program leaves build artifacts in
microwatt/scripts/mw_debug
causing noise in the output of `git status`.
This commit adds them to .gitignore.

Signed-off-by: Boris Shingarov <shingarov@labware.com>
2 years ago
Michael Neuling eeac86c9d8 test: Add test for metavalues
Make sure they don't increase in future

Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling 72fcca8e52 tests: Update FPU test output
The following commit added two tests but didn't update the tests
outputs:

    commit 73cc5167ec
    Author: Paul Mackerras <paulus@ozlabs.org>
    Date:   Mon May 9 19:18:42 2022 +1000
    Use FPU for division instructions if we have an FPU

This patch updates these using tests/update_console_tests

Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling f34b2488e4 tests: Minor script cleanups
Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling 438a76dafd Metavalue cleanup for register_file.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling 7a3e5cac3b Metavalue cleanup for pmu.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling 43e62dbd9e Metavalue cleanup for rotator.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling 5a03de4c90 Metavalue cleanup for mmu.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling 738702f2e2 Metavalue cleanup for loadstore1.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling 404abefd92 Metavalue cleanup for icache.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling 43dadca052 Metavalue cleanup for fpu.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago