Add arrays for ASIC flow
Add VHDL wrappers and verilog behaviourals for the cache_ram, register_file and main_bram arrays. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>caravel-mpw7-20220822
Anton Blanchard
parent
d8ba6a78d2
commit
52f2462232
@ -0,0 +1,24 @@
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module Microwatt_FP_DFFRFile (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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input [6:0] R1, R2, R3, RW,
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input [63:0] DW,
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output [63:0] D1, D2, D3,
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input CLK,
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input WE
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);
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reg [63:0] registers[0:95];
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assign D1 = registers[R1];
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assign D2 = registers[R2];
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assign D3 = registers[R3];
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always @(posedge CLK) begin
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if (WE)
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registers[RW] <= DW;
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end
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endmodule
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@ -0,0 +1,40 @@
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module RAM32_1RW1R #(
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parameter BITS=5
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) (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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input CLK,
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input EN0,
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input [BITS-1:0] A0,
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input [7:0] WE0,
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input [63:0] Di0,
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output reg [63:0] Do0,
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input EN1,
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input [BITS-1:0] A1,
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output reg [63:0] Do1
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);
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reg [63:0] RAM[2**BITS-1:0];
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always @(posedge CLK) begin
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if (EN1)
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Do1 <= RAM[A1];
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end
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generate
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genvar i;
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for (i=0; i<8; i=i+1) begin: BYTE
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always @(posedge CLK) begin
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if (EN0) begin
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if (WE0[i])
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RAM[A0][i*8+7:i*8] <= Di0[i*8+7:i*8];
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end
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end
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end
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endgenerate
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endmodule
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@ -0,0 +1,42 @@
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module RAM512 #(
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parameter BITS=9,
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parameter FILENAME="firmware.hex"
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) (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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input CLK,
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input [7:0] WE0,
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input EN0,
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input [63:0] Di0,
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output reg [63:0] Do0,
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input [BITS-1:0] A0
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);
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reg [63:0] RAM[2**BITS-1:0];
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always @(posedge CLK) begin
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if (EN0)
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Do0 <= RAM[A0];
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else
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Do0 <= 64'b0;
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end
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generate
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genvar i;
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for (i=0; i<8; i=i+1) begin: BYTE
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always @(posedge CLK) begin
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if (EN0) begin
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if (WE0[i])
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RAM[A0][i*8+7:i*8] <= Di0[i*8+7:i*8];
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end
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end
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end
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endgenerate
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initial begin
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$readmemh(FILENAME, RAM);
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end
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endmodule
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@ -0,0 +1,24 @@
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module multiply_add_64x64
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#(
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parameter BITS=64
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) (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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input clk,
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input [BITS-1:0] a,
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input [BITS-1:0] b,
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input [BITS*2-1:0] c,
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output [BITS*2-1:0] o
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);
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reg [BITS*2-1:0] o_tmp[2:0];
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always @(posedge clk) begin
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o_tmp[2] = o_tmp[1];
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o_tmp[1] = o_tmp[0];
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o_tmp[0] = (a * b) + c;
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end
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assign o = o_tmp[2];
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endmodule
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@ -0,0 +1,99 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity cache_ram is
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generic(
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ROW_BITS : integer := 5;
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WIDTH : integer := 64;
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TRACE : boolean := false;
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ADD_BUF : boolean := false
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);
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port(
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clk : in std_logic;
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rd_en : in std_logic;
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rd_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
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rd_data : out std_logic_vector(WIDTH - 1 downto 0);
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wr_sel : in std_logic_vector(WIDTH/8 - 1 downto 0);
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wr_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
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wr_data : in std_logic_vector(WIDTH - 1 downto 0)
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);
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end cache_ram;
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architecture rtl of cache_ram is
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component RAM32_1RW1R port(
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CLK : in std_logic;
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EN0 : in std_logic;
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A0 : in std_logic_vector(4 downto 0);
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WE0 : in std_logic_vector(7 downto 0);
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Di0 : in std_logic_vector(63 downto 0);
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Do0 : out std_logic_vector(63 downto 0);
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EN1 : in std_logic;
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A1 : in std_logic_vector(4 downto 0);
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Do1 : out std_logic_vector(63 downto 0)
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);
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end component;
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signal wr_enable: std_logic;
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signal rd_data0_tmp : std_logic_vector(WIDTH - 1 downto 0);
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signal rd_data0_saved : std_logic_vector(WIDTH - 1 downto 0);
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signal rd_data0 : std_logic_vector(WIDTH - 1 downto 0);
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signal rd_en_prev: std_ulogic;
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begin
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assert (ROW_BITS = 5) report "ROW_BITS must be 5" severity FAILURE;
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assert (WIDTH = 64) report "Must be 64 bit" severity FAILURE;
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assert (TRACE = false) report "Trace not supported" severity FAILURE;
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wr_enable <= or(wr_sel);
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cache_ram_0 : RAM32_1RW1R
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port map (
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CLK => clk,
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EN0 => wr_enable,
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A0 => wr_addr,
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WE0 => wr_sel,
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Di0 => wr_data,
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Do0 => open,
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EN1 => rd_en,
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A1 => rd_addr,
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Do1 => rd_data0_tmp
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);
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-- The caches rely on cache_ram latching the last read. Handle it here
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-- for now.
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process(clk)
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begin
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if rising_edge(clk) then
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rd_en_prev <= rd_en;
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if rd_en_prev = '1' then
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rd_data0_saved <= rd_data0_tmp;
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end if;
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end if;
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end process;
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rd_data0 <= rd_data0_tmp when rd_en_prev = '1' else rd_data0_saved;
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buf: if ADD_BUF generate
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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rd_data <= rd_data0;
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end if;
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end process;
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end generate;
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nobuf: if not ADD_BUF generate
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begin
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rd_data <= rd_data0;
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end generate;
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end architecture rtl;
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@ -0,0 +1,63 @@
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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entity main_bram is
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generic(
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WIDTH : natural := 64;
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HEIGHT_BITS : natural;
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MEMORY_SIZE : natural;
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RAM_INIT_FILE : string
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);
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port(
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clk : in std_logic;
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addr : in std_logic_vector(HEIGHT_BITS - 1 downto 0) ;
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din : in std_logic_vector(WIDTH-1 downto 0);
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dout : out std_logic_vector(WIDTH-1 downto 0);
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sel : in std_logic_vector((WIDTH/8)-1 downto 0);
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re : in std_ulogic;
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we : in std_ulogic
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);
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end entity main_bram;
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architecture behaviour of main_bram is
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component RAM512 port (
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CLK : in std_ulogic;
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WE0 : in std_ulogic_vector(7 downto 0);
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EN0 : in std_ulogic;
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Di0 : in std_ulogic_vector(63 downto 0);
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Do0 : out std_ulogic_vector(63 downto 0);
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A0 : in std_ulogic_vector(8 downto 0)
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);
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end component;
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signal sel_qual: std_ulogic_vector((WIDTH/8)-1 downto 0);
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signal obuf : std_logic_vector(WIDTH-1 downto 0);
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begin
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assert (WIDTH = 64) report "Must be 64 bit" severity FAILURE;
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-- Do we have a log2 round up issue here?
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assert (HEIGHT_BITS = 9) report "HEIGHT_BITS must be 10" severity FAILURE;
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assert (MEMORY_SIZE = 4096) report "MEMORY_SIZE must be 4096" severity FAILURE;
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sel_qual <= sel when we = '1' else (others => '0');
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memory_0 : RAM512
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port map (
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CLK => clk,
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WE0 => sel_qual(7 downto 0),
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EN0 => re or we,
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Di0 => din(63 downto 0),
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Do0 => obuf(63 downto 0),
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A0 => addr(8 downto 0)
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);
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-- The wishbone BRAM wrapper assumes a 1 cycle delay
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memory_read_buffer: process(clk)
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begin
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if rising_edge(clk) then
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dout <= obuf;
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end if;
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end process;
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end architecture behaviour;
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@ -0,0 +1,128 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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-- XXX We should be able to make timing with a 2 cycle multiplier
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entity multiply is
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generic (
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PIPELINE_DEPTH : natural := 4
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);
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port (
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clk : in std_logic;
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m_in : in MultiplyInputType;
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m_out : out MultiplyOutputType
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);
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end entity multiply;
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architecture behaviour of multiply is
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signal m: MultiplyInputType := MultiplyInputInit;
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type multiply_pipeline_stage is record
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valid : std_ulogic;
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is_32bit : std_ulogic;
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not_res : std_ulogic;
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end record;
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constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0',
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is_32bit => '0',
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not_res => '0');
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type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
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constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
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type reg_type is record
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multiply_pipeline : multiply_pipeline_type;
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end record;
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signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
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signal overflow : std_ulogic;
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signal ovf_in : std_ulogic;
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signal mult_out : std_logic_vector(127 downto 0);
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component multiply_add_64x64 port(
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clk : in std_logic;
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a : in std_logic_vector(63 downto 0);
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b : in std_logic_vector(63 downto 0);
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c : in std_logic_vector(127 downto 0);
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o : out std_logic_vector(127 downto 0)
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);
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end component;
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begin
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multiply_0: process(clk)
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begin
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if rising_edge(clk) then
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m <= m_in;
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r <= rin;
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overflow <= ovf_in;
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end if;
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end process;
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multiplier : multiply_add_64x64
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port map (
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clk => clk,
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a => m.data1,
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b => m.data2,
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c => m.addend,
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o => mult_out
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);
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multiply_1: process(all)
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variable v : reg_type;
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variable d : std_ulogic_vector(127 downto 0);
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variable d2 : std_ulogic_vector(63 downto 0);
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variable ov : std_ulogic;
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begin
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v := r;
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v.multiply_pipeline(0).valid := m.valid;
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v.multiply_pipeline(0).is_32bit := m.is_32bit;
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v.multiply_pipeline(0).not_res := m.not_result;
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loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
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v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
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end loop;
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if v.multiply_pipeline(PIPELINE_DEPTH-1).not_res = '1' then
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d := not mult_out;
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else
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d := mult_out;
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end if;
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ov := '0';
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if v.multiply_pipeline(PIPELINE_DEPTH-1).is_32bit = '1' then
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ov := (or d(63 downto 31)) and not (and d(63 downto 31));
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else
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ov := (or d(127 downto 63)) and not (and d(127 downto 63));
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end if;
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ovf_in <= ov;
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m_out.result <= d;
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m_out.overflow <= overflow;
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m_out.valid <= v.multiply_pipeline(PIPELINE_DEPTH-1).valid;
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rin <= v;
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end process;
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end architecture behaviour;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity short_multiply is
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port (
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clk : in std_ulogic;
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a_in : in std_ulogic_vector(15 downto 0);
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b_in : in std_ulogic_vector(15 downto 0);
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m_out : out std_ulogic_vector(31 downto 0)
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);
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end entity short_multiply;
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architecture behaviour of short_multiply is
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begin
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m_out <= std_ulogic_vector(signed(a_in) * signed(b_in));
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end architecture behaviour;
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@ -0,0 +1,103 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity register_file is
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generic (
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SIM : boolean := false;
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HAS_FPU : boolean := true;
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LOG_LENGTH : natural := 0
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);
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port(
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clk : in std_logic;
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d_in : in Decode2ToRegisterFileType;
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d_out : out RegisterFileToDecode2Type;
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w_in : in WritebackToRegisterFileType;
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dbg_gpr_req : in std_ulogic;
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dbg_gpr_ack : out std_ulogic;
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dbg_gpr_addr : in gspr_index_t;
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dbg_gpr_data : out std_ulogic_vector(63 downto 0);
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sim_dump : in std_ulogic;
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sim_dump_done : out std_ulogic;
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log_out : out std_ulogic_vector(71 downto 0)
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);
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end entity register_file;
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architecture behaviour of register_file is
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component Microwatt_FP_DFFRFile port (
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CLK : in std_ulogic;
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R1 : in std_ulogic_vector(6 downto 0);
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R2 : in std_ulogic_vector(6 downto 0);
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R3 : in std_ulogic_vector(6 downto 0);
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D1 : out std_ulogic_vector(63 downto 0);
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D2 : out std_ulogic_vector(63 downto 0);
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D3 : out std_ulogic_vector(63 downto 0);
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WE : in std_ulogic;
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RW : in std_ulogic_vector(6 downto 0);
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DW : in std_ulogic_vector(63 downto 0)
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);
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end component;
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signal d1: std_ulogic_vector(63 downto 0);
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signal d2: std_ulogic_vector(63 downto 0);
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signal d3: std_ulogic_vector(63 downto 0);
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begin
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register_file_0 : Microwatt_FP_DFFRFile
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port map (
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CLK => clk,
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R1 => d_in.read1_reg,
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R2 => d_in.read2_reg,
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R3 => d_in.read3_reg,
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D1 => d1,
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D2 => d2,
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D3 => d3,
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WE => w_in.write_enable,
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RW => w_in.write_reg,
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DW => w_in.write_data
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);
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x_state_check: process(clk)
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begin
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if rising_edge(clk) then
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if w_in.write_enable = '1' then
|
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assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
|
||||
end if;
|
||||
end if;
|
||||
end process x_state_check;
|
||||
|
||||
-- Forward any written data
|
||||
register_read_0: process(all)
|
||||
begin
|
||||
d_out.read1_data <= d1;
|
||||
d_out.read2_data <= d2;
|
||||
d_out.read3_data <= d3;
|
||||
|
||||
if w_in.write_enable = '1' then
|
||||
if d_in.read1_reg = w_in.write_reg then
|
||||
d_out.read1_data <= w_in.write_data;
|
||||
end if;
|
||||
if d_in.read2_reg = w_in.write_reg then
|
||||
d_out.read2_data <= w_in.write_data;
|
||||
end if;
|
||||
if d_in.read3_reg = w_in.write_reg then
|
||||
d_out.read3_data <= w_in.write_data;
|
||||
end if;
|
||||
end if;
|
||||
end process register_read_0;
|
||||
|
||||
end architecture behaviour;
|
||||
Loading…
Reference in New Issue