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Mono Color

• e99d5c4adf
  Merge c2d44b25ae into dc9d351833 #430 Yunseong Kim 2025-04-29 12:12:12 +0800
• dc9d351833
  Merge pull request #444 from paulusmack/master master Paul Mackerras 2025-04-16 18:06:14 +1000
• de2e8f81ee decode: Execute cpabort as a no-op #444 Paul Mackerras 2025-04-16 11:49:15 +1000
• b65dde1a95 arty a7: Display run status of two CPUs on LEDs 6 and 7 Paul Mackerras 2025-01-10 13:22:56 +1100
• 51dd7f578f countbits: Move more popcount calculation before the clock edge Paul Mackerras 2025-04-15 09:59:44 +1000
• b14dd43ce6
  Merge pull request #443 from paulusmack/compliance Paul Mackerras 2025-04-14 14:49:52 +1000
• 361a01259c
  Merge pull request #441 from paulusmack/dcache Paul Mackerras 2025-04-14 14:48:47 +1000
• 7e544c1fb8
  Merge pull request #442 from paulusmack/fpu Paul Mackerras 2025-04-11 14:56:17 +1000
• 8f7326a824 core: Implement various SPRs which read zero and ignore writes #443 Paul Mackerras 2025-04-10 16:22:09 +1000
• 1da8476cf9 dcache: Simplify forwarding of load data while reloading a cache line #441 Paul Mackerras 2025-04-08 20:15:06 +1000
• c938246cc8 dcache: Simplify addressing of the dcache TLB Paul Mackerras 2025-04-05 09:39:48 +1100
• 1b6ee631bc core: Implement LPCR register Paul Mackerras 2025-03-28 17:12:04 +1100
• 63fff5e05c core: Remove HFSCR and Hypervisor Facility Unavailable interrupt logic Paul Mackerras 2025-03-27 17:12:11 +1100
• 5168242cd5 dcache: Rework forwarding data paths Paul Mackerras 2025-03-13 14:55:07 +1100
• 4278387b21 dcache: Simplify reservation logic Paul Mackerras 2025-03-12 15:16:34 +1100
• 26507450b7 dcache: Remove reset on read port of cache tag RAM Paul Mackerras 2025-03-12 10:58:43 +1100
• 9645ab6e1f dcache: Rework forwarding and same-page logic Paul Mackerras 2025-03-11 20:25:10 +1100
• 2529bb66ad dcache: Implement dcbz to non-cacheable memory properly Paul Mackerras 2025-03-10 15:00:55 +1100
• ec323897e3 dcache: Use expanded per-way TLB and cache tag hit information Paul Mackerras 2025-02-05 22:11:21 +1100
• 3268ef717c FPU: Make opsel_a a function of just the state #442 Paul Mackerras 2025-03-21 21:41:39 +1100
• 73505b1626 FPU: Provide a separate path for transferring A/B/C to R Paul Mackerras 2025-03-18 20:53:27 +1100
• b63773f6e9 FPU: Move computation of main adder inputs out of the state machine Paul Mackerras 2024-03-19 15:36:50 +1100
• b4aae8511d FPU: Move special case handling to a separate process Paul Mackerras 2024-03-14 20:41:59 +1100
• b1bd2aa865 FPU: Make set_r independent of multiply_to_f.valid Paul Mackerras 2024-03-13 14:05:52 +1100
• fcfdbc449c FPU: Move condition register calculations to an explicit data path Paul Mackerras 2024-03-13 09:45:46 +1100
• bbc485f336 FPU: Rework inputs to the main adder Paul Mackerras 2024-03-11 12:31:58 +1100
• 0e7c11a0e4 FPU: Move result_class logic outside of state machine Paul Mackerras 2024-03-08 14:44:47 +1100
• 5f0b2d433d FPU: Simplify calculation of result_class Paul Mackerras 2024-03-07 21:01:53 +1100
• 70819c4c39 FPU: Do renormalization from DO_ZERO_DEN state Paul Mackerras 2024-03-07 13:53:01 +1100
• 8648ddb64f FPU: Eliminate EXC_RESULT state Paul Mackerras 2024-03-06 13:45:58 +1100
• 850b87c83f FPU: Get rid of r.madd_cmp and r.exp_cmp Paul Mackerras 2024-03-05 20:50:45 +1100
• ba2add029a FPU: Remove need to set opsel_a one cycle ahead Paul Mackerras 2024-03-05 16:46:08 +1100
• 2731384a4b FPU: Reduce misc_sel to 3 bits Paul Mackerras 2024-03-01 22:12:46 +1100
• cf866ce910 FPU: Simplify logic for setting r.x Paul Mackerras 2024-02-29 21:39:36 +1100
• 4e5f856c55 FPU: Factor out some of the common elements of the DO_* states Paul Mackerras 2024-02-13 17:17:03 +1100
• 2422585e14 FPU: Reduce use of r.insn inside the state machine Paul Mackerras 2024-02-12 22:16:13 +1100
• 7812a55b6c FPU: Reorganize NaN and infinity handling and improve arch compliance Paul Mackerras 2024-02-05 21:57:59 +1100
• 9ac71cfbf2 tests/fpu: Add more floating multiply-add tests Paul Mackerras 2024-04-05 09:34:14 +1100
• a3613d863b FPU: Simplify sign calculation in FP multiply-add instructions Paul Mackerras 2024-02-10 16:53:21 +1100
• 707dd619a0 FPU: Move NaN/infinity and zero/denorm handling out to separate states Paul Mackerras 2024-02-05 14:25:10 +1100
• 27b3e42353 FPU: Move result_sign computations from state machine to a data path Paul Mackerras 2024-01-19 09:37:16 +1100
• 71b7df679b FPU: Calculate quieten_nan in first cycle Paul Mackerras 2024-01-18 22:06:13 +1100
• 955fa561fb FPU: Move most result_sign computation out of state machine Paul Mackerras 2024-01-17 21:05:30 +1100
• c5abe3c0a9
  Merge pull request #440 from paulusmack/compliance Paul Mackerras 2025-02-24 08:59:22 +1100
• 413907e4bc soc: Move timebase back into the core and enable writing to it #440 Paul Mackerras 2025-02-03 19:37:09 +1100
• f705fc5e19 core: Implement reserved/no-op SPR numbers Paul Mackerras 2025-01-30 22:41:59 +1100
• c49c32b5fe core: Implement DEXCR and HDEXCR registers Paul Mackerras 2025-01-30 21:16:05 +1100
• bae24b12e7
  Merge pull request #439 from paulusmack/master Paul Mackerras 2025-02-18 15:05:02 +1100
• 3e0888ae35 litesdcard: Update generated code #439 Paul Mackerras 2025-02-17 09:52:07 +1100
• 3fb0a9ed26 litedram: Update generated code Paul Mackerras 2025-02-15 19:55:15 +1100
• ab7105f438 liteeth: Update generated code Paul Mackerras 2025-02-15 16:33:23 +1100
• 370dbef593
  Merge pull request #438 from paulusmack/master Paul Mackerras 2025-02-14 07:53:55 +1100
• f0c331b8b8 Arty A7: Reduce warnings from Vivado #438 Paul Mackerras 2025-02-04 21:48:57 +1100
• 1395bde3cc core: Store hash key SPRs in the SPR RAM Paul Mackerras 2025-01-29 20:35:22 +1100
• 2c7d1e5d9c decode: Split input B selection into two fields Paul Mackerras 2025-01-29 11:15:01 +1100
• e4e1a033bd
  Merge pull request #437 from paulusmack/compliance Paul Mackerras 2025-01-28 17:45:46 +1100
• 8f537c13bc tests: Add a test for the hash instructions hash{st,cmp}[p] #437 Paul Mackerras 2025-01-25 09:14:02 +1100
• 3bcc31fdda core: Implement hashstp and hashchkp instructions and HASHPKEYR register Paul Mackerras 2025-01-24 14:16:57 +1100
• 00a3db8457 decode1: Indicate instruction privilege in main decode table Paul Mackerras 2025-01-23 18:59:46 +1100
• 0a11e8455f core: Implement hashst and hashchk instructions Paul Mackerras 2025-01-23 15:02:36 +1100
• e9b57ca5bf
  Merge pull request #436 from paulusmack/smp Paul Mackerras 2025-01-24 17:37:27 +1100
• 0a2d3b6f58 loadstore1: Split DAWR check across a clock edge #436 Paul Mackerras 2025-01-17 21:47:26 +1100
• d8423568b6 core: Evaluate rotator control signals in decode2 Paul Mackerras 2025-01-10 16:53:27 +1100
• d1c7b654bb wishbone_arbiter: Remove early_sel optimization when > 4 masters Paul Mackerras 2025-01-05 20:52:06 +1100
• bf55efec6d Arty A7: Add an option to select the number of CPU cores Paul Mackerras 2025-01-10 11:21:43 +1100
• 9bd6b3d175 xics: Implement destination server field in interrupt source registers Paul Mackerras 2025-01-11 17:04:27 +1100
• 3924ed0f49 xics: Implement a presentation controller per CPU core Paul Mackerras 2025-01-09 09:47:29 +1100
• 49fcbaa5b2 soc: Implement a global timebase across all cores Paul Mackerras 2025-01-09 19:27:58 +1100
• e0c5af9bb1 mw_debug: Add -c flag to select which CPU core to address Paul Mackerras 2025-01-04 17:16:14 +1100
• 9a06b0c182 soc: Implement multiple CPU cores Paul Mackerras 2025-01-04 16:24:41 +1100
• 0020c13226
  Merge pull request #435 from paulusmack/compliance Paul Mackerras 2025-01-18 08:28:39 +1100
• 23ff954059 core: Change bperm to a simpler and slower implementation Paul Mackerras 2025-01-07 14:00:01 +1100
• f6a839a86b control: Use a 1-hot encoding for bypass enables Paul Mackerras 2025-01-05 21:59:45 +1100
• 52d8f28d03 execute1: Improve timing for execute bypass tag Paul Mackerras 2025-01-04 16:27:10 +1100
• 80bc9d5098 tests/trace: Add a few tests of DAWR (data watchpoint) functionality #435 Paul Mackerras 2025-01-16 22:37:58 +1100
• 5ddd8884fa core: Implement two data watchpoints Paul Mackerras 2025-01-15 15:18:23 +1100
• 09de0738de tests/trace: Add checks for SIAR and SDAR being set correctly Paul Mackerras 2025-01-16 19:44:28 +1100
• ff00dc1505 PMU: Fix setting of SIAR and SDAR on trace interrupt Paul Mackerras 2025-01-15 21:47:51 +1100
• 23b183fb16 tests/reservation: Check that SRR0 is set correctly on alignment interrupt Paul Mackerras 2025-01-16 19:06:00 +1100
• 622f8c81cc loadstore1: Fix setting of SRR0 on alignment interrupt Paul Mackerras 2025-01-16 18:57:33 +1100
• f64ab6569d tests/trace: Add a couple of tests of CIABR function Paul Mackerras 2025-01-13 22:00:00 +1100
• 5a28f76b6f execute1: Implement CIABR Paul Mackerras 2025-01-13 19:42:57 +1100
• f4ec0c2043
  Merge pull request #434 from paulusmack/compliance Paul Mackerras 2025-01-15 21:55:47 +1100
• 7437f699ca core: Implement the PIR SPR #434 Paul Mackerras 2025-01-08 18:16:26 +1100
• d531e8aa10 dcache: Improve timing Paul Mackerras 2025-01-02 22:11:06 +1100
• 5121e0f392 core: Implement sync instructions Paul Mackerras 2021-05-09 19:58:59 +1000
• 00efcc2c3b dcache: Make aligned quadword loads and stores actually be atomic Paul Mackerras 2025-01-02 13:40:21 +1100
• c2dcf4b334 dcache: Generate a DSI on larx/stcx to non-cacheable memory Paul Mackerras 2025-01-02 13:22:49 +1100
• 0fbeaa2a01 dcache: Use discrete req_op_* signals instead of an encoded req_op Paul Mackerras 2024-12-30 13:01:08 +1100
• ba4614c5f4 dcache: Implement data cache touch and flush instructions Paul Mackerras 2021-05-11 20:26:09 +1000
• b181d28df2 dcache: Cancel reservation on snooped store Paul Mackerras 2021-05-17 13:52:19 +1000
• 140b930ad3 tests: Add tests for lq/stq, plq/pstq and lqarx/stqcx. Paul Mackerras 2020-09-14 18:21:27 +1000
• 722f239c02 Reimplement quadword loads and stores Paul Mackerras 2024-12-26 22:09:51 +1100
• d358981d43 Generate doubled instructions in decode1 rather than decode2 Paul Mackerras 2024-12-23 22:07:07 +1100
• fa9df33f7e Implement cfuged, pdepd and pextd Paul Mackerras 2023-09-28 21:58:15 +1000
• d7d7a3afd4 Implement VRSAVE SPR Paul Mackerras 2023-09-22 12:30:13 +1000
• d112a7ad94 Implement scv and rfscv Paul Mackerras 2023-09-22 08:56:31 +1000
• a88fa9c459 Implement DSCR Paul Mackerras 2023-09-20 20:38:22 +1000
• 205c0e2c78 Implement the wait instruction Paul Mackerras 2023-09-18 22:15:07 +1000
• 7bc7f335f1 Implement CTRL register Paul Mackerras 2023-09-16 13:53:34 +1000