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7c86585654

Merge 89ce8a8b17 into f59485f157 #385 Anton Blanchard 2023-09-22 11:58:24 +0000
0453978568

Merge 73a2fcbc7f into f59485f157 #422 Paul Mackerras 2023-09-19 23:42:59 +0000
73a2fcbc7f icache_tb: Update for recent icache changes #422 Paul Mackerras 2023-09-20 09:41:16 +1000
73b6004ac6 icache: Use next real address to index icache Paul Mackerras 2023-08-15 11:30:53 +1000
f9e5622327 Move iTLB from icache to fetch1 Paul Mackerras 2023-08-15 20:50:17 +1000
27c50bc311 Makefile: Remove overriding of ICACHE_NUM_LINES on ECP5 platforms Paul Mackerras 2023-08-05 14:31:43 +1000
963c225955 icache: Read icache tag RAM synchronously Paul Mackerras 2023-08-01 17:47:22 +1000
723008b8c2 icache: Read iTLB using early next NIA from fetch1 Paul Mackerras 2023-07-31 10:00:05 +1000
f34a54d295 fetch1: Streamline next NIA generation further Paul Mackerras 2023-07-29 19:54:44 +1000
e92d49375f fetch1: Reorganize fetch1 to provide an asynchronous early next NIA to icache Paul Mackerras 2023-07-29 10:22:56 +1000
2dceb28830 Improve timing of redirect_nia going from decode1 to fetch1 Paul Mackerras 2023-07-27 14:22:57 +1000
1c4b5def36 Improve timing of redirect_nia going from writeback to fetch1 Paul Mackerras 2023-07-26 16:33:27 +1000
06ff486567 icache: Restore primary opcode to instruction word Paul Mackerras 2023-09-07 22:22:31 +1000
f59485f157

Merge pull request #420 from paulusmack/master master Paul Mackerras 2023-09-19 16:22:07 +1000
8dc24416aa

Merge pull request #421 from paulusmack/fixes Paul Mackerras 2023-09-19 16:21:34 +1000
b1b1367cd5 icache: Fix instruction sent to log #421 Paul Mackerras 2023-09-16 22:12:02 +1000
af62b9f1eb scripts/fmt_log: Update for recent changes Paul Mackerras 2023-09-16 20:44:53 +1000
f668597f67

Merge pull request #419 from paulusmack/prefix Paul Mackerras 2023-09-15 15:01:46 +1000
4bef477e29 core_debug: Add support for detecting writes to a memory address #420 Paul Mackerras 2023-08-28 12:22:31 +1000
a2890745d5 Makefile: Remove long micropython test from check_light Paul Mackerras 2023-07-26 16:31:05 +1000
9c3d14dd5a dcache: Make reading of DTLB independent of d_in.valid Paul Mackerras 2023-07-26 15:49:12 +1000
8c5dabd67f dcache: Make r1.acks_pending independent of r1.state Paul Mackerras 2022-01-20 08:36:10 +1100
84008fbf41 arty: Change shield I/O pin bus into individual signals Paul Mackerras 2021-04-22 15:37:09 +1000
b7ccffe2a3 Merge pull request #404 from CodeConstruct:dev/gpio-interrupt Paul Mackerras 2023-09-15 09:29:51 +1000
b50170cd1d Implement byte reversal instructions #419 Paul Mackerras 2023-09-09 22:14:03 +1000
fd8c0000c0 Implement set[n]bc[r] instructions Paul Mackerras 2023-07-27 14:58:09 +1000
7c5a2bcaf4 tests: Add a test for prefixed instructions Paul Mackerras 2023-07-05 19:25:28 +1000
c4492c843a Implement interrupts for prefixed instructions Paul Mackerras 2023-07-03 18:19:38 +1000
39ca675ce3 Decode prefixed instructions Paul Mackerras 2023-07-03 12:32:43 +1000
7af0e001ad Move insn_codes for mcrfs, mtfsb0/1 and mtfsfi Paul Mackerras 2023-07-03 21:09:33 +1000
4416ebe92e fetch1: Change the way predictions from the BTC are sent downstream Paul Mackerras 2022-08-20 18:06:06 +1000
28f68c7a7b

Merge 9303ae2c89 into 83dcfeabf8 #354 Jacob Lifshay 2023-03-20 15:34:12 -0700
0f869769fc

Merge 9cb4948690 into 83dcfeabf8 #347 Matt Johnston 2023-02-28 09:24:49 +0100
83dcfeabf8

Merge pull request #417 from kraigher/master Anton Blanchard 2023-02-20 17:18:35 +1100
341a507486 Add vhdl_ls.toml dump to run.py #417 Olof Kraigher 2023-02-12 18:50:10 +0100
da5d3ded3c

Merge pull request #409 from CodeConstruct/dev/soc-reset Michael Neuling 2022-12-05 17:33:11 +1100
9366d23f1f ASIC: No need to add includes any more caravel-mpw7-20221125 Anton Blanchard 2022-11-25 06:48:20 +1100
56f1c41e9c arty: Add software reset from syscon #409 Matt Johnston 2022-10-27 11:50:12 +0800
1f5a2e8aaa soc: Expose sw_soc_reset for syscon reset Matt Johnston 2022-09-29 12:20:40 +0800
89d8cf0788 Regenerate litedram with updated sdram init Matt Johnston 2022-10-27 13:02:05 +0800
1874cad5b7 litedram: only run sdram init at first boot Matt Johnston 2022-10-27 11:20:27 +0800
4bd45af739 Move alt_reset to syscon Matt Johnston 2022-10-27 11:23:30 +0800
dfecda3a5f bin2hex: handle any file length, not just 8 or 4 Matt Johnston 2022-10-27 14:16:49 +0800
7d928200b8

Merge pull request #415 from ozbenh/uart16550-core Michael Neuling 2022-10-25 10:52:34 +1100
964b97e85c

Merge pull request #414 from ozbenh/misc Michael Neuling 2022-10-25 09:02:08 +1100
d299ea925e Bundle the uart16550 core file #415 Benjamin Herrenschmidt 2022-10-24 15:25:39 +1100
6068b635ae Fix plru_tb to use the new plrufn and take out the old plru.vhdl #414 Benjamin Herrenschmidt 2022-10-23 15:24:11 +1100
432d9f3150

Merge pull request #413 from ozbenh/fix-io-bridge-qw-store Michael Neuling 2022-10-24 15:02:33 +1100
4e32dcff80 Clean vunit_out on make clean Benjamin Herrenschmidt 2022-10-23 15:45:48 +1100
41328306f3 Add shebang to run.py Benjamin Herrenschmidt 2022-10-23 15:24:16 +1100
3f788e87dc soc: Fix issues with 64-bit stores to IO bridge #413 Benjamin Herrenschmidt 2022-10-23 13:42:56 +1100
52da535b16 gpio: Add interrupts and trigger registers #404 Matt Johnston 2022-09-08 13:26:00 +0800
413f2dc5d6

Merge pull request #411 from ozbenh/dcache-plru-update-fix Paul Mackerras 2022-10-07 18:27:13 +1100
76f61ef823 dcache: Update PLRU on misses as well as hits #411 Benjamin Herrenschmidt 2022-10-02 17:43:58 +1100
3edbbf5f18 Fix dcache_tb (and add dump of victim way to dcache) #410 Benjamin Herrenschmidt 2022-09-30 12:04:26 +1000
f5d1deb204 Add more interrupt numbers to microwatt_soc.h Matt Johnston 2022-09-08 14:38:39 +0800
fe62bc50e8 arty: Add switches and buttons as gpio 10-17 Matt Johnston 2022-08-18 14:54:12 +0800
9d53882c48 arty: Add other RGB LEDs, attach to gpio 0-8 Matt Johnston 2022-08-18 14:53:32 +0800
7619c3d089 arty: Add switches and buttons to xdc file Matt Johnston 2022-08-18 14:14:20 +0800
84a0fba25d

Merge pull request #408 from paulusmack/plru-improvement Michael Neuling 2022-09-29 11:49:08 +1000
5766dbab37

Merge pull request #406 from shingarov/spi-kintex Michael Neuling 2022-09-26 16:49:11 +1000
d9c55defdb

Merge pull request #407 from shingarov/openocd-012 Michael Neuling 2022-09-26 16:47:15 +1000
ed5807381e Recognize version string "0.12" in recent OpenOCD master #407 Boris Shingarov 2022-09-24 07:08:42 -0400
6c3f7d75d5 Add support for flashing the s25fl256s onboard Genesys2 #406 Boris Shingarov 2022-09-23 16:10:04 -0400
b8f9c833f8 litedram: Split L2 PLRU into storage and logic #408 Paul Mackerras 2022-09-19 18:05:30 +1000
64997811a8 Fix power plumbing in execute unit caravel-mpw7-20220822 Anton Blanchard 2022-09-12 22:05:47 +1000
a1f5867919 dcache: Split PLRU into storage and logic Paul Mackerras 2022-09-07 20:21:42 +1000
86212dc879 icache: Split PLRU into storage and logic Paul Mackerras 2022-09-07 20:18:18 +1000
d3fb2639dd

Merge pull request #403 from mikey/litedram-warnings Anton Blanchard 2022-09-07 18:00:11 +1000
cd2e174113 dcache: Fix compilation with NUM_WAYS and/or TLB_NUM_WAYS = 1 Paul Mackerras 2022-09-07 16:02:06 +1000
82c8b2eae0 icache: Fix compilation with NUM_WAYS = 1 Paul Mackerras 2022-09-07 15:32:46 +1000
24d04ed8f9 Fix litedram wrapper build warnings and metavalues #403 Michael Neuling 2022-09-05 14:57:49 +1000
047f739b58

Merge pull request #402 from ozbenh/misc Michael Neuling 2022-09-05 14:51:29 +1000
39c2abae51 Fix build of core_dram_tb and dram_tb and fix tracing #402 Benjamin Herrenschmidt 2022-09-05 00:21:47 +1000
e31a4f7a9a Ignore vunit_out in git Benjamin Herrenschmidt 2022-09-05 00:22:19 +1000
cb11ad8e64

Merge pull request #401 from shenki/dcscm Michael Neuling 2022-09-01 11:08:59 +1000
ad858995aa openocd: Add Artix DC-SCM cable type #401 Joel Stanley 2022-08-16 15:14:44 +1000
13aa52dfa7 antmicro-artix-dc-scm: Add liteeth Joel Stanley 2022-08-25 19:51:07 +1000
e2ae325d5c antmicro-artix-dc-scm: Add Ethernet pins Joel Stanley 2022-08-25 19:50:47 +1000
87a875b940 antmicro-artix-dc-scm: Enable SPI flash Joel Stanley 2022-08-25 18:27:19 +1000
7065434652 antmicro-artix-dc-scm: Formatting to match top-arty Joel Stanley 2022-08-25 18:26:53 +1000
621da8106f antmicro-artix-dc-scm: Add SPI flash pins Joel Stanley 2022-08-25 18:26:02 +1000
fdc44a71a0 antmicro-artix-dc-scm: Update DRAM properties Joel Stanley 2022-08-25 19:51:55 +1000
9b184ff569 antmicro-artix-dc-scm: Add DRAM support Paul Mackerras 2021-10-27 14:58:34 +1100
d92af779eb Add Antmicro Artix DC SCM hello world support Michael Neuling 2021-10-21 10:50:46 +1100
26095986f3

Merge pull request #400 from mikey/githash Anton Blanchard 2022-08-30 11:49:40 +1000
cf6d57b803

Merge pull request #399 from ozbenh/misc Michael Neuling 2022-08-29 15:20:24 +1000
bd5e4bafba hello_world: Debug print the gitinfo syscon register #400 Dan Horák 2020-09-01 22:43:50 +0200
1ddbacb67f syscon: Implement a register for storing git hash info Dan Horák 2020-08-28 14:24:07 +0200
fa4baa2800 Fix PLRU #399 Benjamin Herrenschmidt 2022-08-25 13:14:20 +1000
2663326f2c ASIC: Register file updates Anton Blanchard 2022-08-22 17:56:25 +1000
b48bf83772 ASIC: Update PVR for MPW7 Anton Blanchard 2022-08-22 14:44:29 +1000
68495c9b4b ASIC: Switch to ghdl --synth Anton Blanchard 2022-08-22 14:40:52 +1000
82c8f48f77 ASIC: Fix multiplier power Anton Blanchard 2022-06-07 08:50:35 +1000
795d57249f ASIC: Reduce multiplier from 4 to 2 cycles Anton Blanchard 2022-05-30 14:34:21 +1000
4fc321cd41 Move register stage back after the RAM Anton Blanchard 2022-03-23 17:43:09 +1100
2b47de30c4 Add a script to post process the Microwatt verilog for caravel Anton Blanchard 2020-12-17 15:14:54 +1100
7e4f627ea4 Add simplebus verilog Anton Blanchard 2022-03-21 06:35:38 +1100
d2cc31cde4 Add simplebus Anton Blanchard 2022-03-15 15:19:13 +1100
6745d9dd5f Hook up JTAG to ASIC top level Anton Blanchard 2021-10-26 15:15:02 +1100