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Mono Color

• b6964f0c62
  Merge 59f1b7f698 into 0b3df8ab00 #451 Sanket Sharma 2025-12-16 23:57:51 +1030
• 845c178bd0
  Merge 09b340e845 into 0b3df8ab00 #457 Paul Mackerras 2025-12-15 13:59:49 +1100
• 09b340e845 FPU: Update committed FPSCR value correctly #457 Paul Mackerras 2025-12-04 08:48:27 +1100
• 1ad8848655 FPU: Improve zero result detection and simplify final states Paul Mackerras 2025-12-14 08:42:23 +1100
• f8a11420ca FPU: Check for rounding overflow in 32-bit convert-to-integer operations Paul Mackerras 2025-12-13 11:31:31 +1100
• 6fe4b549f5 FPU: Improve accuracy in multiply-add almost-cancellation cases Paul Mackerras 2025-12-12 18:51:13 +1100
• 80c81b58ef FPU: Generate correct result sign when B is denormal Paul Mackerras 2025-12-12 16:44:43 +1100
• f631dcd700 FPU: Set FPRF correctly on multiply result that underflows Paul Mackerras 2025-12-12 12:44:13 +1100
• b122577a4e FPU: Be more careful about preserving low-order bits in multiply-add instrs Paul Mackerras 2025-12-12 10:12:10 +1100
• 59992eab90 FPU: Avoid doing overflow processing twice in OE=1 case Paul Mackerras 2025-12-11 13:15:00 +1100
• 9f27f60b26 FPU: Clear FPSCR[FR,FI] on overflow in convert-to-integer instructions Paul Mackerras 2025-12-11 09:19:12 +1100
• 37edba4da7 FPU: Normalize B operand for multiply-add instructions Paul Mackerras 2025-12-11 09:01:41 +1100
• d33f31509b FPU: Clear S in ADD_SHIFT state Paul Mackerras 2025-12-10 21:02:06 +1100
• b8f7cbd894 FPU: Record bits shifted out of addend in fmadd-family instructions Paul Mackerras 2025-12-10 20:14:35 +1100
• 009ee1c9c5 FPU: Renormalize frsp operand if denormalized Paul Mackerras 2025-12-10 11:47:32 +1100
• baf8f5f8c6 FPU: Force reserved FPSCR bit 11 to zero Paul Mackerras 2025-12-10 11:02:23 +1100
• a18c462b27 FPU: Ignore stale P contents in short-circuit multiply-add Paul Mackerras 2025-12-10 09:34:20 +1100
• 41988e3b5f FPU: Fix comparison of remainder in square root code Paul Mackerras 2025-12-10 08:37:02 +1100
• f3b9566ae2 FPU: Round to single precision for fcfid[u]s Paul Mackerras 2025-12-09 19:38:59 +1100
• e5651e2eab FPU: Avoid adding bias twice in UE=1 underflow case Paul Mackerras 2025-12-09 16:12:05 +1100
• a0755935f4 FPU: Normalize B for fmadd family instructions Paul Mackerras 2025-12-09 11:35:12 +1100
• 32919435a3 FPU: Allow mtfsb* to set FPSCR[FX] implicitly Paul Mackerras 2025-12-09 11:20:23 +1100
• e471581222 FPU: Do result processing on denorm short-circuit results when FPSCR[UE] is set Paul Mackerras 2025-12-08 19:12:03 +1100
• 0478fe41dd FPU: Reset FPSCR[FR,FI] at beginning of fcfid* Paul Mackerras 2025-12-08 15:03:43 +1100
• f252dba43d FPU: Only apply zero subtraction result sign rule when result is exactly zero Paul Mackerras 2025-12-08 14:15:24 +1100
• 8a204f1058 FPU: Set FPSCR exception summary based on individual invalid exception bits Paul Mackerras 2025-12-08 08:07:28 +1100
• fb71f62b83 FPU: Round finite special-case results to single precision if required Paul Mackerras 2025-12-06 20:53:38 +1100
• de71a6119c FPU: Make FPSCR bit 11 always read as 0 Paul Mackerras 2025-12-06 18:23:27 +1100
• ca792f3b13 FPU: Make convert-to-integer-word instructions behave like P9 Paul Mackerras 2025-12-06 18:09:20 +1100
• 82825a11ba FPU: Set result sign correctly for denorm +/- 0 case Paul Mackerras 2025-12-06 17:55:11 +1100
• 37b1afc7f7 FPU: Make fri* instructions set FPSCR[FR,FI] to zero Paul Mackerras 2025-12-06 17:28:31 +1100
• dcd85164c6 FPU: Make fsel not alter FPSCR Paul Mackerras 2025-12-06 17:09:46 +1100
• 066e38b8ea FPU: Do proper over/underflow handling for single-precision [fm]add Paul Mackerras 2025-12-06 16:26:52 +1100
• d540171f60 FPU: Ignore Rc bit for mffs* variants other than plain mffs Paul Mackerras 2025-12-06 14:08:48 +1100
• 0e11f80f2f FPU: Set FPSCR[FPRF] to zero for convert to integer operations Paul Mackerras 2025-12-06 13:32:56 +1100
• 2f29daab2d FPU: Fix setting of r.x for single-precision operations Paul Mackerras 2025-12-06 11:15:11 +1100
• 577bbb8f5d tests/fpu: Add test case for denorm input in frsp test Paul Mackerras 2025-11-19 13:36:04 +0000
• ab3783b61b FPU: Fix setting of r.x Paul Mackerras 2025-11-19 13:32:14 +0000
• 7b1febcbd3 tests/fpu: Check setting of FR and FI in FPSCR by frsp instruction Paul Mackerras 2025-11-18 22:49:45 +0000
• e60840eabc FPU: Make sure FR and FI in FPSCR get reset on special-case arith instructions Paul Mackerras 2025-11-18 22:42:37 +0000
• 0b3df8ab00
  bitsort: Fix bperm instruction (#456) master Paul Mackerras 2025-12-15 08:27:42 +1100
• 213c2f6f75 bitsort: Fix bperm instruction #456 Paul Mackerras 2025-11-18 07:27:35 +0000
• e658042e93
  Merge c2d44b25ae into da695e7927 #430 Yunseong Kim 2025-10-12 17:20:22 +0300
• da695e7927
  execute1: Fix bug where LPCR[HEIC] disabled interrupts in problem state (#453) Paul Mackerras 2025-10-10 10:31:43 +1100
• 5189f18d66 execute1: Fix bug where LPCR[HEIC] disabled interrupts in problem state #453 Paul Mackerras 2025-10-09 09:18:38 +1100
• fabe9a4feb
  Merge pull request #452 from paulusmack/master Paul Mackerras 2025-10-04 08:10:47 +1000
• 79e69d2a23 execute2: Simplify execute2 logic to improve timing #452 Paul Mackerras 2025-09-29 19:53:43 +1000
• 9326fc7f18 tests/modes: Test that mfspr/mtspr to unimplemented SPR in user mode causes HEAI Paul Mackerras 2025-09-25 11:43:24 +1000
• 0255283159 tests/spr_read: Test that mfspr/mtspr to SPRs 0,4,5,6 generate HEAI Paul Mackerras 2025-09-24 22:10:48 +1000
• 5548a5ba26 execute1: Make mfspr/mtspr to SPRs 0,4,5,6 generate HEAI Paul Mackerras 2025-09-25 22:37:47 +1000
• 9c40ddffd2 execute1: Implement LPCR[EVIRT] bit Paul Mackerras 2025-09-25 09:01:19 +1000
• 1d758f1d74 execute1: Simplify no-op behaviour of mfspr Paul Mackerras 2025-09-17 09:47:30 +1000
• 788f7a1755 core: Improve timing on bypass control paths Paul Mackerras 2025-09-27 08:52:18 +1000
• f2166d326c tests/fpu: Add a test for result writing being suppressed Paul Mackerras 2025-09-20 15:19:33 +1000
• 34cf092bf6 control: Fix forwarding when previous result write is suppressed Paul Mackerras 2025-09-22 09:15:11 +1000
• 9f9f9046ee tests/spr_read: Add a check for no-op behaviour of mtspr and mfspr Paul Mackerras 2025-09-17 17:57:08 +1000
• 4073aa5ffd execute1: Fix setting HEIR and FSCR[IC] on interrupts Paul Mackerras 2025-09-29 16:12:40 +1000
• 6fe0b6e444 execute1: Fix no-op behaviour of reading undefined SPRs Paul Mackerras 2025-09-19 11:16:33 +1000
• 59f1b7f698 Added support for Xilinx VCU 118 board, without litedram #451 Sanket Sharma 2025-09-08 00:26:16 +0300
• 7619df6b78
  core: Implement HRMOR as a read-only zero register (#450) Paul Mackerras 2025-09-03 11:43:11 +1000
• 6e905cec70 core: Implement HRMOR as a read-only zero register #450 Paul Mackerras 2025-08-25 08:54:17 +1000
• 198ad6d199
  genesys2: Fix SPI_FLASH_OFFSET (#449) Boris Shingarov 2025-08-17 19:48:23 -0400
• a6858f716a
  genesys2: Fix DDR3 PHY cmd_latency (#448) Boris Shingarov 2025-08-17 19:46:57 -0400
• 59f4b8ea47 [genesys2] Fix SPI_FLASH_OFFSET #449 Boris Shingarov 2022-10-01 03:54:36 -0400
• 0b93f1657e [genesys2] Fix DDR3 PHY cmd_latency #448 Boris Shingarov 2025-08-16 17:51:40 -0400
• 152eef1156
  Merge pull request #446 from paulusmack/master Paul Mackerras 2025-08-13 20:33:45 +1000
• d2bf3f3580 core: Implement hypervisor doorbell interrupt and msg* instructions #446 Paul Mackerras 2025-08-08 08:55:48 +1000
• ca872faede core: Consolidate several OP_* values into a single OP_COMPUTE Paul Mackerras 2025-06-03 19:36:12 +1000
• a764fd464e
  Merge pull request #445 from paulusmack/master Paul Mackerras 2025-08-07 08:50:18 +1000
• 8f6c727309 execute1: Rework data paths for mfspr and mtspr #445 Paul Mackerras 2025-06-03 14:07:15 +1000
• fc3ff2d340 logical: Use sub_select rather than insn_type to select logical op Paul Mackerras 2025-06-02 22:10:40 +1000
• 54173a0677 decode: Move result_sel and subresult_sel into main decode table Paul Mackerras 2025-05-31 21:02:09 +1000
• 8bfce4890b predecode: Add some more comments Paul Mackerras 2025-05-31 11:21:14 +1000
• 0f8c4afc52 openocd: Update arty config for newer openocd versions Paul Mackerras 2025-05-30 10:08:04 +1000
• 0bf1dcedbd acorn-cle-215: Implement SMP and enable FPU and BTC Paul Mackerras 2025-05-30 10:05:41 +1000
• ce5a967ac2 soc: Allow for up to 1GB of DRAM in address decoding Paul Mackerras 2025-05-30 10:03:25 +1000
• 4282d37741 FPU: Faster method for testing for 1-bits at right end of R Paul Mackerras 2025-04-20 14:30:28 +1000
• 04b0c901e0 dcache: Simplify expression for read enable of cache RAM Paul Mackerras 2025-04-19 18:12:03 +1000
• 8605dcb4f1 decode2: Use register addresses from decode1 rather than recomputing them Paul Mackerras 2025-04-19 10:14:28 +1000
• e14712e45c core: Simplify operand presentation for hash instructions Paul Mackerras 2025-04-18 16:05:12 +1000
• dc9d351833
  Merge pull request #444 from paulusmack/master Paul Mackerras 2025-04-16 18:06:14 +1000
• de2e8f81ee decode: Execute cpabort as a no-op #444 Paul Mackerras 2025-04-16 11:49:15 +1000
• b65dde1a95 arty a7: Display run status of two CPUs on LEDs 6 and 7 Paul Mackerras 2025-01-10 13:22:56 +1100
• 51dd7f578f countbits: Move more popcount calculation before the clock edge Paul Mackerras 2025-04-15 09:59:44 +1000
• b14dd43ce6
  Merge pull request #443 from paulusmack/compliance Paul Mackerras 2025-04-14 14:49:52 +1000
• 361a01259c
  Merge pull request #441 from paulusmack/dcache Paul Mackerras 2025-04-14 14:48:47 +1000
• 7e544c1fb8
  Merge pull request #442 from paulusmack/fpu Paul Mackerras 2025-04-11 14:56:17 +1000
• 8f7326a824 core: Implement various SPRs which read zero and ignore writes #443 Paul Mackerras 2025-04-10 16:22:09 +1000
• 1da8476cf9 dcache: Simplify forwarding of load data while reloading a cache line #441 Paul Mackerras 2025-04-08 20:15:06 +1000
• c938246cc8 dcache: Simplify addressing of the dcache TLB Paul Mackerras 2025-04-05 09:39:48 +1100
• 1b6ee631bc core: Implement LPCR register Paul Mackerras 2025-03-28 17:12:04 +1100
• 63fff5e05c core: Remove HFSCR and Hypervisor Facility Unavailable interrupt logic Paul Mackerras 2025-03-27 17:12:11 +1100
• 5168242cd5 dcache: Rework forwarding data paths Paul Mackerras 2025-03-13 14:55:07 +1100
• 4278387b21 dcache: Simplify reservation logic Paul Mackerras 2025-03-12 15:16:34 +1100
• 26507450b7 dcache: Remove reset on read port of cache tag RAM Paul Mackerras 2025-03-12 10:58:43 +1100
• 9645ab6e1f dcache: Rework forwarding and same-page logic Paul Mackerras 2025-03-11 20:25:10 +1100
• 2529bb66ad dcache: Implement dcbz to non-cacheable memory properly Paul Mackerras 2025-03-10 15:00:55 +1100
• ec323897e3 dcache: Use expanded per-way TLB and cache tag hit information Paul Mackerras 2025-02-05 22:11:21 +1100
• 3268ef717c FPU: Make opsel_a a function of just the state #442 Paul Mackerras 2025-03-21 21:41:39 +1100
• 73505b1626 FPU: Provide a separate path for transferring A/B/C to R Paul Mackerras 2025-03-18 20:53:27 +1100