Home of https://openpowerfoundation.org and https://openpower.foundation
Updated 2 weeks ago
Curriculum material for teaching computer architecture with MIPS and POWER
Updated 9 months ago
Home of https://openpowerfoundation.org and https://openpower.foundation
Updated 5 months ago
This is the main libreBMC repo that contains an overview of the project and useful links. Start here.
Updated 11 months ago
Home of https://openpowerfoundation.org and https://openpower.foundation
Updated 9 months ago
Updated 1 year ago
Home of https://openpowerfoundation.org and https://openpower.foundation
Updated 1 year ago
This is the main libreBMC repo that contains an overview of the project and useful links. Start here.
Updated 1 year ago
A collection of scripts and meta data for managing the OPF Hub systems with IPMI via the OpenBMC.
Updated 10 months ago
A set of testing utilities for testing SMT performance on POWER9 bare metal and a set of guest VMs set to test the host.
Updated 10 months ago
High-specific-bandwidth memory design
Updated 2 months ago
A tiny Open POWER ISA softcore written in VHDL 2008
Updated 1 year ago
OpenPOWER Foundation General Information & Repository Listing
Updated 1 year ago
The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue
Updated 1 year ago
The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
Updated 1 year ago
Updated 4 months ago
The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
Updated 1 year ago
The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue
Updated 6 months ago
A tiny Open POWER ISA softcore written in VHDL 2008
Updated 6 days ago
An experimental small core based on VexRiscv, written in Scala
Updated 1 year ago