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Paul Mackerras
734e4c4a52
This adds an optional 16 bit x 16 bit signed multiplier and uses it for multiply instructions that return the low 64 bits of the product (mull[dw][o] and mulli, but not maddld) when the operands are both in the range -2^15 .. 2^15 - 1. The "short" 16-bit multiplier produces its result combinatorially, so a multiply that uses it executes in one cycle. This improves the coremark result by about 4%, since coremark does quite a lot of multiplies and they almost all have operands that fit into 16 bits. The presence of the short multiplier is controlled by a generic at the execute1, SOC, core and top levels. For now, it defaults to off for all platforms, and can be enabled using the --has_short_mult flag to fusesoc. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
4 years ago | |
|---|---|---|
| .. | ||
| LICENSE | 6 years ago | |
| acorn-cle-215.xdc | 5 years ago | |
| arty_a7.xdc | 4 years ago | |
| clk_gen_bypass.vhd | 6 years ago | |
| clk_gen_ecp5.vhd | 4 years ago | |
| clk_gen_mcmm.vhd | 4 years ago | |
| clk_gen_plle2.vhd | 4 years ago | |
| cmod_a7-35.xdc | 4 years ago | |
| firmware.hex | 6 years ago | |
| fpga-random.vhdl | 5 years ago | |
| fpga-random.xdc | 5 years ago | |
| genesys2.xdc | 4 years ago | |
| hello_world.hex | 6 years ago | |
| main_bram.vhdl | 4 years ago | |
| nexys-video.xdc | 4 years ago | |
| nexys_a7.xdc | 4 years ago | |
| pp_fifo.vhd | 6 years ago | |
| pp_soc_uart.vhd | 5 years ago | |
| pp_utilities.vhd | 6 years ago | |
| soc_reset.vhdl | 6 years ago | |
| soc_reset_tb.vhdl | 6 years ago | |
| top-acorn-cle-215.vhdl | 5 years ago | |
| top-arty.vhdl | 4 years ago | |
| top-generic.vhdl | 4 years ago | |
| top-genesys2.vhdl | 5 years ago | |
| top-nexys-video.vhdl | 4 years ago | |