microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Paul Mackerras e41cb01bca fetch1: Fix debug stop The ability to stop the core using the debug interface has been broken since commit bb4332b7e6b5 ("Remove fetch2 pipeline stage"), which removed a statement that cleared the valid bit on instructions when their stop_mark was 1. Fix this by clearing r.req coming out of fetch1 when r.stop_mark = 1. This has the effect of making i_out.valid be 0 from the icache. We also fix a bug in icache.vhdl where it was not honouring i_in.req when use_previous = 1. It turns out that the logic in fetch1.vhdl to handle stopping and restarting was not correct, with the effect that stopping the core would leave NIA pointing to the last instruction executed, not the next instruction to be executed. In fact the state machine is unnecessary and the whole thing can be simplified enormously - we need to increment NIA whenever stop_in = 0 in the previous cycle. Fixes: bb4332b7e6b5 ("Remove fetch2 pipeline stage") Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		4 years ago
.github/workflows	ci: use job.container	4 years ago
constraints	…
fpga	Add LOG_LENGTH to top-generic.vhdl	4 years ago
hello_world	Reduce hello_world footprint to fit in 8kB	4 years ago
include	…
lib	…
litedram	…
liteeth	…
media	…
micropython	…
openocd	…
rust_lib_demo	…
scripts	…
sim-unisim	…
tests	tests/misc: Add a test for correct CTR and LR updating by branches	4 years ago
uart16550	…
verilator	…
.gitignore	…
LICENSE	…
Makefile	Add verilator FPGA target	4 years ago
README.md	…
cache_ram.vhdl	…
common.vhdl	Fully initialize FPU buses when FPU is disabled	4 years ago
control.vhdl	…
core.vhdl	Fully initialize FPU buses when FPU is disabled	4 years ago
core_debug.vhdl	…
core_dram_tb.vhdl	…
core_flash_tb.vhdl	…
core_tb.vhdl	…
countzero.vhdl	…
countzero_tb.vhdl	…
cr_file.vhdl	…
cr_hazard.vhdl	…
crhelpers.vhdl	…
dcache.vhdl	…
dcache_tb.vhdl	…
decode1.vhdl	core: Implement mtmsr instruction	4 years ago
decode2.vhdl	FPU: Implement fmul[s]	4 years ago
decode_types.vhdl	FPU: Implement fmul[s]	4 years ago
divider.vhdl	…
divider_tb.vhdl	…
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	…
dram_tb.vhdl	…
execute1.vhdl	execute1: Fix forwarding of result when doing delayed LR update	4 years ago
fetch1.vhdl	fetch1: Fix debug stop	4 years ago
fpu.vhdl	FPU: Do masking after adder rather than on A input	4 years ago
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
gpr_hazard.vhdl	…
helpers.vhdl	…
icache.vhdl	fetch1: Fix debug stop	4 years ago
icache_tb.vhdl	…
icache_test.bin	…
insn_helpers.vhdl	…
loadstore1.vhdl	…
logical.vhdl	…
microwatt.core	…
mmu.vhdl	…
multiply.vhdl	…
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rotator.vhdl	…
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sim_16550_uart.vhdl	…
sim_bram.vhdl	…
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sim_bram_helpers_c.c	…
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sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
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sim_no_flash.vhdl	…
sim_pp_uart.vhdl	…
sim_vhpi_c.c	…
sim_vhpi_c.h	…
soc.vhdl	soc: Drive uart1_irq to 0 when we don't have UART1	4 years ago
spi_flash_ctrl.vhdl	Fix an issue in flash controller when BOOT_CLOCKS is false	4 years ago
spi_rxtx.vhdl	…
sync_fifo.vhdl	…
syscon.vhdl	…
utils.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_bram_tb.bin	…
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wishbone_bram_wrapper.vhdl	…
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README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)