core: Remove fetch2 pipeline stage
The fetch2 stage existed primarily to provide a stash buffer for the output of icache when a stall occurred. However, we can get the same effect -- of having the input to decode1 stay unchanged on a stall cycle -- by using the read enable of the BRAMs in icache, and by adding logic to keep the outputs unchanged on a clock cycle when stall_in = 1. This reduces branch and interrupt latency by one cycle. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>pull/208/head
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity fetch2 is
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port(
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clk : in std_ulogic;
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rst : in std_ulogic;
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stall_in : in std_ulogic;
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flush_in : in std_ulogic;
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-- Results from icache
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i_in : in IcacheToFetch2Type;
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-- Output to decode
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f_out : out Fetch2ToDecode1Type
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);
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end entity fetch2;
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architecture behaviour of fetch2 is
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-- The icache cannot stall, so we need to stash a cycle
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-- of output from it when we stall.
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type reg_internal_type is record
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stash : IcacheToFetch2Type;
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stash_valid : std_ulogic;
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stopped : std_ulogic;
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end record;
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signal r_int, rin_int : reg_internal_type;
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signal r, rin : Fetch2ToDecode1Type;
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begin
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regs : process(clk)
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begin
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if rising_edge(clk) then
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if (r /= rin) then
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report "fetch2 rst:" & std_ulogic'image(rst) &
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" S:" & std_ulogic'image(stall_in) &
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" F:" & std_ulogic'image(flush_in) &
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" T:" & std_ulogic'image(rin.stop_mark) &
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" V:" & std_ulogic'image(rin.valid) &
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" FF:" & std_ulogic'image(rin.fetch_failed) &
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" nia:" & to_hstring(rin.nia);
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end if;
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-- Output state remains unchanged on stall, unless we are flushing
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if rst = '1' or flush_in = '1' or stall_in = '0' then
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r <= rin;
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end if;
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-- Internal state is updated on every clock
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r_int <= rin_int;
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end if;
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end process;
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comb : process(all)
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variable v : Fetch2ToDecode1Type;
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variable v_int : reg_internal_type;
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variable v_i_in : IcacheToFetch2Type;
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begin
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v := r;
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v_int := r_int;
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-- If stalling, stash away the current input from the icache
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if stall_in = '1' and v_int.stash_valid = '0' then
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v_int.stash := i_in;
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v_int.stash_valid := '1';
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end if;
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-- If unstalling, source input from the stash and invalidate it,
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-- otherwise source normally from the icache.
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--
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v_i_in := i_in;
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if v_int.stash_valid = '1' and stall_in = '0' then
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v_i_in := v_int.stash;
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v_int.stash_valid := '0';
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end if;
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v.valid := v_i_in.valid;
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v.stop_mark := v_i_in.stop_mark;
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v.fetch_failed := v_i_in.fetch_failed;
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v.nia := v_i_in.nia;
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v.insn := v_i_in.insn;
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-- Clear stash internal valid bit on flush. We still mark
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-- the stash itself as valid since we still want to override
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-- whatever comes form icache when unstalling, but we'll
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-- override it with something invalid.
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--
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if flush_in = '1' then
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v_int.stash.valid := '0';
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v_int.stash.fetch_failed := '0';
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end if;
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-- If we are flushing or the instruction comes with a stop mark
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-- we tag it as invalid so it doesn't get decoded and executed
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if flush_in = '1' or v.stop_mark = '1' then
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v.valid := '0';
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v.fetch_failed := '0';
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end if;
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-- Clear stash on reset
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if rst = '1' then
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v_int.stash_valid := '0';
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v.valid := '0';
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end if;
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-- Update registers
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rin <= v;
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rin_int <= v_int;
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-- Update outputs
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f_out <= r;
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end process;
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end architecture behaviour;
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