microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Iago Caran Aquino de1bf10114 tests/pmu: Add load/store completed, instruction count and cycle count tests Signed-off-by: Iago Caran Aquino <iago.caran@gmail.com>		2 years ago
.github/workflows	ci: Add new Orange Crab build	3 years ago
constraints	orangecrab: add Orange Crab r0.2 target	3 years ago
fpga	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
hello_world	Zero BSS in hello world test	3 years ago
include	arty_a7: Add litesdcard interface	4 years ago
lib	console: Add support for the 16550 UART	5 years ago
litedram	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
liteeth	Regenerate litedram and liteeth	3 years ago
litesdcard	litesdcard: add lattice, regenerate	3 years ago
media	Add title image	5 years ago
micropython	tests: Add updated micropython build with 16550 support	5 years ago
openocd	flash-arty: Add cable argument	3 years ago
rust_lib_demo	console: Cleanup console API	5 years ago
scripts	mw_debug: Add STATIC_URJTAG flag	3 years ago
sim-unisim	Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs	5 years ago
tests	tests/pmu: Add load/store completed, instruction count and cycle count tests	2 years ago
uart16550	Add uart16550 files from fusesoc	5 years ago
verilator	verilator: Specify top level module	3 years ago
.gitignore	Add liteeth/build to gitignore	3 years ago
LICENSE	Initial import of microwatt	5 years ago
Makefile	dmi_dtm_ecp5: Use ECP5 JTAGG for DMI	3 years ago
README.md	README: Add Linux on Microwatt instructions	3 years ago
cache_ram.vhdl	Reformat cache_ram	4 years ago
common.vhdl	Remove unused sequential signal from Fetch1ToIcacheType	3 years ago
control.vhdl	Remove some FPGA style signal inits	3 years ago
core.vhdl	core: Remove unused icache_inv signal	3 years ago
core_debug.vhdl	core_debug: Initialise gspr_index	3 years ago
core_dram_tb.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
core_flash_tb.vhdl	Reformat testbenches	4 years ago
core_tb.vhdl	Reformat testbenches	4 years ago
countbits.vhdl	Use alternative count-leading-zeroes algorithm in the FPU and LSU	3 years ago
countbits_tb.vhdl	core: Make popcnt* take two cycles	3 years ago
cr_file.vhdl	Reformat cr_file	4 years ago
crhelpers.vhdl	crhelpers: Constraint "crnum" integer	5 years ago
dcache.vhdl	dcache: remove unused do_write signal	3 years ago
dcache_tb.vhdl	Reformat testbenches	4 years ago
decode1.vhdl	decode1: Conditional trap instructions don't need to be single-issue	3 years ago
decode2.vhdl	core: Make popcnt* take two cycles	3 years ago
decode_types.vhdl	core: Crack update-form loads into two internal ops	4 years ago
divider.vhdl	divider: Fix d_out.overflow U state issue	3 years ago
divider_tb.vhdl	Replaced VHDL assert and report with VUnit checking and logging	4 years ago
dmi_dtm_dummy.vhdl	Fix build issue in dmi_dtm_dummy.vhdl	5 years ago
dmi_dtm_ecp5.vhdl	dmi_dtm_ecp5: Use ECP5 JTAGG for DMI	3 years ago
dmi_dtm_tb.vhdl	Reformat testbenches	4 years ago
dmi_dtm_xilinx.vhdl	Fix some whitespace issues	3 years ago
dram_tb.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
execute1.vhdl	execute1: sub_mux_sel and result_mux_sel are unused	3 years ago
fetch1.vhdl	fetch1/icache1: Remove the use_previous logic	3 years ago
foreign_random.vhdl	Make core testbenches recognized by VUnit	4 years ago
fpu.vhdl	fpu: Reduce uninitialised signals	3 years ago
glibc_random.vhdl	Reformat glibc_random	5 years ago
glibc_random_helpers.vhdl	Reformat glibc_random	5 years ago
gpio.vhdl	Remove some FPGA style signal inits	3 years ago
helpers.vhdl	xics: Rework the irq_gen process	3 years ago
icache.vhdl	Merge pull request #373 from antonblanchard/icache-insn-u-state	3 years ago
icache_tb.vhdl	fix: fix icache_tb not finishing correctly	3 years ago
icache_test.bin	icache_tb: Improve test and include test file	5 years ago
insn_helpers.vhdl	core: Implement quadword loads and stores	4 years ago
loadstore1.vhdl	loadstore1: reduce U state being output	3 years ago
logical.vhdl	core: Make popcnt* take two cycles	3 years ago
microwatt.core	core: Make popcnt* take two cycles	3 years ago
mmu.vhdl	MMU: Implement a vestigial partition table	4 years ago
multiply.vhdl	core: Add a short multiplier	3 years ago
multiply_tb.vhdl	Replaced VHDL assert and report with VUnit checking and logging	4 years ago
nonrandom.vhdl	Add random number generator and implement the darn instruction	4 years ago
plru.vhdl	Reformat plru	4 years ago
plru_tb.vhdl	Replaced VHDL assert and report with VUnit checking and logging	4 years ago
pmu.vhdl	PMU: Add several more events	3 years ago
ppc_fx_insns.vhdl	Fix some whitespace issues	3 years ago
random.vhdl	Make core testbenches recognized by VUnit	4 years ago
register_file.vhdl	Reformat register_file	4 years ago
rotator.vhdl	Reformat rotator	4 years ago
rotator_tb.vhdl	Replaced VHDL assert and report with VUnit checking and logging	4 years ago
run.py	VUnit: style	3 years ago
sim_16550_uart.vhdl	uart: Add a simulation model for the 16550 compatible UART	5 years ago
sim_bram.vhdl	Rename 'do' signal to avoid verilator System Verilog warning	3 years ago
sim_bram_helpers.vhdl	ram: Rework main RAM interface	5 years ago
sim_bram_helpers_c.c	Consolidate VHPI code	5 years ago
sim_console.vhdl	Reformat sim_console	5 years ago
sim_console_c.c	sim_console: Fix polling to check for POLLIN	5 years ago
sim_jtag.vhdl	Add jtag support in simulation via a socket	5 years ago
sim_jtag_socket.vhdl	Add jtag support in simulation via a socket	5 years ago
sim_jtag_socket_c.c	Consolidate VHPI code	5 years ago
sim_no_flash.vhdl	spi: Add simulation support	5 years ago
sim_pp_uart.vhdl	uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl	5 years ago
sim_vhpi_c.c	Consolidate VHPI code	5 years ago
sim_vhpi_c.h	Consolidate VHPI code	5 years ago
soc.vhdl	Remove some FPGA style signal inits	3 years ago
spi_flash_ctrl.vhdl	Remove some FPGA style signal inits	3 years ago
spi_rxtx.vhdl	Remove some FPGA style signal inits	3 years ago
sync_fifo.vhdl	litedram: Add an L2 cache with store queue	5 years ago
syscon.vhdl	Make wishbone addresses be in units of doublewords or words	3 years ago
utils.vhdl	litedram: Add support for booting without BRAM	5 years ago
wishbone_arbiter.vhdl	wb_arbiter: Early master selection	5 years ago
wishbone_bram_tb.bin	ram: Rework main RAM interface	5 years ago
wishbone_bram_tb.vhdl	Make wishbone addresses be in units of doublewords or words	3 years ago
wishbone_bram_wrapper.vhdl	wishbone_bram_wrapper ram_addr_bits is 1 bit off	3 years ago
wishbone_debug_master.vhdl	Make wishbone addresses be in units of doublewords or words	3 years ago
wishbone_types.vhdl	Introduce addr_to_wb() and wb_to_addr() helpers	3 years ago
writeback.vhdl	PMU: Add several more events	3 years ago
xics.vhdl	xics: Fix warning when comparing two std_ulogic_vectors	3 years ago
xilinx-mult.vhdl	core: Add a short multiplier	3 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run

fusesoc init
fusesoc fetch uart16550
fusesoc library add microwatt /path/to/microwatt

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.

fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Linux on Microwatt

Mainline Linux supports Microwatt as of v5.14. The Arty A7 is the best tested platform, but it's also been tested on the OrangeCrab and ButterStick.

Use buildroot to create a userspace

A small change is required to glibc in order to support the VMX/AltiVec-less Microwatt, as float128 support is mandiatory and for this in GCC requires VSX/AltiVec. This change is included in Joel's buildroot fork, along with a defconfig:
```
git clone -b microwatt https://github.com/shenki/buildroot
cd buildroot
make ppc64le_microwatt_defconfig
make
```
The output is output/images/rootfs.cpio.

Build the Linux kernel

git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
cd linux
make ARCH=powerpc microwatt_defconfig
make ARCH=powerpc CROSS_COMPILE=powerpc64le-linux-gnu- \
  CONFIG_INITRAMFS_SOURCE=/buildroot/output/images/rootfs.cpio -j`nproc`

The output is arch/powerpc/boot/dtbImage.microwatt.elf.

Build gateware using FuseSoC

First configure FuseSoC as above.
```
fusesoc run --build --target=arty_a7-100 microwatt --no_bram --memory_size=0
```
The output is build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit.
Program the flash

This operation will overwrite the contents of your flash.

For the Arty A7 A100, set FLASH_ADDRESS to 0x400000 and pass -f a100.

For the Arty A7 A35, set FLASH_ADDRESS to 0x300000 and pass -f a35.
```
microwatt/openocd/flash-arty -f a100 build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit
microwatt/openocd/flash-arty -f a100 dtbImage.microwatt.elf -t bin -a $FLASH_ADDRESS
```
Connect to the second USB TTY device exposed by the FPGA
```
minicom -D /dev/ttyUSB1
```
The gateware has firmware that will look at FLASH_ADDRESS and attempt to parse an ELF there, loading it to the address specified in the ELF header and jumping to it.

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

There are a few instructions still to be implemented:
- Vector/VMX/VSX