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caravel-mpw7-20221125
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trace-test
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litedram-update
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fpu-init
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microwatt/fpga
History
Michael Neuling d92af779eb Add Antmicro Artix DC SCM hello world support 
works with:
 fusesoc build --target=antmicro-artix-dc-scm microwatt --ram_init_file=../hello_world/hello_world.hex

Signed-off-by: Michael Neuling <mikey@neuling.org>
[joel: Fixes and updates]
Signed-off-by: Joel Stanley <joel@jms.id.au>
 		3 years ago
..
LICENSE
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acorn-cle-215.xdc
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antmicro_artix_dc_scm.xdc Add Antmicro Artix DC SCM hello world support 3 years ago
arty_a7.xdc Remove -add from xdc files 4 years ago
clk_gen_bypass.vhd
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clk_gen_ecp5.vhd ECP5: Adjust PLL constants so the PLL lock indication works 4 years ago
clk_gen_mcmm.vhd
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clk_gen_plle2.vhd fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz 4 years ago
cmod_a7-35.xdc Remove -add from xdc files 4 years ago
firmware.hex
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fpga-random.vhdl
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fpga-random.xdc
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genesys2.xdc Remove -waveform from xdc files 4 years ago
hello_world.hex
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main_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning 4 years ago
nexys-video.xdc litesdcard: Add Nexys Video support 4 years ago
nexys_a7.xdc Remove -add from xdc files 4 years ago
pp_fifo.vhd
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pp_soc_uart.vhd
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pp_utilities.vhd
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soc_reset.vhdl
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soc_reset_tb.vhdl
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top-acorn-cle-215.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 4 years ago
top-antmicro-artix-dc-scm.vhdl Add Antmicro Artix DC SCM hello world support 3 years ago
top-arty.vhdl Remove option for "short" 16x16 bit multiplier 3 years ago
top-generic.vhdl Remove option for "short" 16x16 bit multiplier 3 years ago
top-genesys2.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 4 years ago
top-nexys-video.vhdl Remove option for "short" 16x16 bit multiplier 3 years ago
top-orangecrab0.2.vhdl Remove option for "short" 16x16 bit multiplier 3 years ago
top-wukong-v2.vhdl Remove option for "short" 16x16 bit multiplier 3 years ago
wukong-v2.xdc Add support for QMTech Wukong v2 board 4 years ago