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34 lines
1.5 KiB
Plaintext
34 lines
1.5 KiB
Plaintext
################################################################################
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# clkin, reset, uart pins...
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################################################################################
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set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
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set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }];
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set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }];
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set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { d11_led }];
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set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { d12_led }];
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set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { d13_led }];
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################################################################################
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# Design constraints and bitsteam attributes
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################################################################################
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#Internal VREF
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set_property INTERNAL_VREF 0.675 [get_iobanks 34]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CFGBVS VCCO [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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################################################################################
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# Clock constraints
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################################################################################
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create_clock -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
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