A tiny Open POWER ISA softcore written in VHDL 2008
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Benjamin Herrenschmidt d654667304 console: Add support for the 16550 UART
And rebuild various binaries

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
3 years ago
.github/workflows Move from travis to github workflow 3 years ago
constraints Initial support for ghdl synthesis 4 years ago
fpga uart: Import and hook up opencore 16550 compatible UART 3 years ago
hello_world console: Add support for the 16550 UART 3 years ago
include console: Add support for the 16550 UART 3 years ago
lib console: Add support for the 16550 UART 3 years ago
litedram console: Add support for the 16550 UART 3 years ago
liteeth liteeth: Hook up LiteX LiteEth ethernet controller 3 years ago
media Add title image 4 years ago
micropython Update micropython 4 years ago
openocd flash-arty: update error message (#203) 3 years ago
rust_lib_demo console: Cleanup console API 3 years ago
scripts uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 3 years ago
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs 4 years ago
tests console: Add support for the 16550 UART 3 years ago
verilator Pass clock frequency to UART sim wrapper 3 years ago
.gitignore gitignore: Add more exlusions 3 years ago
LICENSE Initial import of microwatt 4 years ago
Makefile uart: Add a simulation model for the 16550 compatible UART 3 years ago
README.md Add Makefile command line variables to enable docker and podman 3 years ago
cache_ram.vhdl dcache: Rework RAM wrapper to synthetize better on Xilinx 3 years ago
common.vhdl ex1: Add SPR_TBU support 3 years ago
control.vhdl core: Use a busy signal rather than a stall 3 years ago
core.vhdl Make LOG_LENGTH configurable per FPGA variant 3 years ago
core_debug.vhdl Make LOG_LENGTH configurable per FPGA variant 3 years ago
core_dram_tb.vhdl soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding 3 years ago
core_flash_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 3 years ago
core_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 3 years ago
countzero.vhdl countzero: Add a register to help make timing 4 years ago
countzero_tb.vhdl Exit cleanly from testbench on success 3 years ago
cr_file.vhdl Add core logging 3 years ago
cr_hazard.vhdl core: Use a busy signal rather than a stall 3 years ago
crhelpers.vhdl crhelpers: Constraint "crnum" integer 4 years ago
dcache.vhdl dcache: Reduce back-to-back store latency from 3 cycles to 2 3 years ago
dcache_tb.vhdl Exit cleanly from testbench on success 3 years ago
decode1.vhdl core: Implement a simple branch predictor 3 years ago
decode2.vhdl core: Implement a simple branch predictor 3 years ago
decode_types.vhdl core: Do addpcis using the main adder (#189) 3 years ago
divider.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations 4 years ago
divider_tb.vhdl Exit cleanly from testbench on success 3 years ago
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl 4 years ago
dmi_dtm_tb.vhdl ram: Rework main RAM interface 4 years ago
dmi_dtm_xilinx.vhdl dmi: Add ASYNC_REG attribute on synchronizers (#200) 3 years ago
dram_tb.vhdl litedram: Improve dram_tb error output 3 years ago
execute1.vhdl ex1: Add SPR_TBU support 3 years ago
fetch1.vhdl core: Implement a simple branch predictor 3 years ago
glibc_random.vhdl Reformat glibc_random 4 years ago
glibc_random_helpers.vhdl Reformat glibc_random 4 years ago
gpr_hazard.vhdl core: Use a busy signal rather than a stall 3 years ago
helpers.vhdl execute: Copy XER[SO] to CR for cmp[i] and cmpl[i] instructions 4 years ago
icache.vhdl icache: Improve latencies when reloading cache lines 3 years ago
icache_tb.vhdl core: Remove fetch2 pipeline stage 3 years ago
icache_test.bin icache_tb: Improve test and include test file 4 years ago
insn_helpers.vhdl Implement the addpcis instruction 3 years ago
loadstore1.vhdl loadstore1: Reduce busy cycles 3 years ago
logical.vhdl execute1: Reduce width of the result mux to help timing 3 years ago
microwatt.core uart: Import and hook up opencore 16550 compatible UART 3 years ago
mmu.vhdl mmu: Take an extra cycle to do TLB invalidations 3 years ago
multiply.vhdl multiply: Move selection of result bits into execute1 3 years ago
multiply_tb.vhdl multiply: Move selection of result bits into execute1 3 years ago
plru.vhdl plru: Improve sensitivity list 4 years ago
plru_tb.vhdl Exit cleanly from testbench on success 3 years ago
ppc_fx_insns.vhdl core: Implement a simple branch predictor 3 years ago
register_file.vhdl Add core logging 3 years ago
rotator.vhdl Implement the extswsli instruction 3 years ago
rotator_tb.vhdl Exit cleanly from testbench on success 3 years ago
sim_16550_uart.vhdl uart: Add a simulation model for the 16550 compatible UART 3 years ago
sim_bram.vhdl ram: Rework main RAM interface 4 years ago
sim_bram_helpers.vhdl ram: Rework main RAM interface 4 years ago
sim_bram_helpers_c.c Consolidate VHPI code 4 years ago
sim_console.vhdl Reformat sim_console 4 years ago
sim_console_c.c Consolidate VHPI code 4 years ago
sim_jtag.vhdl Add jtag support in simulation via a socket 4 years ago
sim_jtag_socket.vhdl Add jtag support in simulation via a socket 4 years ago
sim_jtag_socket_c.c Consolidate VHPI code 4 years ago
sim_no_flash.vhdl spi: Add simulation support 3 years ago
sim_pp_uart.vhdl uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 3 years ago
sim_vhpi_c.c Consolidate VHPI code 4 years ago
sim_vhpi_c.h Consolidate VHPI code 4 years ago
soc.vhdl uart: Import and hook up opencore 16550 compatible UART 3 years ago
spi_flash_ctrl.vhdl spi: Add SPI Flash controller 3 years ago
spi_rxtx.vhdl spi: Add SPI Flash controller 3 years ago
sync_fifo.vhdl litedram: Add an L2 cache with store queue 3 years ago
syscon.vhdl uart: Import and hook up opencore 16550 compatible UART 3 years ago
utils.vhdl litedram: Add support for booting without BRAM 3 years ago
wishbone_arbiter.vhdl wb_arbiter: Early master selection 4 years ago
wishbone_bram_tb.bin ram: Rework main RAM interface 4 years ago
wishbone_bram_tb.vhdl Exit cleanly from testbench on success 3 years ago
wishbone_bram_wrapper.vhdl Add log2ceil and use it in bram code 4 years ago
wishbone_debug_master.vhdl wishbone_debug_master: Fix address auto-increment for memory writes 3 years ago
wishbone_types.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 3 years ago
writeback.vhdl core: Use a busy signal rather than a stall 3 years ago
xics.vhdl xics: Add support for reduced priority field size 3 years ago
xilinx-mult.vhdl multiply: Use DSP48 slices for multiplication on Xilinx FPGAs 3 years ago

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)