A tiny Open POWER ISA softcore written in VHDL 2008
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Benjamin Herrenschmidt bf7def5503 soc: Don't require dram wishbones signals to be wired by toplevel
Currently, when not using litedram, the top level still has to hook
up "dummy" wishbones to the main dram and control dram busses coming
out of the SoC and provide ack signals.

Instead, make the SoC generate the acks internally when not using
litedram and use defaults to make the wiring entirely optional.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
.github/workflows Move from travis to github workflow 4 years ago
constraints
fpga soc: Don't require dram wishbones signals to be wired by toplevel 4 years ago
hello_world
include spi: Add booting from flash to litedram init 4 years ago
lib sw: Properly mask syscon register fields 4 years ago
litedram spi: Add booting from flash to litedram init 4 years ago
media
micropython
openocd flash-arty: update error message (#203) 4 years ago
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LICENSE
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README.md
cache_ram.vhdl
common.vhdl
control.vhdl
core.vhdl icache: Fix icbi potentially clobbering the icache (#192) 4 years ago
core_debug.vhdl
core_dram_tb.vhdl soc: Add defaults for some input signals 4 years ago
core_flash_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 4 years ago
core_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 4 years ago
countzero.vhdl
countzero_tb.vhdl
cr_file.vhdl
cr_hazard.vhdl
crhelpers.vhdl
dcache.vhdl
dcache_tb.vhdl
decode1.vhdl decode1: Reformat to 4-space indentation 4 years ago
decode2.vhdl decode2: Reformat to 4-space indentation 4 years ago
decode_types.vhdl
divider.vhdl
divider_tb.vhdl
dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl
dmi_dtm_xilinx.vhdl dmi: Add ASYNC_REG attribute on synchronizers (#200) 4 years ago
dram_tb.vhdl litedram: Improve dram_tb error output 4 years ago
execute1.vhdl
fetch1.vhdl
fetch2.vhdl
glibc_random.vhdl
glibc_random_helpers.vhdl
gpr_hazard.vhdl
helpers.vhdl
icache.vhdl icache: Latch PLRU victim output (#199) 4 years ago
icache_tb.vhdl icache: Fix icbi potentially clobbering the icache (#192) 4 years ago
icache_test.bin
insn_helpers.vhdl
loadstore1.vhdl
logical.vhdl
microwatt.core spi: Add SPI Flash controller 4 years ago
mmu.vhdl
multiply.vhdl
multiply_tb.vhdl
plru.vhdl
plru_tb.vhdl
ppc_fx_insns.vhdl
register_file.vhdl
rotator.vhdl
rotator_tb.vhdl
sim_bram.vhdl
sim_bram_helpers.vhdl
sim_bram_helpers_c.c
sim_console.vhdl
sim_console_c.c
sim_jtag.vhdl
sim_jtag_socket.vhdl
sim_jtag_socket_c.c
sim_no_flash.vhdl spi: Add simulation support 4 years ago
sim_uart.vhdl
sim_vhpi_c.c
sim_vhpi_c.h
soc.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 4 years ago
spi_flash_ctrl.vhdl spi: Add SPI Flash controller 4 years ago
spi_rxtx.vhdl spi: Add SPI Flash controller 4 years ago
sync_fifo.vhdl
syscon.vhdl syscon: Remove combinational loop on ack and stall 4 years ago
utils.vhdl
wishbone_arbiter.vhdl
wishbone_bram_tb.bin
wishbone_bram_tb.vhdl
wishbone_bram_wrapper.vhdl
wishbone_debug_master.vhdl
wishbone_types.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 4 years ago
writeback.vhdl
xics.vhdl

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)