A tiny Open POWER ISA softcore written in VHDL 2008
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 
Go to file
Benjamin Herrenschmidt bedc9c0085 litedram: l2: Add a few comments about litedram behaviour
litedram ignores a couple of signals of his "pseudo-axi" port,
this adds a bit of documentation around it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
.github/workflows Create github artifacts for ECP5 devices 4 years ago
constraints
fpga litedram: l2: Add support for more geometries 4 years ago
hello_world Send line feed if we get a carriage return in hello world. 4 years ago
include syscon: Add flag to indicate the timebase frequency 4 years ago
lib console: Add support for the 16550 UART 4 years ago
litedram litedram: l2: Add a few comments about litedram behaviour 4 years ago
liteeth liteeth: Hook up LiteX LiteEth ethernet controller 4 years ago
media
micropython tests: Add updated micropython build with 16550 support 4 years ago
openocd
rust_lib_demo console: Cleanup console API 4 years ago
scripts uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 4 years ago
sim-unisim
tests tests: Add updated micropython build with 16550 support 4 years ago
uart16550 Add uart16550 files from fusesoc 4 years ago
verilator
.gitignore Add yosys builds files to gitignore 4 years ago
LICENSE
Makefile Add PLL for ECP5 device 4 years ago
README.md
cache_ram.vhdl
common.vhdl execute1: Do forwarding of the CR result to the next instruction 4 years ago
control.vhdl execute1: Do forwarding of the CR result to the next instruction 4 years ago
core.vhdl Make LOG_LENGTH configurable per FPGA variant 4 years ago
core_debug.vhdl Make LOG_LENGTH configurable per FPGA variant 4 years ago
core_dram_tb.vhdl litedram: l2: Add support for more geometries 4 years ago
core_flash_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 4 years ago
core_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 4 years ago
countzero.vhdl
countzero_tb.vhdl
cr_file.vhdl
cr_hazard.vhdl execute1: Do forwarding of the CR result to the next instruction 4 years ago
crhelpers.vhdl
dcache.vhdl dcache: Reduce back-to-back store latency from 3 cycles to 2 4 years ago
dcache_tb.vhdl
decode1.vhdl execute1: Do forwarding of the CR result to the next instruction 4 years ago
decode2.vhdl execute1: Do forwarding of the CR result to the next instruction 4 years ago
decode_types.vhdl
divider.vhdl
divider_tb.vhdl
dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl
dmi_dtm_xilinx.vhdl
dram_tb.vhdl litedram: l2: Add support for more geometries 4 years ago
execute1.vhdl execute1: Do forwarding of the CR result to the next instruction 4 years ago
fetch1.vhdl core: Implement CFAR register 4 years ago
glibc_random.vhdl
glibc_random_helpers.vhdl
gpr_hazard.vhdl core: Use a busy signal rather than a stall 4 years ago
helpers.vhdl
icache.vhdl Merge pull request #206 from Jbalkind/icachecleanup 4 years ago
icache_tb.vhdl
icache_test.bin
insn_helpers.vhdl
loadstore1.vhdl loadstore1: Reduce busy cycles 4 years ago
logical.vhdl logical: Only do output inversion for OP_AND, OP_OR and OP_XOR 4 years ago
microwatt.core corefile/nexys_video: Parameter fixes 4 years ago
mmu.vhdl mmu: Take an extra cycle to do TLB invalidations 4 years ago
multiply.vhdl
multiply_tb.vhdl
plru.vhdl
plru_tb.vhdl
ppc_fx_insns.vhdl core: Implement a simple branch predictor 4 years ago
register_file.vhdl
rotator.vhdl
rotator_tb.vhdl
sim_16550_uart.vhdl uart: Add a simulation model for the 16550 compatible UART 4 years ago
sim_bram.vhdl
sim_bram_helpers.vhdl
sim_bram_helpers_c.c
sim_console.vhdl
sim_console_c.c sim_console: Fix polling to check for POLLIN 4 years ago
sim_jtag.vhdl
sim_jtag_socket.vhdl
sim_jtag_socket_c.c
sim_no_flash.vhdl
sim_pp_uart.vhdl uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 4 years ago
sim_vhpi_c.c
sim_vhpi_c.h
soc.vhdl uart: Make 16550 the default 4 years ago
spi_flash_ctrl.vhdl spi: Send dummy clocks at boot 4 years ago
spi_rxtx.vhdl
sync_fifo.vhdl
syscon.vhdl syscon: Add flag to indicate the timebase frequency 4 years ago
utils.vhdl
wishbone_arbiter.vhdl
wishbone_bram_tb.bin
wishbone_bram_tb.vhdl
wishbone_bram_wrapper.vhdl
wishbone_debug_master.vhdl
wishbone_types.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 4 years ago
writeback.vhdl core: Use a busy signal rather than a stall 4 years ago
xics.vhdl xics: Add support for reduced priority field size 4 years ago
xilinx-mult.vhdl

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)