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Paul Mackerras
8cdb00652b
Rename 'do' signal to avoid verilator System Verilog warning |
3 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| acorn-cle-215.xdc | ||
| arty_a7.xdc | 3 years ago | |
| clk_gen_bypass.vhd | ||
| clk_gen_ecp5.vhd | ||
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | ||
| cmod_a7-35.xdc | 3 years ago | |
| firmware.hex | ||
| fpga-random.vhdl | ||
| fpga-random.xdc | ||
| genesys2.xdc | ||
| hello_world.hex | ||
| main_bram.vhdl | 3 years ago | |
| nexys-video.xdc | 3 years ago | |
| nexys_a7.xdc | 3 years ago | |
| pp_fifo.vhd | ||
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| top-acorn-cle-215.vhdl | ||
| top-arty.vhdl | 3 years ago | |
| top-generic.vhdl | ||
| top-genesys2.vhdl | ||
| top-nexys-video.vhdl | 3 years ago | |