A tiny Open POWER ISA softcore written in VHDL 2008
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Paul Mackerras bb5f356386 loadstore1: Make r1.req.addr not depend on l_in.valid
Some critical path reports showed r1.req.addr depending on l_in.valid,
which then depended ultimately on the dcache's r1.ls_valid.  In fact
we can update r1.req.addr (and other fields of r1.req, except for
r1.req.valid) independently of l_in.valid as long as busy = 0.
We do also need to preserve r1.req.addr0 when l_in.valid = 0, so we
pull it out of r1.req and store it separately in r1.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years ago
.github/workflows ci: Add verilator tests 3 years ago
constraints
fpga Merge pull request #316 from antonblanchard/verilator-fix 3 years ago
hello_world
include arty_a7: Add litesdcard interface 3 years ago
lib console: Add support for the 16550 UART 4 years ago
litedram litedram: Regenerate from upstream litex 3 years ago
liteeth liteeth: Regenerate from upstream litex 3 years ago
litesdcard litesdcard: Use vendor not board type 3 years ago
media Add title image 5 years ago
micropython
openocd openocd: Fix verify command for v0.10 3 years ago
rust_lib_demo
scripts makefile: Add some verilator micropython tests 3 years ago
sim-unisim
tests tests/misc: Add a test for a load that hits two preceding stores 3 years ago
uart16550 Add uart16550 files from fusesoc 4 years ago
verilator verilator: Specify top level module 3 years ago
.gitignore
LICENSE
Makefile makefile: Check environment for MEMORY_SIZE/RAM_INIT_FILE 3 years ago
README.md Update documentation. (#280) 3 years ago
cache_ram.vhdl
common.vhdl core: Predict not-taken conditional branches using BTC 3 years ago
control.vhdl Reformat control 3 years ago
core.vhdl PMU: Add several more events 3 years ago
core_debug.vhdl Fix some whitespace issues 3 years ago
core_dram_tb.vhdl Reformat testbenches 3 years ago
core_flash_tb.vhdl Reformat testbenches 3 years ago
core_tb.vhdl Reformat testbenches 3 years ago
countzero.vhdl
countzero_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
cr_file.vhdl
crhelpers.vhdl
dcache.vhdl dcache: Loads from non-cacheable PTEs load entire 64 bits 3 years ago
dcache_tb.vhdl Reformat testbenches 3 years ago
decode1.vhdl Merge pull request #324 from paulusmack/master 3 years ago
decode2.vhdl
decode_types.vhdl
divider.vhdl
divider_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl Reformat testbenches 3 years ago
dmi_dtm_xilinx.vhdl Fix some whitespace issues 3 years ago
dram_tb.vhdl Reformat testbenches 3 years ago
execute1.vhdl core: Fix mcrxrx, addpcis and bpermd 3 years ago
fetch1.vhdl core: Predict not-taken conditional branches using BTC 3 years ago
foreign_random.vhdl Make core testbenches recognized by VUnit 3 years ago
fpu.vhdl
glibc_random.vhdl
glibc_random_helpers.vhdl
gpio.vhdl
helpers.vhdl
icache.vhdl core: Predict not-taken conditional branches using BTC 3 years ago
icache_tb.vhdl Reformat testbenches 3 years ago
icache_test.bin
insn_helpers.vhdl
loadstore1.vhdl loadstore1: Make r1.req.addr not depend on l_in.valid 3 years ago
logical.vhdl core: Fix mcrxrx, addpcis and bpermd 3 years ago
microwatt.core Merge pull request #315 from paulusmack/pmu 3 years ago
mmu.vhdl MMU: Implement a vestigial partition table 3 years ago
multiply.vhdl
multiply_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
nonrandom.vhdl
plru.vhdl
plru_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
pmu.vhdl PMU: Add several more events 3 years ago
ppc_fx_insns.vhdl Fix some whitespace issues 3 years ago
random.vhdl Make core testbenches recognized by VUnit 3 years ago
register_file.vhdl
rotator.vhdl
rotator_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
run.py VUnit: style 3 years ago
sim_16550_uart.vhdl
sim_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning 3 years ago
sim_bram_helpers.vhdl
sim_bram_helpers_c.c
sim_console.vhdl
sim_console_c.c
sim_jtag.vhdl
sim_jtag_socket.vhdl
sim_jtag_socket_c.c
sim_no_flash.vhdl
sim_pp_uart.vhdl
sim_vhpi_c.c
sim_vhpi_c.h
soc.vhdl gpio: Add HAS_GPIO to avoid verilator build errors 3 years ago
spi_flash_ctrl.vhdl Reformat spi_flash_ctrl 3 years ago
spi_rxtx.vhdl
sync_fifo.vhdl
syscon.vhdl arty_a7: Add litesdcard interface 3 years ago
utils.vhdl
wishbone_arbiter.vhdl
wishbone_bram_tb.bin
wishbone_bram_tb.vhdl Reformat testbenches 3 years ago
wishbone_bram_wrapper.vhdl Rename 'do' signal to avoid verilator System Verilog warning 3 years ago
wishbone_debug_master.vhdl Fix some whitespace issues 3 years ago
wishbone_types.vhdl arty_a7: Add litesdcard interface 3 years ago
writeback.vhdl PMU: Add several more events 3 years ago
xics.vhdl Fix some whitespace issues 3 years ago
xilinx-mult.vhdl xilinx-mult: Move some registers later in the data flow 3 years ago

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)