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Raptor Engineering Development Team fcb783a0fb Extend LiteDRAM VHDL wrapper to allow more than one clock line 
This is necessary for the upcoming Arctic Tern system enablement,
since Arctic Tern uses two DRAM devices and a separate clock line
is routed to each device.  LiteX handles this behavior correctly,
therefore we assume other hardware exists that uses a similar
DRAM clock design.

Updates from Mikey to fix some compile issues.

Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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LICENSE
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acorn-cle-215.xdc
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arty_a7.xdc Remove -add from xdc files
clk_gen_bypass.vhd
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clk_gen_ecp5.vhd ECP5: Adjust PLL constants so the PLL lock indication works
clk_gen_mcmm.vhd
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clk_gen_plle2.vhd fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz
cmod_a7-35.xdc Remove -add from xdc files
firmware.hex
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fpga-random.vhdl
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fpga-random.xdc
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genesys2.xdc
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hello_world.hex
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main_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning
nexys-video.xdc litesdcard: Add Nexys Video support
nexys_a7.xdc Remove -add from xdc files
pp_fifo.vhd
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pp_soc_uart.vhd
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pp_utilities.vhd
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soc_reset.vhdl
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soc_reset_tb.vhdl
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top-acorn-cle-215.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line
top-arty.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line
top-generic.vhdl core: Add a short multiplier
top-genesys2.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line
top-nexys-video.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line
top-orangecrab0.2.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line
top-wukong-v2.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line
wukong-v2.xdc Add support for QMTech Wukong v2 board