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microwatt/fpga
Raptor Engineering Development Team fcb783a0fb Extend LiteDRAM VHDL wrapper to allow more than one clock line
This is necessary for the upcoming Arctic Tern system enablement,
since Arctic Tern uses two DRAM devices and a separate clock line
is routed to each device.  LiteX handles this behavior correctly,
therefore we assume other hardware exists that uses a similar
DRAM clock design.

Updates from Mikey to fix some compile issues.

Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
..
LICENSE
acorn-cle-215.xdc
arty_a7.xdc
clk_gen_bypass.vhd
clk_gen_ecp5.vhd ECP5: Adjust PLL constants so the PLL lock indication works 3 years ago
clk_gen_mcmm.vhd
clk_gen_plle2.vhd
cmod_a7-35.xdc
firmware.hex
fpga-random.vhdl
fpga-random.xdc
genesys2.xdc
hello_world.hex
main_bram.vhdl
nexys-video.xdc litesdcard: Add Nexys Video support 3 years ago
nexys_a7.xdc
pp_fifo.vhd
pp_soc_uart.vhd
pp_utilities.vhd
soc_reset.vhdl
soc_reset_tb.vhdl
top-acorn-cle-215.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 2 years ago
top-arty.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 2 years ago
top-generic.vhdl
top-genesys2.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 2 years ago
top-nexys-video.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 2 years ago
top-orangecrab0.2.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 2 years ago
top-wukong-v2.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 2 years ago
wukong-v2.xdc