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Raptor Engineering Development Team fcb783a0fb Extend LiteDRAM VHDL wrapper to allow more than one clock line ... This is necessary for the upcoming Arctic Tern system enablement, since Arctic Tern uses two DRAM devices and a separate clock line is routed to each device. LiteX handles this behavior correctly, therefore we assume other hardware exists that uses a similar DRAM clock design. Updates from Mikey to fix some compile issues. Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Michael Neuling <mikey@neuling.org>		3 years ago
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LICENSE	…
acorn-cle-215.xdc	acorn: Add support for the Acorn CLE 215+	4 years ago
arty_a7.xdc	Remove -add from xdc files	3 years ago
clk_gen_bypass.vhd	Fix clk_gen_bypass	5 years ago
clk_gen_ecp5.vhd	ECP5: Adjust PLL constants so the PLL lock indication works	3 years ago
clk_gen_mcmm.vhd	Fix some whitespace issues	3 years ago
clk_gen_plle2.vhd	fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz	3 years ago
cmod_a7-35.xdc	Remove -add from xdc files	3 years ago
firmware.hex	…
fpga-random.vhdl	Add random number generator and implement the darn instruction	4 years ago
fpga-random.xdc	Add random number generator and implement the darn instruction	4 years ago
genesys2.xdc	Remove -waveform from xdc files	3 years ago
hello_world.hex	hello_world: Use new headers and frequency from syscon	5 years ago
main_bram.vhdl	Rename 'do' signal to avoid verilator System Verilog warning	3 years ago
nexys-video.xdc	litesdcard: Add Nexys Video support	3 years ago
nexys_a7.xdc	Remove -add from xdc files	3 years ago
pp_fifo.vhd	pp_fifo: Fix full fifo losing all data on simultaneous push & pop	5 years ago
pp_soc_uart.vhd	uart: Remove combinational loops on ack and stall signal	5 years ago
pp_utilities.vhd	…
soc_reset.vhdl	soc_reset: Use counters, add synchronizers	5 years ago
soc_reset_tb.vhdl	Exit cleanly from testbench on success	5 years ago
top-acorn-cle-215.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
top-arty.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
top-generic.vhdl	core: Add a short multiplier	3 years ago
top-genesys2.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
top-nexys-video.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
top-orangecrab0.2.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
top-wukong-v2.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
wukong-v2.xdc	Add support for QMTech Wukong v2 board	3 years ago