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Matt Johnston 049f0549d8 orangecrab: Fix sdcard wishbone addressing 
Orangecrab missed out on:

Make wishbone addresses be in units of doublewords or words
Author: Paul Mackerras <paulus@ozlabs.org>
Date:   Wed Sep 15 18:18:09 2021 +1000

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
..
LICENSE Initial import of microwatt
acorn-cle-215.xdc acorn: Add support for the Acorn CLE 215+
arty_a7.xdc Remove -add from xdc files
clk_gen_bypass.vhd Fix clk_gen_bypass
clk_gen_ecp5.vhd ECP5: Adjust PLL constants so the PLL lock indication works
clk_gen_mcmm.vhd Fix some whitespace issues
clk_gen_plle2.vhd fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz
cmod_a7-35.xdc Remove -add from xdc files
firmware.hex Add a few more FPGA related files
fpga-random.vhdl Add random number generator and implement the darn instruction
fpga-random.xdc Add random number generator and implement the darn instruction
genesys2.xdc Remove -waveform from xdc files
hello_world.hex hello_world: Use new headers and frequency from syscon
main_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning
nexys-video.xdc litesdcard: Add Nexys Video support
nexys_a7.xdc Remove -add from xdc files
pp_fifo.vhd pp_fifo: Fix full fifo losing all data on simultaneous push & pop
pp_soc_uart.vhd uart: Remove combinational loops on ack and stall signal
pp_utilities.vhd Initial import of microwatt
soc_reset.vhdl soc_reset: Use counters, add synchronizers
soc_reset_tb.vhdl Exit cleanly from testbench on success
top-acorn-cle-215.vhdl acorn: Add support for the Acorn CLE 215+
top-arty.vhdl Merge pull request from paulusmack/wb-fix
top-generic.vhdl core: Add a short multiplier
top-genesys2.vhdl fpga: Add support for Genesys2
top-nexys-video.vhdl Merge pull request from paulusmack/wb-fix
top-orangecrab0.2.vhdl orangecrab: Fix sdcard wishbone addressing
top-wukong-v2.vhdl Add support for QMTech Wukong v2 board
wukong-v2.xdc Add support for QMTech Wukong v2 board