microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Benjamin Herrenschmidt 6fe077910b litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		4 years ago
constraints	…
fpga	soc: Rework interconnect	4 years ago
hello_world	Makefile: Improve clean a bit	4 years ago
include	soc: Rework interconnect	4 years ago
lib	litedram: Update to new LiteX/LiteDRAM version	4 years ago
litedram	litedram: Add simulation support	4 years ago
media	…
micropython	…
openocd	flash-arty: Add support for specifying the file type	4 years ago
rust_lib_demo	console: Move console files	4 years ago
scripts	bin2hex: Make sure to generate little endian files	4 years ago
sim-unisim	…
tests	soc: Rework interconnect	4 years ago
verilator	Pass clock frequency to UART sim wrapper	4 years ago
.gitignore	…
.travis.yml	…
LICENSE	…
Makefile	litedram: Add simulation support	4 years ago
README.md	Add Makefile command line variables to enable docker and podman	4 years ago
cache_ram.vhdl	dcache: Rework RAM wrapper to synthetize better on Xilinx	4 years ago
common.vhdl	irq: Simplify xics->core irq input	4 years ago
control.vhdl	…
core.vhdl	irq: Simplify xics->core irq input	4 years ago
core_debug.vhdl	…
core_dram_tb.vhdl	litedram: Add simulation support	4 years ago
core_tb.vhdl	soc: Rework interconnect	4 years ago
countzero.vhdl	…
countzero_tb.vhdl	Exit cleanly from testbench on success	4 years ago
cr_file.vhdl	…
cr_hazard.vhdl	…
crhelpers.vhdl	…
dcache.vhdl	dcache: Rework RAM wrapper to synthetize better on Xilinx	4 years ago
dcache_tb.vhdl	Exit cleanly from testbench on success	4 years ago
decode1.vhdl	MMU: Implement reading of the process table	4 years ago
decode2.vhdl	…
decode_types.vhdl	Add TLB to icache	4 years ago
divider.vhdl	…
divider_tb.vhdl	Exit cleanly from testbench on success	4 years ago
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	…
execute1.vhdl	irq: Simplify xics->core irq input	4 years ago
fetch1.vhdl	Merge branch 'mmu'	4 years ago
fetch2.vhdl	Merge branch 'mmu'	4 years ago
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
gpr_hazard.vhdl	…
helpers.vhdl	…
icache.vhdl	dcache: Rework RAM wrapper to synthetize better on Xilinx	4 years ago
icache_tb.vhdl	Exit cleanly from testbench on success	4 years ago
icache_test.bin	…
insn_helpers.vhdl	…
loadstore1.vhdl	MMU: Implement reading of the process table	4 years ago
logical.vhdl	…
microwatt.core	Merge branch 'mmu'	4 years ago
mmu.vhdl	MMU: Implement reading of the process table	4 years ago
multiply.vhdl	…
multiply_tb.vhdl	Exit cleanly from testbench on success	4 years ago
plru.vhdl	…
plru_tb.vhdl	Exit cleanly from testbench on success	4 years ago
ppc_fx_insns.vhdl	…
register_file.vhdl	…
rotator.vhdl	…
rotator_tb.vhdl	Exit cleanly from testbench on success	4 years ago
sim_bram.vhdl	…
sim_bram_helpers.vhdl	…
sim_bram_helpers_c.c	…
sim_console.vhdl	…
sim_console_c.c	…
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	…
sim_uart.vhdl	…
sim_vhpi_c.c	…
sim_vhpi_c.h	…
soc.vhdl	irq: Simplify xics->core irq input	4 years ago
syscon.vhdl	soc: Rework interconnect	4 years ago
utils.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_bram_tb.bin	…
wishbone_bram_tb.vhdl	Exit cleanly from testbench on success	4 years ago
wishbone_bram_wrapper.vhdl	…
wishbone_debug_master.vhdl	…
wishbone_types.vhdl	soc: Rework interconnect	4 years ago
writeback.vhdl	…
xics.vhdl	irq: Simplify xics->core irq input	4 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)