microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Paul Mackerras 3cd3449b4b core: Move redirect and interrupt delivery logic to writeback This moves the logic for redirecting fetching and writing SRR0 and SRR1 to writeback. The aim is that ultimately units other than execute1 can send their interrupts to writeback along with their instruction completions, so that there can be multiple instructions in flight without needing execute1 to keep track of the address of each outstanding instruction. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		4 years ago
.github/workflows	…
constraints	…
fpga	fetch1: Implement a simple branch target cache	4 years ago
hello_world	…
include	…
lib	…
litedram	…
liteeth	…
media	…
micropython	…
openocd	…
rust_lib_demo	…
scripts	decode: Add a facility field to the instruction decode tables	4 years ago
sim-unisim	…
tests	tests: Add tests for lq/stq and lqarx/stqcx.	4 years ago
uart16550	…
verilator	…
.gitignore	…
LICENSE	…
Makefile	core: Track CR hazards and bypasses using tags	4 years ago
README.md	…
cache_ram.vhdl	…
common.vhdl	core: Move redirect and interrupt delivery logic to writeback	4 years ago
control.vhdl	core: Move redirect and interrupt delivery logic to writeback	4 years ago
core.vhdl	core: Move redirect and interrupt delivery logic to writeback	4 years ago
core_debug.vhdl	core_debug: Stop logging 256 cycles after trigger	4 years ago
core_dram_tb.vhdl	…
core_flash_tb.vhdl	…
core_tb.vhdl	…
countzero.vhdl	…
countzero_tb.vhdl	…
cr_file.vhdl	…
crhelpers.vhdl	…
dcache.vhdl	loadstore1/dcache: Send store data one cycle later	4 years ago
dcache_tb.vhdl	…
decode1.vhdl	core: Track CR hazards and bypasses using tags	4 years ago
decode2.vhdl	execute1: Move CR result to data path process	4 years ago
decode_types.vhdl	core: Crack update-form loads into two internal ops	4 years ago
divider.vhdl	…
divider_tb.vhdl	…
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	Reset JTAG/DMI	4 years ago
dram_tb.vhdl	…
execute1.vhdl	core: Move redirect and interrupt delivery logic to writeback	4 years ago
fetch1.vhdl	core: Move redirect and interrupt delivery logic to writeback	4 years ago
fpu.vhdl	core: Track GPR hazards using tags that propagate through the pipelines	4 years ago
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
helpers.vhdl	…
icache.vhdl	fetch1: Implement a simple branch target cache	4 years ago
icache_tb.vhdl	…
icache_test.bin	…
insn_helpers.vhdl	core: Implement quadword loads and stores	4 years ago
loadstore1.vhdl	core: Track GPR hazards using tags that propagate through the pipelines	4 years ago
logical.vhdl	core: Make result multiplexing explicit	4 years ago
microwatt.core	core: Track CR hazards and bypasses using tags	4 years ago
mmu.vhdl	Initialize PID register	4 years ago
multiply.vhdl	…
multiply_tb.vhdl	…
nonrandom.vhdl	…
plru.vhdl	…
plru_tb.vhdl	…
ppc_fx_insns.vhdl	…
random.vhdl	…
register_file.vhdl	…
rotator.vhdl	…
rotator_tb.vhdl	…
sim_16550_uart.vhdl	…
sim_bram.vhdl	…
sim_bram_helpers.vhdl	…
sim_bram_helpers_c.c	…
sim_console.vhdl	…
sim_console_c.c	…
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	…
sim_no_flash.vhdl	…
sim_pp_uart.vhdl	…
sim_vhpi_c.c	…
sim_vhpi_c.h	…
soc.vhdl	fetch1: Implement a simple branch target cache	4 years ago
spi_flash_ctrl.vhdl	…
spi_rxtx.vhdl	Merge pull request #265 from antonblanchard/another-spi-rxtx-reset-issu	4 years ago
sync_fifo.vhdl	…
syscon.vhdl	…
utils.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_bram_tb.bin	…
wishbone_bram_tb.vhdl	…
wishbone_bram_wrapper.vhdl	…
wishbone_debug_master.vhdl	…
wishbone_types.vhdl	Make wishbone_master_out and wb_io_master_out match	4 years ago
writeback.vhdl	core: Move redirect and interrupt delivery logic to writeback	4 years ago
xics.vhdl	…
xilinx-mult.vhdl	…

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)