microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Paul Mackerras 29221315e9 core: Send loadstore1 interrupts to writeback rather than execute1 Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		4 years ago
.github/workflows	ci: use job.container	4 years ago
constraints	Initial support for ghdl synthesis	5 years ago
fpga	fetch1: Implement a simple branch target cache	4 years ago
hello_world	Reduce hello_world footprint to fit in 8kB	4 years ago
include	syscon: Add flag to indicate the timebase frequency	5 years ago
lib	console: Add support for the 16550 UART	5 years ago
litedram	fpga: Add support for Genesys2	4 years ago
liteeth	liteeth: Hook up LiteX LiteEth ethernet controller	5 years ago
media	Add title image	5 years ago
micropython	tests: Add updated micropython build with 16550 support	5 years ago
openocd	flash-arty: update error message (#203 )	5 years ago
rust_lib_demo	console: Cleanup console API	5 years ago
scripts	decode: Add a facility field to the instruction decode tables	4 years ago
sim-unisim	Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs	5 years ago
tests	tests: Add tests for lq/stq and lqarx/stqcx.	4 years ago
uart16550	Add uart16550 files from fusesoc	5 years ago
verilator	Pass clock frequency to UART sim wrapper	5 years ago
.gitignore	Add yosys builds files to gitignore	5 years ago
LICENSE	Initial import of microwatt	5 years ago
Makefile	core: Track CR hazards and bypasses using tags	4 years ago
README.md	Add Makefile command line variables to enable docker and podman	5 years ago
cache_ram.vhdl	dcache: Rework RAM wrapper to synthetize better on Xilinx	5 years ago
common.vhdl	core: Send loadstore1 interrupts to writeback rather than execute1	4 years ago
control.vhdl	core: Move redirect and interrupt delivery logic to writeback	4 years ago
core.vhdl	core: Move redirect and interrupt delivery logic to writeback	4 years ago
core_debug.vhdl	core_debug: Stop logging 256 cycles after trigger	4 years ago
core_dram_tb.vhdl	litedram: l2: Add support for more geometries	5 years ago
core_flash_tb.vhdl	soc: Don't require dram wishbones signals to be wired by toplevel	5 years ago
core_tb.vhdl	soc: Don't require dram wishbones signals to be wired by toplevel	5 years ago
countzero.vhdl	core: Add support for single-precision FP loads and stores	4 years ago
countzero_tb.vhdl	Exit cleanly from testbench on success	5 years ago
cr_file.vhdl	core: Don't generate logic for log data when LOG_LENGTH = 0	5 years ago
crhelpers.vhdl	crhelpers: Constraint "crnum" integer	5 years ago
dcache.vhdl	loadstore1/dcache: Send store data one cycle later	4 years ago
dcache_tb.vhdl	Exit cleanly from testbench on success	5 years ago
decode1.vhdl	core: Track CR hazards and bypasses using tags	4 years ago
decode2.vhdl	execute1: Move CR result to data path process	4 years ago
decode_types.vhdl	core: Crack update-form loads into two internal ops	4 years ago
divider.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
divider_tb.vhdl	Exit cleanly from testbench on success	5 years ago
dmi_dtm_dummy.vhdl	Fix build issue in dmi_dtm_dummy.vhdl	5 years ago
dmi_dtm_tb.vhdl	ram: Rework main RAM interface	5 years ago
dmi_dtm_xilinx.vhdl	Reset JTAG/DMI	4 years ago
dram_tb.vhdl	litedram: l2: Add support for more geometries	5 years ago
execute1.vhdl	core: Send loadstore1 interrupts to writeback rather than execute1	4 years ago
fetch1.vhdl	core: Move redirect and interrupt delivery logic to writeback	4 years ago
fpu.vhdl	core: Track GPR hazards using tags that propagate through the pipelines	4 years ago
glibc_random.vhdl	Reformat glibc_random	5 years ago
glibc_random_helpers.vhdl	Reformat glibc_random	5 years ago
helpers.vhdl	core: Add support for single-precision FP loads and stores	4 years ago
icache.vhdl	fetch1: Implement a simple branch target cache	4 years ago
icache_tb.vhdl	core: Remove fetch2 pipeline stage	5 years ago
icache_test.bin	icache_tb: Improve test and include test file	5 years ago
insn_helpers.vhdl	core: Implement quadword loads and stores	4 years ago
loadstore1.vhdl	core: Send loadstore1 interrupts to writeback rather than execute1	4 years ago
logical.vhdl	core: Make result multiplexing explicit	4 years ago
microwatt.core	core: Track CR hazards and bypasses using tags	4 years ago
mmu.vhdl	Initialize PID register	4 years ago
multiply.vhdl	execute1: Take an extra cycle for OE=1 multiply instructions	4 years ago
multiply_tb.vhdl	multiplier: Generalize interface to the multiplier	4 years ago
nonrandom.vhdl	Add random number generator and implement the darn instruction	4 years ago
plru.vhdl	plru: Improve sensitivity list	5 years ago
plru_tb.vhdl	Exit cleanly from testbench on success	5 years ago
ppc_fx_insns.vhdl	core: Implement the cmpeqb and cmprb instructions	4 years ago
random.vhdl	Add random number generator and implement the darn instruction	4 years ago
register_file.vhdl	core: Add support for floating-point loads and stores	4 years ago
rotator.vhdl	Implement the extswsli instruction	5 years ago
rotator_tb.vhdl	Exit cleanly from testbench on success	5 years ago
sim_16550_uart.vhdl	uart: Add a simulation model for the 16550 compatible UART	5 years ago
sim_bram.vhdl	ram: Rework main RAM interface	5 years ago
sim_bram_helpers.vhdl	ram: Rework main RAM interface	5 years ago
sim_bram_helpers_c.c	Consolidate VHPI code	5 years ago
sim_console.vhdl	Reformat sim_console	5 years ago
sim_console_c.c	sim_console: Fix polling to check for POLLIN	5 years ago
sim_jtag.vhdl	Add jtag support in simulation via a socket	5 years ago
sim_jtag_socket.vhdl	Add jtag support in simulation via a socket	5 years ago
sim_jtag_socket_c.c	Consolidate VHPI code	5 years ago
sim_no_flash.vhdl	spi: Add simulation support	5 years ago
sim_pp_uart.vhdl	uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl	5 years ago
sim_vhpi_c.c	Consolidate VHPI code	5 years ago
sim_vhpi_c.h	Consolidate VHPI code	5 years ago
soc.vhdl	fetch1: Implement a simple branch target cache	4 years ago
spi_flash_ctrl.vhdl	Fix an issue in flash controller when BOOT_CLOCKS is false	4 years ago
spi_rxtx.vhdl	Merge pull request #265 from antonblanchard/another-spi-rxtx-reset-issu	4 years ago
sync_fifo.vhdl	litedram: Add an L2 cache with store queue	5 years ago
syscon.vhdl	syscon: Add flag to indicate the timebase frequency	5 years ago
utils.vhdl	litedram: Add support for booting without BRAM	5 years ago
wishbone_arbiter.vhdl	wb_arbiter: Early master selection	5 years ago
wishbone_bram_tb.bin	ram: Rework main RAM interface	5 years ago
wishbone_bram_tb.vhdl	Exit cleanly from testbench on success	5 years ago
wishbone_bram_wrapper.vhdl	Add log2ceil and use it in bram code	5 years ago
wishbone_debug_master.vhdl	wishbone_debug_master: Fix address auto-increment for memory writes	5 years ago
wishbone_types.vhdl	Make wishbone_master_out and wb_io_master_out match	4 years ago
writeback.vhdl	core: Send loadstore1 interrupts to writeback rather than execute1	4 years ago
xics.vhdl	xics: Add support for reduced priority field size	5 years ago
xilinx-mult.vhdl	execute1: Take an extra cycle for OE=1 multiply instructions	4 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)