FPU: Make FPSCR bit 11 always read as 0

Bit 11 (52 in BE numbering) is a reserved bit.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

fpu.vhdl

@@ -1323,7 +1323,7 @@ begin
         opsel_s <= S_ZERO;
         misc_sel <= "000";
         opsel_sel <= AIN_ZERO;
-        fpscr_mask := (others => '1');
+        fpscr_mask := x"FFFFF7FF";      -- ignore bit 11 (52 BE), it's reserved
         cr_op := CROP_NONE;
         update_fx := '0';
         arith_done := '0';
@@ -1428,7 +1428,7 @@ begin
                         fpscr_mask(k + 3 downto k) := "0000";
                     end if;
                 end loop;
-                v.fpscr := r.fpscr and (fpscr_mask or x"6007F8FF");
+                v.fpscr := r.fpscr and (fpscr_mask or x"6007F0FF");
                 v.instr_done := '1';
 
             when DO_FTDIV =>

tests/fpu/fpu.c

@@ -274,6 +274,7 @@ void set_fpscr(unsigned long fpscr)
 unsigned long fpscr_eval(unsigned long val)
 {
 	val &= ~0x60000000;	/* clear FEX and VX */
+	val &= ~0x00000800;	/* clear reserved bit 52 (BE) */
 	if (val & 0x1f80700)	/* test all VX* bits */
 		val |= 0x20000000;
 	if ((val >> 25) & (val >> 3) & 0x1f)