genesys2: Fix SPI_FLASH_OFFSET (#449)

Signed-off-by: Boris Shingarov <shingarov@labware.com>

fpga/top-genesys2.vhdl

@@ -17,7 +17,7 @@ entity toplevel is
 	USE_LITEDRAM  : boolean  := false;
 	NO_BRAM       : boolean  := false;
 	DISABLE_FLATTEN_CORE : boolean := false;
-        SPI_FLASH_OFFSET   : integer := 10485760;
+        SPI_FLASH_OFFSET   : integer := 12582912;
         SPI_FLASH_DEF_CKDV : natural := 1;
         SPI_FLASH_DEF_QUAD : boolean := true;
         LOG_LENGTH         : natural := 2048;

microwatt.core

@@ -185,7 +185,7 @@ targets:
       - use_litedram=false
       - no_bram=false
       - disable_flatten_core
-      - spi_flash_offset=10485760
+      - spi_flash_offset=12582912
       - log_length=2048
       - uart_is_16550=false
     generate: [git_hash]
@@ -222,7 +222,7 @@ targets:
       - use_litedram=true
       - disable_flatten_core
       - no_bram
-      - spi_flash_offset=10485760
+      - spi_flash_offset=12582912
       - log_length=2048
       - uart_is_16550=false
     generate: [litedram_genesys2, git_hash]