Make a few changes to match what mw_debug expects:
- 6 byte instructions
- IDCODE at 001001
- microwatt debug at 000011
Also change IDCODE to be an IBM ID.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
The verilator simulation interface uses the remote_bitbang
protocol from openocd. I have a simple implementation for
urjtag too.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This fixes a bug in the BTC where entries created for a given address
when MSR[IR] = 0 are used when MSR[IR] = 1 and vice-versa. The fix is
to include r.virt_mode (which mirrors MSR[IR]) in the tag portion of
the BTC.
Fixes: 0fb207be60 ("fetch1: Implement a simple branch target cache", 2020-12-19)
Reported-by: Anton Blanchard <anton@linux.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This fixes a bug which causes a trace interrupt to store the wrong
value in SRR0 in the case where the instruction that has just
completed is followed by a sc (system call) instruction. What happens
is that first the traced instruction sets ex1.trace_next. Then, when
the sc instruction following it comes in, the execute1_actions process
sets v.e.last_nia to next_nia because it is an sc instruction, even
though it is not going to be executed -- we are going to take the
trace interrupt instead. Then when the trace interrupt is taken, we
incorrectly set SRR0 to the incremented address (the address of the
instruction following the sc).
To fix this, we have execute1_actions set a new flag if the current
instruction is sc, and only set v.e.last_nia to next_nia if we
actually execute the sc (in the "if go = '1'" case).
Fixes: 813e2317bf ("execute1: Restructure to separate out execution of side effects", 2022-06-18)
Reported-by: Anton Blanchard <anton@linux.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
xics.vhdl:83:25⚠️ declaration of "v" hides variable "v" [-Whide]
function bswap(v : in std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
xics.vhdl:84:22⚠️ declaration of "r" hides signal "r" [-Whide]
variable r : std_ulogic_vector(31 downto 0);
Signed-off-by: Joel Stanley <joel@jms.id.au>
fpu.vhdl:513:18⚠️ declaration of "result" hides signal "result" [-Whide]
variable result : std_ulogic_vector(63 downto 0);
Signed-off-by: Joel Stanley <joel@jms.id.au>
Regenerate from upstream litex. Something in the update has improved
memory read and write performance quite a lot on my Nexys Video:
Before:
Write speed: 83.2MiB/s
Read speed: 140.4MiB/s
After:
Write speed: 352.1MiB/s
Read speed: 218.5MiB/s
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Fix the litex generate script to pass frequencies in Hz. Regenerate
the litesdcard Verilog for both Xilinx and Lattice. This fixes
litesdcard on my Nexys Video.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Building the mw_debug program leaves build artifacts in
microwatt/scripts/mw_debug
causing noise in the output of `git status`.
This commit adds them to .gitignore.
Signed-off-by: Boris Shingarov <shingarov@labware.com>
The following commit added two tests but didn't update the tests
outputs:
commit 73cc5167ec
Author: Paul Mackerras <paulus@ozlabs.org>
Date: Mon May 9 19:18:42 2022 +1000
Use FPU for division instructions if we have an FPU
This patch updates these using tests/update_console_tests
Signed-off-by: Michael Neuling <mikey@neuling.org>
This improves timing a little because the register addresses now come
directly from a latch instead of being calculated by
decode_input_reg_*. The asserts that check that the two are the same
are now in decode2 rather than register_file.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard
