Commit Graph

89 Commits (bf36ea365b9998f5cf8e1cb082fc1d8c78cb6721)

Author SHA1 Message Date
Michael Neuling 5aaa63ee3b Add PLL for ECP5 device
Means we can synthesize at 40Mhz (where we currently make timing) and
our UART still works at 115200 baud.

Tested working hello world unmodified with ECP5 eval board. Orange
Crab is updated but is untested.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Anton Blanchard 4e977bf8a9
Merge pull request #220 from mikey/ghdl-makefile
Use $(GHDL) rather than ghdl in Makefile
4 years ago
Michael Neuling 1697f8a08f Use $(GHDL) rather than ghdl in Makefile
Suggestion from @eine in PR #219.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 10a1a86ba0 Add FPGA_TARGET=ECP5-EVN make option for synthesis build
This allows these targets
  FPGA_TARGET=ORANGE-CRAB make microwatt.bit
  FPGA_TARGET=ECP5-EVN make microwatt.bit
Default is ORANGE-CRAB as before

ECP5-EVN is tested on real hardware. The console only works at 38400 so
needs this in console.c and a recompile of hello_world to work:

  -#define UART_FREQ 115200
  +#define UART_FREQ 38400

With this 'FPGA_TARGET=ECP5-EVN make prog' works on the ECP5 dev board.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling ef0dcf3bc6 Add SYNTH_ECP5_FLAGS option for building
This is useful to specify "-noflatten" which helps CI stay under 8GB
limit.

Normally the AUTONAME stage of yosys will take around 10GB if
operating on the whole design. With -noflatten, AUTONAME occurs only
per VHDL entity, so only consumes around 3GB of memory. This gets us
under the limitations on github actions.

More discussion here:
  https://github.com/antonblanchard/microwatt/pull/209#issuecomment-652186078

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 45fd2354f2 Add ram file to synthesis build dependencies
Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 7347786b08 Add uart16550 files to yosys/nextpnr build
These are verilog so need passed to yosys differently than the VHDL
files.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 3f6d48f2fc Build to tmp file so nextpnr errors don't confuse make
nextpnr will leave an output file around even when it errors out, so
build to a tmp file and move it when we succeed so we don't confuse
make.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 3e0ac8c94c Fix building with yosys/nextpnr
Add --no-formal so that asserts are removed by yosys as nextpnr
doesn't like them.

This was suggested by @tgingold here:
  https://github.com/YosysHQ/yosys/issues/2068#issuecomment-644545863

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Benjamin Herrenschmidt cc10f6b289 uart: Add a simulation model for the 16550 compatible UART
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 4eae29801b uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Paul Mackerras b5a7dbb78d core: Remove fetch2 pipeline stage
The fetch2 stage existed primarily to provide a stash buffer for the
output of icache when a stall occurred.  However, we can get the same
effect -- of having the input to decode1 stay unchanged on a stall
cycle -- by using the read enable of the BRAMs in icache, and by
adding logic to keep the outputs unchanged on a clock cycle when
stall_in = 1.  This reduces branch and interrupt latency by one
cycle.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Benjamin Herrenschmidt a89e1469ef spi: Add simulation support
This require the s25fl128s.vhd flash model and FMF libraries,
which will be built when passed to the Makefile via the
FLASH_MODEL_PATH argument. Otherwise a dummy module is used
which ties MISO to '1'.

The model isn't included as I'm not sure its licence (GPL) is
at this point, but it can be obtained from

https://github.com/ozbenh/microspi

FLASH_MODEL_PATH=<path to microspi>/model

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 097d19fd32 Makefile: Improve unisim library generation
The rewrite of the Makefile to use "ghdl -c" somewhat broke building
the unisim library as ghdl doesn't yet support putting files in
separate libraries from a single command line invocation.

The workaround at the time was to put the entire project in "unisim"
which is ... weird and will break if we try to add another library
such as fmf.

This fixes it by generating the library separately using "ghdl -i"

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Michael Neuling 6323f27423 Add unit tests to check and check_light
Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 809933a567 Add unit tests make target
We don't run these but we should.

The SOC tests have bit rotted. We need to fix them but leave them out
for now.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 560a6f6b18 Add tests_console make target
Will use when splitting out Travis tests later

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Benjamin Herrenschmidt 599fad117b litedram: Remove old "VexRiscV" based initializations
Support for this has bitrotted and would require refactoring of L2 to
be brought back. It's also not really needed anymore now that we ship
pre-generated litedram and that LiteX supports what we do.

So take it out, which simplifies some of the scripts as well. This also
fixes up CSR alignment the sim model.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 6828e93113 litedram: Test bench
The test bench test simple access forms for now, it's a starting point
but it already helped find/fix a bug.

Includes a litedram update to be able to operate the sim model without
inits.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt a3857aac94 litedram: Add an L2 cache with store queue
This adds a cache between the wishbone and litedram with the following
features (at this point, it's still evolving)

  - 128 bytes line width in order to have a reasonable amount of
litedram pipelining on the 128-bit wide data port.

  - Configurable geometry otherwise

  - Stores are acked immediately on wishbone whether hit or miss
(minus a 2 cycles delay if there's a previous load response in the
way) and sent to LiteDRAM via 8 entries (configurable) store queue

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 6fe077910b litedram: Add simulation support
This adds a simulated litedram model along with the necessary
Makefile gunk to verilate it and wrap it for use by ghdl.

The core_dram_tb test bench is a variant of core_tb with
LiteDRAM simulated. It's not built by default, an explicit

make core_dram_tb

is necessary as to not require verilator to be installed for
the normal build process (also it's slow'ish).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Anton Blanchard 04c56a0c52 Pass clock frequency to UART sim wrapper
The UART sim wrapper is currently hard wired to 50 MHz.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 7b14819dbb A little less shouting in the Makefile
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 01da807476 Fix the simulated DMI
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard a9e7194de5 Merge Makefile and Makefile.synth
We still need to a way to our FPGA target on the command line, but this
at least gets us down to a common Makefile.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 6326efaca4 Add Makefile command line variables to enable docker and podman
Instead of having to edit the Makefile, we can now do:

make DOCKER=1
make PODMAN=1

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 224e7734a8 Rework Makefile
Instead of building each file one by one (and having to track all
the dependencies manually), use the ghdl -c command that does
analysis and elaboration in one go.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 4e78b8078e
Merge branch 'master' into litedram 4 years ago
Benjamin Herrenschmidt 803ee9ef35 Makefile: Improve clean a bit
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Paul Mackerras c164a2f4ea Merge branch 'mmu'
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Benjamin Herrenschmidt 025cf5efe8 syscon: Add syscon registers
These provides some info about the SoC (though it's still somewhat
incomplete and needs more work, see comments).

There's also a control register for selecting DRAM vs. BRAM at 0
(and for soft-resetting the SoC but that isn't wired up yet).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Paul Mackerras 8160f4f821 Add framework for implementing an MMU
This adds a new module to implement an MMU.  At the moment it doesn't
do very much.  Tlbie instructions now get sent by loadstore1 to mmu,
which sends them to dcache, rather than loadstore1 sending them
directly to dcache.  TLB misses from dcache now get sent by loadstore1
to mmu, which currently just returns an error.  Loadstore1 then
generates a DSI in response to the error return from mmu.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Benjamin Herrenschmidt 982cf166dd litedram: Add basic support for LiteX LiteDRAM
This comes in two parts:

 - A generator script which uses LiteX to generate litedram cores
along with their init files for various boards (currently Arty and
Nexys-video). This comes with configs for arty and nexys_video.

 - A fusesoc "generator" which uses pre-generated litedram cores

The generation process is manual on purpose. This include pre-generated
cores for the two above boards.

This is done so that one doesn't have to install LiteX to build
microwatt. In addition, the generator script or wrapper vhdl tend to
break when LiteX changes significantly which happens.

This is still rather standalone and hasn't been plumbed into the SoC
or the FPGA toplevel files yet.

At this point LiteDRAM self-initializes using a built-in VexRiscv
"Minimum" core obtained from LiteX and included in this commit. There
is some plumbing to generate and cores that are initialized by Microwatt
directly but this isn't working yet and so isn't enabled yet.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Paul Mackerras 102b304db7 Merge remote-tracking branch 'remotes/origin/master' 4 years ago
Anton Blanchard 4160f2138d
Merge pull request #165 from mikey/xics
Implement XICS compliant interrupt controller
4 years ago
Paul Mackerras a05ee9fc7f Makefile: fix typo
Fix a typo which meant that the console tests weren't getting
executed by 'make check'.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 167e37d667 Plumb insn_type through to loadstore1
In preparation for adding a TLB to the dcache, this plumbs the
insn_type from execute1 through to loadstore1, so that we can have
other operations besides loads and stores (e.g. tlbie) going to
loadstore1 and thence to the dcache.  This also plumbs the unit field
of the decode ROM from decode2 through to execute1 to simplify the
logic around which ops need to go to loadstore1.

The load and store data formatting are now not conditional on the
op being OP_LOAD or OP_STORE.  This eliminates the inferred latches
clocked by each of the bits of r.op that we were getting previously.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Michael Neuling b4f20c20b9 XICS interrupt controller
New unified ICP and ICS XICS compliant interrupt controller.
Configurable number of hardware sources.

Fixed hardware source number based on hardware line taken. All
hardware interrupts are a fixed priority. Level interrupts supported
only.

Hardwired to 0xc0004000 in SOC (UART is kept at 0xc0002000).

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling ff162e42eb Add VHDL TAGS
Adds `make TAGS`

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 9d7df2d507 Add test cases for new exceptions and supervisor state
This adds test cases for:
- sc, illegals and decrementer exceptions
- decrementer overflow
- rfid
- mt/mf sprg0/1 srr0/1
- mtdec
- mtmsrd
- sc

It also adds these test cases to make check/check_light

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Dan Horák ab50c7710d make the sources volume mount SELinux friendly
Signed-off-by: Dan Horák <dan@danny.cz>
5 years ago
Anton Blanchard 471c7e2197 Consolidate VHPI code
We had many copies of the VHPI marshalling/unmarshalling code.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard f77b31a552
Merge pull request #134 from paulusmack/master
Add bypass from execute1 output to input
5 years ago
Anton Blanchard c18830a5e5 Add an option to use Docker
Some distros don't have a version of ghdl with the  LLVM or GCC backend,
so add a Docker image as an alternative.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard a4dbbfda4a Fix Makefile dependency issue with files in vhdl/*
GHDL doesn't seem to have a way to specify the location of the object
file it writes, so right now they are all ending up in the root
directory. The Makefile rules did not reflect that, so make would
continually the files in fpga/*

Fix the rules to match what GHDL is doing.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Paul Mackerras 39d18d2738 Make divider hang off the side of execute1
With this, the divider is a unit that execute1 sends operands to and
which sends its results back to execute1, which then send them to
writeback.  Execute1 now sends a stall signal when it gets a divide
or modulus instruction until it gets a valid signal back from the
divider.  Divide and modulus instructions are no longer marked as
single-issue.

The data formatting step that used to be done in decode2 for div
and mod instructions is now done in execute1.  We also do the
absolute value operation in that same cycle instead of taking an
extra cycle inside the divider for signed operations with a
negative operand.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras 2167186b5f Make multiplier hang off the side of execute1
With this, the multiplier isn't a separate pipe that decode2 issues
instructions to, but rather is a unit that execute1 sends operands
to and which sends the result back to execute1, which then sends it
to writeback.  Execute1 now sends a stall signal when it gets a
multiply instruction until it gets a valid signal back from the
multiplier.

This all means that we no longer need to mark the multiply
instructions as single-issue.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Benjamin Herrenschmidt e4f475e17f sprs: Store common SPRs in register file
This stores the most common SPRs in the register file.

This includes CTR and LR and a not yet final list of others.

The register file is set to 64 entries for now. Specific types
are defined that can represent a GPR index (gpr_index_t) or
a GPR/SPR index (gspr_index_t) along with conversion functions
between the two.

On order to deal with some forms of branch updating both LR and
CTR, we introduced a delayed update of LR after a branch link.

Note: We currently stall the pipeline on such a delayed branch,
but we could avoid stalling fetch in that specific case as we
know we have a branch delay. We could also limit that to the
specific case where we need to update both CTR and LR.

This allows us to make bcreg, mtspr and mfspr pipelined. decode1
will automatically force the single issue flag on mfspr/mtspr to
a "slow" SPR.

[paulus@ozlabs.org - fix direction of decode2.stall_in]

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Benjamin Herrenschmidt 8e0389b973 ram: Rework main RAM interface
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 9a63c098a5 Move log2/ispow2 to a utils package
(Out of icache and dcache)


Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago