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caravel-mpw7-20221125
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trace-test
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litedram-update
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fix-sdcard
fpu-init
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
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boxarty-20211011
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remove-potato-uart
cache-tlb-parameters-2
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jtag-port-2
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nia-debug
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2 Commits (6c3a8bf4171173c87d694d6721464c8e2f6423a6)

Author SHA1 Message Date
Anton Blanchard ab86b58d95 Exit cleanly from testbench on success 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Benjamin Herrenschmidt 8e0389b973 ram: Rework main RAM interface 
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago