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caravel-mpw7-20221125
caravel-mpw7-20220822
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trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
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core_debug-init
icache-unused-sig
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fpu-typo
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caravel-mpw6-20220530
caravel-mpw5-20220323
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
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caravel-20210105
jtag-port-2
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nia-debug
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3 Commits (65c43b488bff9157d2a9e83ba6ce5b851604536a)

Author SHA1 Message Date
Anton Blanchard 21f482f967 Reformat testbenches 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard ab86b58d95 Exit cleanly from testbench on success 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Benjamin Herrenschmidt 8e0389b973 ram: Rework main RAM interface 
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago