litedram: Add simulation support
This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>pull/190/head
Benjamin Herrenschmidt
5 years ago
parent
42e138e539
commit
6fe077910b
@ -0,0 +1,114 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity core_dram_tb is
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end core_dram_tb;
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architecture behave of core_dram_tb is
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signal clk, rst: std_logic;
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signal system_clk, soc_rst : std_ulogic;
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-- testbench signals
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constant clk_period : time := 10 ns;
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-- Sim DRAM
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signal wb_dram_in : wishbone_master_out;
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signal wb_dram_out : wishbone_slave_out;
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signal wb_dram_ctrl_in : wb_io_master_out;
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signal wb_dram_ctrl_out : wb_io_slave_out;
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signal wb_dram_is_csr : std_ulogic;
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signal wb_dram_is_init : std_ulogic;
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signal core_alt_reset : std_ulogic;
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begin
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soc0: entity work.soc
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generic map(
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SIM => true,
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MEMORY_SIZE => (384*1024),
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RAM_INIT_FILE => "main_ram.bin",
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RESET_LOW => false,
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HAS_DRAM => true,
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DRAM_SIZE => 256 * 1024 * 1024,
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CLK_FREQ => 100000000
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)
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port map(
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rst => soc_rst,
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system_clk => system_clk,
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uart0_rxd => '0',
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uart0_txd => open,
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wb_dram_in => wb_dram_in,
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wb_dram_out => wb_dram_out,
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wb_dram_ctrl_in => wb_dram_ctrl_in,
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wb_dram_ctrl_out => wb_dram_ctrl_out,
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wb_dram_is_csr => wb_dram_is_csr,
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wb_dram_is_init => wb_dram_is_init,
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alt_reset => core_alt_reset
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);
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dram: entity work.litedram_wrapper
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generic map(
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DRAM_ABITS => 24,
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DRAM_ALINES => 1
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)
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port map(
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clk_in => clk,
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rst => rst,
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system_clk => system_clk,
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system_reset => soc_rst,
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core_alt_reset => core_alt_reset,
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pll_locked => open,
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wb_in => wb_dram_in,
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wb_out => wb_dram_out,
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wb_ctrl_in => wb_dram_ctrl_in,
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wb_ctrl_out => wb_dram_ctrl_out,
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wb_ctrl_is_csr => wb_dram_is_csr,
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wb_ctrl_is_init => wb_dram_is_init,
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serial_tx => open,
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serial_rx => '1',
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init_done => open,
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init_error => open,
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ddram_a => open,
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ddram_ba => open,
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ddram_ras_n => open,
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ddram_cas_n => open,
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ddram_we_n => open,
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ddram_cs_n => open,
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ddram_dm => open,
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ddram_dq => open,
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ddram_dqs_p => open,
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ddram_dqs_n => open,
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ddram_clk_p => open,
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ddram_clk_n => open,
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ddram_cke => open,
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ddram_odt => open,
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ddram_reset_n => open
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);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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rst_process: process
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begin
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rst <= '1';
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wait for 10*clk_period;
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rst <= '0';
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wait;
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end process;
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jtag: entity work.sim_jtag;
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end;
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@ -0,0 +1,10 @@
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OPT_FAST=-O3 -fstrict-aliasing
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OPT_SLOW=-O3 -fstrict-aliasing
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top_all: top_all2
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include Vlitedram_core.mk
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top_all2: default $(VK_GLOBAL_OBJS)
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.PHONY: top_all top_all2
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@ -0,0 +1,214 @@
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library ieee;
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use ieee.std_logic_1164.all;
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package sim_litedram is
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-- WB req format:
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-- 73 .. 71 : cti(2..0)
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-- 70 .. 69 : bte(1..0)
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-- 68 .. 65 : sel(3..0)
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-- 64 : we
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-- 63 : stb
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-- 62 : cyc
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-- 61 .. 32 : addr(29..0)
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-- 31 .. 0 : write_data(31..0)
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--
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procedure litedram_set_wb(req : in std_ulogic_vector(73 downto 0));
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attribute foreign of litedram_set_wb : procedure is "VHPIDIRECT litedram_set_wb";
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-- WB rsp format:
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-- 35 : init_error;
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-- 34 : init_done;
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-- 33 : err
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-- 32 : ack
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-- 31 .. 0 : read_data(31..0)
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--
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procedure litedram_get_wb(rsp : out std_ulogic_vector(35 downto 0));
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attribute foreign of litedram_get_wb : procedure is "VHPIDIRECT litedram_get_wb";
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-- User req format:
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-- 171 : cmd_valid
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-- 170 : cmd_we
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-- 169 : wdata_valid
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-- 168 : rdata_ready
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-- 167 .. 144 : cmd_addr(23..0)
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-- 143 .. 128 : wdata_we(15..0)
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-- 127 .. 0 : wdata_data(127..0)
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--
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procedure litedram_set_user(req: in std_ulogic_vector(171 downto 0));
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attribute foreign of litedram_set_user : procedure is "VHPIDIRECT litedram_set_user";
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-- User rsp format:
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-- 130 : cmd_ready
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-- 129 : wdata_ready
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-- 128 : rdata_valid
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-- 127 .. 0 : rdata_data(127..0)
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procedure litedram_get_user(req: in std_ulogic_vector(130 downto 0));
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attribute foreign of litedram_get_user : procedure is "VHPIDIRECT litedram_get_user";
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procedure litedram_clock;
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attribute foreign of litedram_clock : procedure is "VHPIDIRECT litedram_clock";
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procedure litedram_init(trace: integer);
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attribute foreign of litedram_init : procedure is "VHPIDIRECT litedram_init";
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end sim_litedram;
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package body sim_litedram is
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procedure litedram_set_wb(req : in std_ulogic_vector(73 downto 0)) is
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begin
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assert false report "VHPI" severity failure;
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end procedure;
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procedure litedram_get_wb(rsp : out std_ulogic_vector(35 downto 0)) is
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begin
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assert false report "VHPI" severity failure;
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end procedure;
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procedure litedram_set_user(req: in std_ulogic_vector(171 downto 0)) is
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begin
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assert false report "VHPI" severity failure;
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end procedure;
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procedure litedram_get_user(req: in std_ulogic_vector(130 downto 0)) is
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begin
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assert false report "VHPI" severity failure;
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end procedure;
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procedure litedram_clock is
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begin
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assert false report "VHPI" severity failure;
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end procedure;
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procedure litedram_init(trace: integer) is
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begin
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assert false report "VHPI" severity failure;
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end procedure;
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end sim_litedram;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.sim_litedram.all;
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entity litedram_core is
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port(
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clk : in std_ulogic;
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rst : in std_ulogic;
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pll_locked : out std_ulogic;
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ddram_a : out std_ulogic_vector(0 downto 0);
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ddram_ba : out std_ulogic_vector(2 downto 0);
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ddram_ras_n : out std_ulogic;
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ddram_cas_n : out std_ulogic;
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ddram_we_n : out std_ulogic;
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ddram_cs_n : out std_ulogic;
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ddram_dm : out std_ulogic_vector(1 downto 0);
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ddram_dq : inout std_ulogic_vector(15 downto 0);
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ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
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ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
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ddram_clk_p : out std_ulogic;
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ddram_clk_n : out std_ulogic;
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ddram_cke : out std_ulogic;
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ddram_odt : out std_ulogic;
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ddram_reset_n : out std_ulogic;
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init_done : out std_ulogic;
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init_error : out std_ulogic;
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user_clk : out std_ulogic;
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user_rst : out std_ulogic;
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wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
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wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
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wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
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wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
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wb_ctrl_cyc : in std_ulogic;
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wb_ctrl_stb : in std_ulogic;
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wb_ctrl_ack : out std_ulogic;
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wb_ctrl_we : in std_ulogic;
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wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
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wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
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wb_ctrl_err : out std_ulogic;
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user_port_native_0_cmd_valid : in std_ulogic;
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user_port_native_0_cmd_ready : out std_ulogic;
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user_port_native_0_cmd_we : in std_ulogic;
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user_port_native_0_cmd_addr : in std_ulogic_vector(23 downto 0);
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user_port_native_0_wdata_valid : in std_ulogic;
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user_port_native_0_wdata_ready : out std_ulogic;
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user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0);
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user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0);
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user_port_native_0_rdata_valid : out std_ulogic;
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user_port_native_0_rdata_ready : in std_ulogic;
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user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0)
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);
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end entity litedram_core;
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architecture behaviour of litedram_core is
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signal idone : std_ulogic := '0';
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signal ierr : std_ulogic := '0';
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signal old_wb_cyc : std_ulogic := '1';
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begin
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user_rst <= rst;
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user_clk <= clk;
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pll_locked <= '1';
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init_done <= idone;
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init_error <= ierr;
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poll: process(user_clk)
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procedure send_signals is
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begin
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litedram_set_wb(wb_ctrl_cti & wb_ctrl_bte &
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wb_ctrl_sel & wb_ctrl_we &
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wb_ctrl_stb & wb_ctrl_cyc &
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wb_ctrl_adr & wb_ctrl_dat_w);
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litedram_set_user(user_port_native_0_cmd_valid &
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user_port_native_0_cmd_we &
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user_port_native_0_wdata_valid &
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user_port_native_0_rdata_ready &
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user_port_native_0_cmd_addr &
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user_port_native_0_wdata_we &
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user_port_native_0_wdata_data);
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end procedure;
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procedure recv_signals is
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variable wb_response : std_ulogic_vector(35 downto 0);
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variable ur_response : std_ulogic_vector(130 downto 0);
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begin
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litedram_get_wb(wb_response);
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wb_ctrl_dat_r <= wb_response(31 downto 0);
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wb_ctrl_ack <= wb_response(32);
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wb_ctrl_err <= wb_response(33);
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idone <= wb_response(34);
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ierr <= wb_response(35);
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litedram_get_user(ur_response);
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user_port_native_0_cmd_ready <= ur_response(130);
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user_port_native_0_wdata_ready <= ur_response(129);
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user_port_native_0_rdata_valid <= ur_response(128);
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user_port_native_0_rdata_data <= ur_response(127 downto 0);
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end procedure;
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begin
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if rising_edge(user_clk) then
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send_signals;
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recv_signals;
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-- Then generate a clock cycle ( 0->1 then 1->0 )
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litedram_clock;
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recv_signals;
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end if;
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if falling_edge(user_clk) then
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send_signals;
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recv_signals;
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end if;
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end process;
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end architecture;
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library work;
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use work.sim_litedram.all;
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entity litedram_trace_stub is
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end entity;
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architecture behaviour of litedram_trace_stub is
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begin
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process
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begin
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litedram_init(1);
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wait;
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end process;
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end architecture;
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@ -0,0 +1,198 @@
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <string.h>
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#include <termios.h>
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#include <unistd.h>
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#include <poll.h>
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#include "sim_vhpi_c.h"
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#include "Vlitedram_core.h"
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#include "verilated_vcd_c.h"
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static Vlitedram_core *v;
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vluint64_t main_time = 0;
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#if VM_TRACE
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VerilatedVcdC *tfp;
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#endif
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static void cleanup(void)
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{
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#if VM_TRACE
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if (tfp) {
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tfp->flush();
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tfp->close();
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delete tfp;
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}
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#endif
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}
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static inline void check_init(bool traces)
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{
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if (v)
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return;
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// XX Catch exceptions ?
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v = new Vlitedram_core;
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if (!v) {
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fprintf(stderr, "Failure allocating litedram core\n");
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exit(1);
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}
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#if VM_TRACE
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if (traces) {
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// init trace dump
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Verilated::traceEverOn(true);
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tfp = new VerilatedVcdC;
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v->trace(tfp, 99);
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tfp->open("litedram.vcd");
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}
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#endif
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atexit(cleanup);
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}
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unsigned char get_bit(unsigned char **p)
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{
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unsigned char b = **p;
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*p = *p + 1;
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return b == vhpi1 ? 1 : 0;
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}
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uint64_t get_bits(unsigned char **p, int len)
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{
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uint64_t r = 0;
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while(len--)
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r = (r << 1) | get_bit(p);
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return r;
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}
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void set_bit(unsigned char **p, int bit)
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{
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**p = bit ? vhpi1 : vhpi0;
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*p = *p + 1;
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}
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void set_bits(unsigned char **p, uint64_t val, int len)
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{
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while(len--)
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set_bit(p, (val >> len) & 1);
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}
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double sc_time_stamp(void)
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{
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return main_time;
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}
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#define check_size(s, exp) \
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do { \
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int __s = (s); \
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int __e = (exp); \
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if (__s != __e) \
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fprintf(stderr, "WARNING: %s exp %d got %d\n", __func__, __e, __s); \
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} while(0)
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static void do_eval(void)
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{
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v->eval();
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#if VM_TRACE
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if (tfp)
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tfp->dump((double) main_time);
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#endif
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}
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extern "C" void litedram_set_wb(unsigned char *req)
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{
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unsigned char *orig = req;
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check_init(false);
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v->wb_ctrl_cti = get_bits(&req, 3);
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v->wb_ctrl_bte = get_bits(&req, 2);
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v->wb_ctrl_sel = get_bits(&req, 4);
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v->wb_ctrl_we = get_bit(&req);
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v->wb_ctrl_stb = get_bit(&req);
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v->wb_ctrl_cyc = get_bit(&req);
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v->wb_ctrl_adr = get_bits(&req, 30);
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v->wb_ctrl_dat_w = get_bits(&req, 32);
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check_size(req - orig, 74);
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do_eval();
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}
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|
||||
extern "C" void litedram_get_wb(unsigned char *req)
|
||||
{
|
||||
unsigned char *orig = req;
|
||||
|
||||
check_init(false);
|
||||
|
||||
set_bit(&req, v->init_error);
|
||||
set_bit(&req, v->init_done);
|
||||
set_bit(&req, v->wb_ctrl_err);
|
||||
set_bit(&req, v->wb_ctrl_ack);
|
||||
set_bits(&req, v->wb_ctrl_dat_r, 32);
|
||||
|
||||
check_size(req - orig, 36);
|
||||
}
|
||||
|
||||
extern "C" void litedram_set_user(unsigned char *req)
|
||||
{
|
||||
unsigned char *orig = req;
|
||||
|
||||
check_init(false);
|
||||
|
||||
v->user_port_native_0_cmd_valid = get_bit(&req);
|
||||
v->user_port_native_0_cmd_we = get_bit(&req);
|
||||
v->user_port_native_0_wdata_valid = get_bit(&req);
|
||||
v->user_port_native_0_rdata_ready = get_bit(&req);
|
||||
v->user_port_native_0_cmd_addr = get_bits(&req, 24);
|
||||
v->user_port_native_0_wdata_we = get_bits(&req, 16);
|
||||
v->user_port_native_0_wdata_data[3] = get_bits(&req, 32);
|
||||
v->user_port_native_0_wdata_data[2] = get_bits(&req, 32);
|
||||
v->user_port_native_0_wdata_data[1] = get_bits(&req, 32);
|
||||
v->user_port_native_0_wdata_data[0] = get_bits(&req, 32);
|
||||
|
||||
check_size(req - orig, 172);
|
||||
|
||||
do_eval();
|
||||
}
|
||||
|
||||
extern "C" void litedram_get_user(unsigned char *req)
|
||||
{
|
||||
unsigned char *orig = req;
|
||||
|
||||
check_init(false);
|
||||
|
||||
set_bit(&req, v->user_port_native_0_cmd_ready);
|
||||
set_bit(&req, v->user_port_native_0_wdata_ready);
|
||||
set_bit(&req, v->user_port_native_0_rdata_valid);
|
||||
set_bits(&req, v->user_port_native_0_rdata_data[3], 32);
|
||||
set_bits(&req, v->user_port_native_0_rdata_data[2], 32);
|
||||
set_bits(&req, v->user_port_native_0_rdata_data[1], 32);
|
||||
set_bits(&req, v->user_port_native_0_rdata_data[0], 32);
|
||||
|
||||
check_size(req - orig, 131);
|
||||
}
|
||||
|
||||
extern "C" void litedram_clock(void)
|
||||
{
|
||||
check_init(false);
|
||||
|
||||
v->clk = 1;
|
||||
do_eval();
|
||||
main_time++;
|
||||
v->clk = 0;
|
||||
do_eval();
|
||||
main_time++;
|
||||
}
|
||||
|
||||
extern "C" void litedram_init(int trace_on)
|
||||
{
|
||||
check_init(!!trace_on);
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,39 @@
|
||||
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# License: BSD
|
||||
|
||||
{
|
||||
# General ------------------------------------------------------------------
|
||||
"cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32)
|
||||
"cpu_variant":"minimal",
|
||||
"speedgrade": -1, # FPGA speedgrade
|
||||
"memtype": "DDR3", # DRAM type
|
||||
"sim" : "True",
|
||||
|
||||
# PHY ----------------------------------------------------------------------
|
||||
"cmd_delay": 0, # Command additional delay (in taps)
|
||||
"cmd_latency": 0, # Command additional latency
|
||||
"sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM
|
||||
"sdram_module_nb": 2, # Number of byte groups
|
||||
"sdram_rank_nb": 1, # Number of ranks
|
||||
"sdram_phy": "A7DDRPHY", # Type of FPGA PHY
|
||||
|
||||
# Electrical ---------------------------------------------------------------
|
||||
"rtt_nom": "60ohm", # Nominal termination
|
||||
"rtt_wr": "60ohm", # Write termination
|
||||
"ron": "34ohm", # Output driver impedance
|
||||
|
||||
# Frequency ----------------------------------------------------------------
|
||||
"input_clk_freq": 100e6, # Input clock frequency
|
||||
"sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
|
||||
"iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
|
||||
|
||||
# Core ---------------------------------------------------------------------
|
||||
"cmd_buffer_depth": 16, # Depth of the command buffer
|
||||
|
||||
# User Ports ---------------------------------------------------------------
|
||||
"user_ports": {
|
||||
"native_0": {
|
||||
"type": "native",
|
||||
},
|
||||
},
|
||||
}
|
||||
@ -0,0 +1 @@
|
||||
none
|
||||
@ -1,284 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use std.textio.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
|
||||
entity litedram_wrapper is
|
||||
generic (
|
||||
DRAM_ABITS : positive;
|
||||
DRAM_ALINES : positive
|
||||
);
|
||||
port(
|
||||
-- LiteDRAM generates the system clock and reset
|
||||
-- from the input clkin
|
||||
clk_in : in std_ulogic;
|
||||
rst : in std_ulogic;
|
||||
system_clk : out std_ulogic;
|
||||
system_reset : out std_ulogic;
|
||||
core_alt_reset : out std_ulogic;
|
||||
pll_locked : out std_ulogic;
|
||||
|
||||
-- Wishbone ports:
|
||||
wb_in : in wishbone_master_out;
|
||||
wb_out : out wishbone_slave_out;
|
||||
wb_ctrl_in : in wb_io_master_out;
|
||||
wb_ctrl_out : out wb_io_slave_out;
|
||||
wb_ctrl_is_csr : in std_ulogic;
|
||||
wb_ctrl_is_init : in std_ulogic;
|
||||
|
||||
-- Init core serial debug
|
||||
serial_tx : out std_ulogic;
|
||||
serial_rx : in std_ulogic;
|
||||
|
||||
-- Misc
|
||||
init_done : out std_ulogic;
|
||||
init_error : out std_ulogic;
|
||||
|
||||
-- DRAM wires
|
||||
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
|
||||
ddram_ba : out std_ulogic_vector(2 downto 0);
|
||||
ddram_ras_n : out std_ulogic;
|
||||
ddram_cas_n : out std_ulogic;
|
||||
ddram_we_n : out std_ulogic;
|
||||
ddram_cs_n : out std_ulogic;
|
||||
ddram_dm : out std_ulogic_vector(1 downto 0);
|
||||
ddram_dq : inout std_ulogic_vector(15 downto 0);
|
||||
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
|
||||
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
|
||||
ddram_clk_p : out std_ulogic;
|
||||
ddram_clk_n : out std_ulogic;
|
||||
ddram_cke : out std_ulogic;
|
||||
ddram_odt : out std_ulogic;
|
||||
ddram_reset_n : out std_ulogic
|
||||
);
|
||||
end entity litedram_wrapper;
|
||||
|
||||
architecture behaviour of litedram_wrapper is
|
||||
|
||||
component litedram_core port (
|
||||
clk : in std_ulogic;
|
||||
rst : in std_ulogic;
|
||||
pll_locked : out std_ulogic;
|
||||
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
|
||||
ddram_ba : out std_ulogic_vector(2 downto 0);
|
||||
ddram_ras_n : out std_ulogic;
|
||||
ddram_cas_n : out std_ulogic;
|
||||
ddram_we_n : out std_ulogic;
|
||||
ddram_cs_n : out std_ulogic;
|
||||
ddram_dm : out std_ulogic_vector(1 downto 0);
|
||||
ddram_dq : inout std_ulogic_vector(15 downto 0);
|
||||
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
|
||||
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
|
||||
ddram_clk_p : out std_ulogic;
|
||||
ddram_clk_n : out std_ulogic;
|
||||
ddram_cke : out std_ulogic;
|
||||
ddram_odt : out std_ulogic;
|
||||
ddram_reset_n : out std_ulogic;
|
||||
init_done : out std_ulogic;
|
||||
init_error : out std_ulogic;
|
||||
user_clk : out std_ulogic;
|
||||
user_rst : out std_ulogic;
|
||||
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
|
||||
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
|
||||
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
|
||||
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
|
||||
wb_ctrl_cyc : in std_ulogic;
|
||||
wb_ctrl_stb : in std_ulogic;
|
||||
wb_ctrl_ack : out std_ulogic;
|
||||
wb_ctrl_we : in std_ulogic;
|
||||
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
|
||||
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
|
||||
wb_ctrl_err : out std_ulogic;
|
||||
user_port_native_0_cmd_valid : in std_ulogic;
|
||||
user_port_native_0_cmd_ready : out std_ulogic;
|
||||
user_port_native_0_cmd_we : in std_ulogic;
|
||||
user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
|
||||
user_port_native_0_wdata_valid : in std_ulogic;
|
||||
user_port_native_0_wdata_ready : out std_ulogic;
|
||||
user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0);
|
||||
user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0);
|
||||
user_port_native_0_rdata_valid : out std_ulogic;
|
||||
user_port_native_0_rdata_ready : in std_ulogic;
|
||||
user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal user_port0_cmd_valid : std_ulogic;
|
||||
signal user_port0_cmd_ready : std_ulogic;
|
||||
signal user_port0_cmd_we : std_ulogic;
|
||||
signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0);
|
||||
signal user_port0_wdata_valid : std_ulogic;
|
||||
signal user_port0_wdata_ready : std_ulogic;
|
||||
signal user_port0_wdata_we : std_ulogic_vector(15 downto 0);
|
||||
signal user_port0_wdata_data : std_ulogic_vector(127 downto 0);
|
||||
signal user_port0_rdata_valid : std_ulogic;
|
||||
signal user_port0_rdata_ready : std_ulogic;
|
||||
signal user_port0_rdata_data : std_ulogic_vector(127 downto 0);
|
||||
|
||||
signal ad3 : std_ulogic;
|
||||
|
||||
signal wb_ctrl_adr : std_ulogic_vector(29 downto 0);
|
||||
signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0);
|
||||
signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0);
|
||||
signal wb_ctrl_sel : std_ulogic_vector(3 downto 0);
|
||||
signal wb_ctrl_cyc : std_ulogic;
|
||||
signal wb_ctrl_stb : std_ulogic;
|
||||
signal wb_ctrl_ack : std_ulogic;
|
||||
signal wb_ctrl_we : std_ulogic;
|
||||
|
||||
signal wb_init_in : wb_io_master_out;
|
||||
signal wb_init_out : wb_io_slave_out;
|
||||
|
||||
type state_t is (CMD, MWRITE, MREAD);
|
||||
signal state : state_t;
|
||||
|
||||
begin
|
||||
|
||||
-- alternate core reset address set when DRAM is not initialized.
|
||||
core_alt_reset <= not init_done;
|
||||
|
||||
-- Init code BRAM memory slave
|
||||
init_ram_0: entity work.dram_init_mem
|
||||
port map(
|
||||
clk => system_clk,
|
||||
wb_in => wb_init_in,
|
||||
wb_out => wb_init_out
|
||||
);
|
||||
|
||||
--
|
||||
-- Control bus wishbone: This muxes the wishbone to the CSRs
|
||||
-- and an internal small one to the init BRAM
|
||||
--
|
||||
|
||||
-- Init DRAM wishbone IN signals
|
||||
wb_init_in.adr <= wb_ctrl_in.adr;
|
||||
wb_init_in.dat <= wb_ctrl_in.dat;
|
||||
wb_init_in.sel <= wb_ctrl_in.sel;
|
||||
wb_init_in.we <= wb_ctrl_in.we;
|
||||
wb_init_in.stb <= wb_ctrl_in.stb;
|
||||
wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init;
|
||||
|
||||
-- DRAM CSR IN signals
|
||||
wb_ctrl_adr <= x"0000" & wb_ctrl_in.adr(15 downto 2);
|
||||
wb_ctrl_dat_w <= wb_ctrl_in.dat;
|
||||
wb_ctrl_sel <= wb_ctrl_in.sel;
|
||||
wb_ctrl_we <= wb_ctrl_in.we;
|
||||
wb_ctrl_cyc <= wb_ctrl_in.cyc and wb_ctrl_is_csr;
|
||||
wb_ctrl_stb <= wb_ctrl_in.stb and wb_ctrl_is_csr;
|
||||
|
||||
-- Ctrl bus wishbone OUT signals
|
||||
wb_ctrl_out.ack <= wb_ctrl_ack when wb_ctrl_is_csr = '1'
|
||||
else wb_init_out.ack;
|
||||
wb_ctrl_out.dat <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1'
|
||||
else wb_init_out.dat;
|
||||
wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else
|
||||
'0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack;
|
||||
|
||||
--
|
||||
-- Data bus wishbone to LiteDRAM native port
|
||||
--
|
||||
-- Address bit 3 selects the top or bottom half of the data
|
||||
-- bus (64-bit wishbone vs. 128-bit DRAM interface)
|
||||
--
|
||||
-- XXX TODO: Figure out how to pipeline this
|
||||
--
|
||||
ad3 <= wb_in.adr(3);
|
||||
|
||||
-- Wishbone port IN signals
|
||||
user_port0_cmd_valid <= wb_in.cyc and wb_in.stb when state = CMD else '0';
|
||||
user_port0_cmd_we <= wb_in.we when state = CMD else '0';
|
||||
user_port0_wdata_valid <= '1' when state = MWRITE else '0';
|
||||
user_port0_rdata_ready <= '1' when state = MREAD else '0';
|
||||
user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4);
|
||||
user_port0_wdata_data <= wb_in.dat & wb_in.dat;
|
||||
user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
|
||||
"00000000" & wb_in.sel;
|
||||
|
||||
-- Wishbone OUT signals
|
||||
wb_out.ack <= user_port0_wdata_ready when state = MWRITE else
|
||||
user_port0_rdata_valid when state = MREAD else '0';
|
||||
|
||||
wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else
|
||||
user_port0_rdata_data(63 downto 0);
|
||||
|
||||
-- We don't do pipelining yet.
|
||||
wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
|
||||
|
||||
-- DRAM user port State machine
|
||||
sm: process(system_clk)
|
||||
begin
|
||||
|
||||
if rising_edge(system_clk) then
|
||||
if system_reset = '1' then
|
||||
state <= CMD;
|
||||
else
|
||||
case state is
|
||||
when CMD =>
|
||||
if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
|
||||
state <= MWRITE when wb_in.we = '1' else MREAD;
|
||||
end if;
|
||||
when MWRITE =>
|
||||
if user_port0_wdata_ready = '1' then
|
||||
state <= CMD;
|
||||
end if;
|
||||
when MREAD =>
|
||||
if user_port0_rdata_valid = '1' then
|
||||
state <= CMD;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
litedram: litedram_core
|
||||
port map(
|
||||
clk => clk_in,
|
||||
rst => rst,
|
||||
pll_locked => pll_locked,
|
||||
ddram_a => ddram_a,
|
||||
ddram_ba => ddram_ba,
|
||||
ddram_ras_n => ddram_ras_n,
|
||||
ddram_cas_n => ddram_cas_n,
|
||||
ddram_we_n => ddram_we_n,
|
||||
ddram_cs_n => ddram_cs_n,
|
||||
ddram_dm => ddram_dm,
|
||||
ddram_dq => ddram_dq,
|
||||
ddram_dqs_p => ddram_dqs_p,
|
||||
ddram_dqs_n => ddram_dqs_n,
|
||||
ddram_clk_p => ddram_clk_p,
|
||||
ddram_clk_n => ddram_clk_n,
|
||||
ddram_cke => ddram_cke,
|
||||
ddram_odt => ddram_odt,
|
||||
ddram_reset_n => ddram_reset_n,
|
||||
init_done => init_done,
|
||||
init_error => init_error,
|
||||
user_clk => system_clk,
|
||||
user_rst => system_reset,
|
||||
wb_ctrl_adr => wb_ctrl_adr,
|
||||
wb_ctrl_dat_w => wb_ctrl_dat_w,
|
||||
wb_ctrl_dat_r => wb_ctrl_dat_r,
|
||||
wb_ctrl_sel => wb_ctrl_sel,
|
||||
wb_ctrl_cyc => wb_ctrl_cyc,
|
||||
wb_ctrl_stb => wb_ctrl_stb,
|
||||
wb_ctrl_ack => wb_ctrl_ack,
|
||||
wb_ctrl_we => wb_ctrl_we,
|
||||
wb_ctrl_cti => "000",
|
||||
wb_ctrl_bte => "00",
|
||||
wb_ctrl_err => open,
|
||||
user_port_native_0_cmd_valid => user_port0_cmd_valid,
|
||||
user_port_native_0_cmd_ready => user_port0_cmd_ready,
|
||||
user_port_native_0_cmd_we => user_port0_cmd_we,
|
||||
user_port_native_0_cmd_addr => user_port0_cmd_addr,
|
||||
user_port_native_0_wdata_valid => user_port0_wdata_valid,
|
||||
user_port_native_0_wdata_ready => user_port0_wdata_ready,
|
||||
user_port_native_0_wdata_we => user_port0_wdata_we,
|
||||
user_port_native_0_wdata_data => user_port0_wdata_data,
|
||||
user_port_native_0_rdata_valid => user_port0_rdata_valid,
|
||||
user_port_native_0_rdata_ready => user_port0_rdata_ready,
|
||||
user_port_native_0_rdata_data => user_port0_rdata_data
|
||||
);
|
||||
|
||||
end architecture behaviour;
|
||||
@ -0,0 +1 @@
|
||||
none
|
||||
@ -1,284 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use std.textio.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
|
||||
entity litedram_wrapper is
|
||||
generic (
|
||||
DRAM_ABITS : positive;
|
||||
DRAM_ALINES : positive
|
||||
);
|
||||
port(
|
||||
-- LiteDRAM generates the system clock and reset
|
||||
-- from the input clkin
|
||||
clk_in : in std_ulogic;
|
||||
rst : in std_ulogic;
|
||||
system_clk : out std_ulogic;
|
||||
system_reset : out std_ulogic;
|
||||
core_alt_reset : out std_ulogic;
|
||||
pll_locked : out std_ulogic;
|
||||
|
||||
-- Wishbone ports:
|
||||
wb_in : in wishbone_master_out;
|
||||
wb_out : out wishbone_slave_out;
|
||||
wb_ctrl_in : in wb_io_master_out;
|
||||
wb_ctrl_out : out wb_io_slave_out;
|
||||
wb_ctrl_is_csr : in std_ulogic;
|
||||
wb_ctrl_is_init : in std_ulogic;
|
||||
|
||||
-- Init core serial debug
|
||||
serial_tx : out std_ulogic;
|
||||
serial_rx : in std_ulogic;
|
||||
|
||||
-- Misc
|
||||
init_done : out std_ulogic;
|
||||
init_error : out std_ulogic;
|
||||
|
||||
-- DRAM wires
|
||||
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
|
||||
ddram_ba : out std_ulogic_vector(2 downto 0);
|
||||
ddram_ras_n : out std_ulogic;
|
||||
ddram_cas_n : out std_ulogic;
|
||||
ddram_we_n : out std_ulogic;
|
||||
ddram_cs_n : out std_ulogic;
|
||||
ddram_dm : out std_ulogic_vector(1 downto 0);
|
||||
ddram_dq : inout std_ulogic_vector(15 downto 0);
|
||||
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
|
||||
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
|
||||
ddram_clk_p : out std_ulogic;
|
||||
ddram_clk_n : out std_ulogic;
|
||||
ddram_cke : out std_ulogic;
|
||||
ddram_odt : out std_ulogic;
|
||||
ddram_reset_n : out std_ulogic
|
||||
);
|
||||
end entity litedram_wrapper;
|
||||
|
||||
architecture behaviour of litedram_wrapper is
|
||||
|
||||
component litedram_core port (
|
||||
clk : in std_ulogic;
|
||||
rst : in std_ulogic;
|
||||
pll_locked : out std_ulogic;
|
||||
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
|
||||
ddram_ba : out std_ulogic_vector(2 downto 0);
|
||||
ddram_ras_n : out std_ulogic;
|
||||
ddram_cas_n : out std_ulogic;
|
||||
ddram_we_n : out std_ulogic;
|
||||
ddram_cs_n : out std_ulogic;
|
||||
ddram_dm : out std_ulogic_vector(1 downto 0);
|
||||
ddram_dq : inout std_ulogic_vector(15 downto 0);
|
||||
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
|
||||
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
|
||||
ddram_clk_p : out std_ulogic;
|
||||
ddram_clk_n : out std_ulogic;
|
||||
ddram_cke : out std_ulogic;
|
||||
ddram_odt : out std_ulogic;
|
||||
ddram_reset_n : out std_ulogic;
|
||||
init_done : out std_ulogic;
|
||||
init_error : out std_ulogic;
|
||||
user_clk : out std_ulogic;
|
||||
user_rst : out std_ulogic;
|
||||
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
|
||||
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
|
||||
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
|
||||
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
|
||||
wb_ctrl_cyc : in std_ulogic;
|
||||
wb_ctrl_stb : in std_ulogic;
|
||||
wb_ctrl_ack : out std_ulogic;
|
||||
wb_ctrl_we : in std_ulogic;
|
||||
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
|
||||
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
|
||||
wb_ctrl_err : out std_ulogic;
|
||||
user_port_native_0_cmd_valid : in std_ulogic;
|
||||
user_port_native_0_cmd_ready : out std_ulogic;
|
||||
user_port_native_0_cmd_we : in std_ulogic;
|
||||
user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
|
||||
user_port_native_0_wdata_valid : in std_ulogic;
|
||||
user_port_native_0_wdata_ready : out std_ulogic;
|
||||
user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0);
|
||||
user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0);
|
||||
user_port_native_0_rdata_valid : out std_ulogic;
|
||||
user_port_native_0_rdata_ready : in std_ulogic;
|
||||
user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal user_port0_cmd_valid : std_ulogic;
|
||||
signal user_port0_cmd_ready : std_ulogic;
|
||||
signal user_port0_cmd_we : std_ulogic;
|
||||
signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0);
|
||||
signal user_port0_wdata_valid : std_ulogic;
|
||||
signal user_port0_wdata_ready : std_ulogic;
|
||||
signal user_port0_wdata_we : std_ulogic_vector(15 downto 0);
|
||||
signal user_port0_wdata_data : std_ulogic_vector(127 downto 0);
|
||||
signal user_port0_rdata_valid : std_ulogic;
|
||||
signal user_port0_rdata_ready : std_ulogic;
|
||||
signal user_port0_rdata_data : std_ulogic_vector(127 downto 0);
|
||||
|
||||
signal ad3 : std_ulogic;
|
||||
|
||||
signal wb_ctrl_adr : std_ulogic_vector(29 downto 0);
|
||||
signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0);
|
||||
signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0);
|
||||
signal wb_ctrl_sel : std_ulogic_vector(3 downto 0);
|
||||
signal wb_ctrl_cyc : std_ulogic;
|
||||
signal wb_ctrl_stb : std_ulogic;
|
||||
signal wb_ctrl_ack : std_ulogic;
|
||||
signal wb_ctrl_we : std_ulogic;
|
||||
|
||||
signal wb_init_in : wb_io_master_out;
|
||||
signal wb_init_out : wb_io_slave_out;
|
||||
|
||||
type state_t is (CMD, MWRITE, MREAD);
|
||||
signal state : state_t;
|
||||
|
||||
begin
|
||||
|
||||
-- alternate core reset address set when DRAM is not initialized.
|
||||
core_alt_reset <= not init_done;
|
||||
|
||||
-- Init code BRAM memory slave
|
||||
init_ram_0: entity work.dram_init_mem
|
||||
port map(
|
||||
clk => system_clk,
|
||||
wb_in => wb_init_in,
|
||||
wb_out => wb_init_out
|
||||
);
|
||||
|
||||
--
|
||||
-- Control bus wishbone: This muxes the wishbone to the CSRs
|
||||
-- and an internal small one to the init BRAM
|
||||
--
|
||||
|
||||
-- Init DRAM wishbone IN signals
|
||||
wb_init_in.adr <= wb_ctrl_in.adr;
|
||||
wb_init_in.dat <= wb_ctrl_in.dat;
|
||||
wb_init_in.sel <= wb_ctrl_in.sel;
|
||||
wb_init_in.we <= wb_ctrl_in.we;
|
||||
wb_init_in.stb <= wb_ctrl_in.stb;
|
||||
wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init;
|
||||
|
||||
-- DRAM CSR IN signals
|
||||
wb_ctrl_adr <= x"0000" & wb_ctrl_in.adr(15 downto 2);
|
||||
wb_ctrl_dat_w <= wb_ctrl_in.dat;
|
||||
wb_ctrl_sel <= wb_ctrl_in.sel;
|
||||
wb_ctrl_we <= wb_ctrl_in.we;
|
||||
wb_ctrl_cyc <= wb_ctrl_in.cyc and wb_ctrl_is_csr;
|
||||
wb_ctrl_stb <= wb_ctrl_in.stb and wb_ctrl_is_csr;
|
||||
|
||||
-- Ctrl bus wishbone OUT signals
|
||||
wb_ctrl_out.ack <= wb_ctrl_ack when wb_ctrl_is_csr = '1'
|
||||
else wb_init_out.ack;
|
||||
wb_ctrl_out.dat <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1'
|
||||
else wb_init_out.dat;
|
||||
wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else
|
||||
'0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack;
|
||||
|
||||
--
|
||||
-- Data bus wishbone to LiteDRAM native port
|
||||
--
|
||||
-- Address bit 3 selects the top or bottom half of the data
|
||||
-- bus (64-bit wishbone vs. 128-bit DRAM interface)
|
||||
--
|
||||
-- XXX TODO: Figure out how to pipeline this
|
||||
--
|
||||
ad3 <= wb_in.adr(3);
|
||||
|
||||
-- Wishbone port IN signals
|
||||
user_port0_cmd_valid <= wb_in.cyc and wb_in.stb when state = CMD else '0';
|
||||
user_port0_cmd_we <= wb_in.we when state = CMD else '0';
|
||||
user_port0_wdata_valid <= '1' when state = MWRITE else '0';
|
||||
user_port0_rdata_ready <= '1' when state = MREAD else '0';
|
||||
user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4);
|
||||
user_port0_wdata_data <= wb_in.dat & wb_in.dat;
|
||||
user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
|
||||
"00000000" & wb_in.sel;
|
||||
|
||||
-- Wishbone OUT signals
|
||||
wb_out.ack <= user_port0_wdata_ready when state = MWRITE else
|
||||
user_port0_rdata_valid when state = MREAD else '0';
|
||||
|
||||
wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else
|
||||
user_port0_rdata_data(63 downto 0);
|
||||
|
||||
-- We don't do pipelining yet.
|
||||
wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
|
||||
|
||||
-- DRAM user port State machine
|
||||
sm: process(system_clk)
|
||||
begin
|
||||
|
||||
if rising_edge(system_clk) then
|
||||
if system_reset = '1' then
|
||||
state <= CMD;
|
||||
else
|
||||
case state is
|
||||
when CMD =>
|
||||
if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
|
||||
state <= MWRITE when wb_in.we = '1' else MREAD;
|
||||
end if;
|
||||
when MWRITE =>
|
||||
if user_port0_wdata_ready = '1' then
|
||||
state <= CMD;
|
||||
end if;
|
||||
when MREAD =>
|
||||
if user_port0_rdata_valid = '1' then
|
||||
state <= CMD;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
litedram: litedram_core
|
||||
port map(
|
||||
clk => clk_in,
|
||||
rst => rst,
|
||||
pll_locked => pll_locked,
|
||||
ddram_a => ddram_a,
|
||||
ddram_ba => ddram_ba,
|
||||
ddram_ras_n => ddram_ras_n,
|
||||
ddram_cas_n => ddram_cas_n,
|
||||
ddram_we_n => ddram_we_n,
|
||||
ddram_cs_n => ddram_cs_n,
|
||||
ddram_dm => ddram_dm,
|
||||
ddram_dq => ddram_dq,
|
||||
ddram_dqs_p => ddram_dqs_p,
|
||||
ddram_dqs_n => ddram_dqs_n,
|
||||
ddram_clk_p => ddram_clk_p,
|
||||
ddram_clk_n => ddram_clk_n,
|
||||
ddram_cke => ddram_cke,
|
||||
ddram_odt => ddram_odt,
|
||||
ddram_reset_n => ddram_reset_n,
|
||||
init_done => init_done,
|
||||
init_error => init_error,
|
||||
user_clk => system_clk,
|
||||
user_rst => system_reset,
|
||||
wb_ctrl_adr => wb_ctrl_adr,
|
||||
wb_ctrl_dat_w => wb_ctrl_dat_w,
|
||||
wb_ctrl_dat_r => wb_ctrl_dat_r,
|
||||
wb_ctrl_sel => wb_ctrl_sel,
|
||||
wb_ctrl_cyc => wb_ctrl_cyc,
|
||||
wb_ctrl_stb => wb_ctrl_stb,
|
||||
wb_ctrl_ack => wb_ctrl_ack,
|
||||
wb_ctrl_we => wb_ctrl_we,
|
||||
wb_ctrl_cti => "000",
|
||||
wb_ctrl_bte => "00",
|
||||
wb_ctrl_err => open,
|
||||
user_port_native_0_cmd_valid => user_port0_cmd_valid,
|
||||
user_port_native_0_cmd_ready => user_port0_cmd_ready,
|
||||
user_port_native_0_cmd_we => user_port0_cmd_we,
|
||||
user_port_native_0_cmd_addr => user_port0_cmd_addr,
|
||||
user_port_native_0_wdata_valid => user_port0_wdata_valid,
|
||||
user_port_native_0_wdata_ready => user_port0_wdata_ready,
|
||||
user_port_native_0_wdata_we => user_port0_wdata_we,
|
||||
user_port_native_0_wdata_data => user_port0_wdata_data,
|
||||
user_port_native_0_rdata_valid => user_port0_rdata_valid,
|
||||
user_port_native_0_rdata_ready => user_port0_rdata_ready,
|
||||
user_port_native_0_rdata_data => user_port0_rdata_data
|
||||
);
|
||||
|
||||
end architecture behaviour;
|
||||
@ -0,0 +1 @@
|
||||
none
|
||||
@ -0,0 +1,72 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use std.textio.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
|
||||
entity dram_init_mem is
|
||||
port (
|
||||
clk : in std_ulogic;
|
||||
wb_in : in wb_io_master_out;
|
||||
wb_out : out wb_io_slave_out
|
||||
);
|
||||
end entity dram_init_mem;
|
||||
|
||||
architecture rtl of dram_init_mem is
|
||||
|
||||
constant INIT_RAM_SIZE : integer := 16384;
|
||||
constant INIT_RAM_ABITS :integer := 14;
|
||||
constant INIT_RAM_FILE : string := "litedram/generated/sim/litedram_core.init";
|
||||
|
||||
type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
|
||||
|
||||
impure function init_load_ram(name : string) return ram_t is
|
||||
file ram_file : text open read_mode is name;
|
||||
variable temp_word : std_logic_vector(63 downto 0);
|
||||
variable temp_ram : ram_t := (others => (others => '0'));
|
||||
variable ram_line : line;
|
||||
begin
|
||||
for i in 0 to (INIT_RAM_SIZE/8)-1 loop
|
||||
exit when endfile(ram_file);
|
||||
readline(ram_file, ram_line);
|
||||
hread(ram_line, temp_word);
|
||||
temp_ram(i*2) := temp_word(31 downto 0);
|
||||
temp_ram(i*2+1) := temp_word(63 downto 32);
|
||||
end loop;
|
||||
return temp_ram;
|
||||
end function;
|
||||
|
||||
signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
|
||||
|
||||
attribute ram_style : string;
|
||||
attribute ram_style of init_ram: signal is "block";
|
||||
|
||||
begin
|
||||
|
||||
init_ram_0: process(clk)
|
||||
variable adr : integer;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
wb_out.ack <= '0';
|
||||
if (wb_in.cyc and wb_in.stb) = '1' then
|
||||
adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
|
||||
if wb_in.we = '0' then
|
||||
wb_out.dat <= init_ram(adr);
|
||||
else
|
||||
for i in 0 to 3 loop
|
||||
if wb_in.sel(i) = '1' then
|
||||
init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
|
||||
wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
wb_out.ack <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
wb_out.stall <= '0';
|
||||
|
||||
end architecture rtl;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
Loading…
Reference in New Issue