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73 lines
1.9 KiB
VHDL
73 lines
1.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.wishbone_types.all;
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entity dram_init_mem is
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port (
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clk : in std_ulogic;
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wb_in : in wb_io_master_out;
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wb_out : out wb_io_slave_out
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);
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end entity dram_init_mem;
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architecture rtl of dram_init_mem is
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constant INIT_RAM_SIZE : integer := 16384;
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constant INIT_RAM_ABITS :integer := 14;
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constant INIT_RAM_FILE : string := "litedram/generated/sim/litedram_core.init";
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type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
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impure function init_load_ram(name : string) return ram_t is
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file ram_file : text open read_mode is name;
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variable temp_word : std_logic_vector(63 downto 0);
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variable temp_ram : ram_t := (others => (others => '0'));
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variable ram_line : line;
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begin
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for i in 0 to (INIT_RAM_SIZE/8)-1 loop
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exit when endfile(ram_file);
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readline(ram_file, ram_line);
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hread(ram_line, temp_word);
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temp_ram(i*2) := temp_word(31 downto 0);
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temp_ram(i*2+1) := temp_word(63 downto 32);
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end loop;
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return temp_ram;
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end function;
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signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
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attribute ram_style : string;
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attribute ram_style of init_ram: signal is "block";
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begin
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init_ram_0: process(clk)
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variable adr : integer;
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begin
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if rising_edge(clk) then
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wb_out.ack <= '0';
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if (wb_in.cyc and wb_in.stb) = '1' then
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adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
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if wb_in.we = '0' then
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wb_out.dat <= init_ram(adr);
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else
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for i in 0 to 3 loop
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if wb_in.sel(i) = '1' then
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init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
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wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
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end if;
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end loop;
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end if;
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wb_out.ack <= '1';
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end if;
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end if;
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end process;
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wb_out.stall <= '0';
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end architecture rtl;
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