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a3c25ddd99
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2 years ago | |
|---|---|---|
| .. | ||
| build_smt2 | ||
| build_st | ||
| build_sweetpea | ||
| A2L2.py | 2 years ago | |
| A2O.py | 2 years ago | |
| Makefile.node | 2 years ago | |
| Makefile.smt2 | ||
| Makefile.st | 2 years ago | |
| Makefile.sweetpea | ||
| Makefile.verilator | ||
| OPEnv.py | 2 years ago | |
| boot.lst | ||
| cocotb_icarus.v | ||
| cocotb_icarus_node.v | 2 years ago | |
| makegtkw | ||
| pyvcd.gtkw | ||
| readme.md | 2 years ago | |
| results.xml | ||
| sim.png | ||
| sim.txt | 2 years ago | |
| tb.py | 2 years ago | |
| tb_node.py | 2 years ago | |
| verilog | ||
| wtf.gtkw | 2 years ago | |
readme.md
Cocotb Sim Experiments
Core-only version with partial implementation of Python A2L2 interface
- testbench provides memory using A2 core-L2 interface
make -f Makefile.st build |& grep -v Anac
Core+wrapper version with partial implementation of A2Node
- testbench provides memory using simple RAM interface
make -f Makefile.node build |& grep -v Anac
Core+wrapper version with implementation of A2Node (Wishbone system bus)
- testbench provides Wishbone interface
- can be easily dropped into Litex, etc. for Verilator and FPGA
- can add L2 mem
- can add multiple core intefaces (SMP)
- can add multicore+heterogeneous cores (mixed A2L2, WB-1, WB-2)