add dev

README.md

@@ -1,5 +1,20 @@
 # A2O
 
+# Current Status
+
+* for now, /rel is the original and /dev has updates:
+
+   * compiles with verilator, iverilog, yosys
+   * runs original simple boot code up to test invocation with cocotb (A2L2 interface partially implemented in Python)
+
+## To Do
+
+   * continue with cocotb testing
+   * add A2Node bridge to WB, and Litex wrapper
+   * experiment with parameters to create smaller version(s) for dOpenLane
+
+# Original Release
+
 ## The Project
 This is the release of the A2O POWER processor core RTL and associated FPGA implementation (using ADM-PCIE-9V3 FPGA).
 

dev/.gitignore

@@ -0,0 +1 @@
+*.pdf

dev/readme.md

@@ -0,0 +1,32 @@
+# Testing RTL with new environments
+
+##
+
+* RTL
+
+   * updated source to remove a bunch of Verilator warnings
+   * updated source for compatibility with Icaraus -g2012
+   * changed the GPR/FPR macro to remove need for clk4x on FPGA; was ugly and not working with either simulator
+
+* Verilator
+
+   * can IFETCH some ops in ST and SMT2 mode
+   * can't get cocotb to build with Verilator (very long compile times)
+
+* Icarus (w/cocotb)
+
+   * executing boot code until test call with python A2L2 interface
+
+* Yosys
+
+   * finishes compile
+
+
+## Next To Do
+
+* create A2L2 cpp model that can be used by Verilator and cocotb (Cython wrapper)
+* create simple A2L2-WB RTL for easily connecting to Litex, etc.
+* create Litex core wrapper
+* OpenLane experiments with blackbox arrays and yosys/abc/sta
+* create FPGA version of GPR/FPR (4R4W) using (4)4R1W banks and valid table
+* parse vcd/fst and serve browser code for custom trace screens (handle spec/arch mapped facilities, arrays, etc.)

dev/sim/.gitignore

@@ -0,0 +1,11 @@
+# verilator
+**/obj_dir*/
+# cooc/icarus
+coco_icarus
+**/sim_build*/
+# gtkwave
+*.vcd
+*.fst
+# python
+**/__pycache__/
+*.py[cod]

dev/sim/coco/A2L2.py

@@ -0,0 +1,413 @@
+# A2L2 Interface
+
+import cocotb
+from cocotb.triggers import Timer, RisingEdge
+from cocotb.binary import BinaryValue
+from cocotb.handle import Force
+from cocotb.handle import Release
+
+from dotmap import DotMap
+import itertools
+
+# ------------------------------------------------------------------------------------------------
+# Classes
+
+'''
+Data return timings from spec:
+
+* Reload Data Coming
+Indicates that reload data is coming in three cycles. This signal is required for L2 designs that return data in consecutive cycles, but can be
+tied to a logic ‘0’ for designs that return data in every other cycle. For L2 designs that return data in consecutive cycles, this signal should be
+asserted three cycles ahead of the first of two paired data beats. If more than two data beats will be presented consecutively, this signal should be
+asserted once for the first set of two (paired) data beats and once for the second set of two (paired) data beats. Each assertion
+should be three cycles ahead of the first beat of the paired set of data beats. This signal allows the A2 core to insert an issue bubble for the second
+reload data beat to avoid flushing the processor pipe. This signal is not required to be asserted as described above for DITC return data.
+For non-cacheable (I=1) reloads of one or two beats, this signal should be asserted three cycles ahead of the first (and possibly only) data beat transfer.
+
+* Reload Data Valid
+Indicates that reload data is coming in two cycles.  This signal qualifies the other reload interface signals sent in this cycle: reld_ditc, reld_core_tag, reld_crit_qw, and reld_qw.
+If reld_data_vld is not active, then the qualified signals should be ignored.
+
+* Reload Direct Inter-Thread Communication
+Indicates that the reload data is associated with a DITC transfer instead of a standard load-ttype reload. This signal is qualified by reld_data_vld and determines the
+interpretation of the reld_core_tag bus. DITC reload data transfers are always 64-Byte transfers that follow the same consecutive cycle or every-other-cycle behavior
+as standard load-ttype reloads for the attached L2.
+
+**i believe this means ditc can use either 1of2/2of2 or 1of2/-/-/2of2 pattern, but never requires data_coming (probs because pipe considerations not important for ditc)**
+
+======
+Cycles:
+
+* d-3 (reld_data_coming)
+Loads:
+1. I=1: assert 3 cycs ahead of first transfer (two transfers only if 32B allowed)
+2. I=0 data every other cycle: not asserted
+3. I=0 data consecutive cycles: assert 3 cycs ahead of the 1of2 paired beats; if more than 2 beats are consecutive, assert 3 cycs ahead of each paired beat
+DITC:
+1. assertion not required **(or used by core?)**
+
+* d-2 (reld_data_vld and qualified signals)
+Loads:
+1. assert 2 cycs ahead of data
+DITC:
+1. assert 2 cycs ahead of data and also assert reld_ditc
+
+Cacheable Return Modes:
+1. no back-to-back: coming=0
+2. all back-to-back: coming=1/0/1
+3. interleaved back-to-back: coming=1/0/0/0/1
+4. mixed: legal cases for subxfers (?) **i think the 'mixed' aren't valid - xucr0[52] selects b2b mode**
+   * 1 1 1 1   (no b2b)
+   * 1 2 1     (mixed)
+   * 1 1 2     (mixed)
+   * 2 1 1     (mixed)
+   * 2 2       (full b2b)
+5. between subxfers a delay or other transaction can be inserted
+
+?? xucr0[52] definition selects b2b but also says crit first; i guess this means crit first is allowed, but not required?? a2l2 spec says it is not required to send crit first
+
+'''
+class A2L2Trans(DotMap):
+   '''A2L2 Transaction'''
+   nextID = itertools.count()
+   def __init__(self, sim, tid, tt, tag=None, addr=None, length=0, wimg=0, cycD=None, be=None, data=None):
+      super().__init__()
+      self.sim = sim
+      self.id = next(A2L2Trans.nextID)
+      self.tid = tid
+      self.tt = tt
+      self.tag = tag
+      self.addr = addr
+      self.len = length
+      self.wimg = wimg
+      self.xfers = 1
+      self.xferNum = 0
+      self.xferCrit = 1
+      self.beatNum = 1
+      if cycD is not None:
+         self.cycC = cycD - 3
+         self.cycV = cycD - 2
+         self.cycD = cycD
+      self.be = f'{int(be, 16):032b}' if be is not None else None
+      self.data = data
+      self.done = False
+
+      self.ieq1 = wimg & 0x4 == 0x4
+
+      self.load = tt == 0x00 or tt == 0x08 or tt == 0x22 or tt == 0x09 or tt == 0x0B   # IF, LD, DITC, LARX, LARX_HINT
+      self.store = tt == 0x20 or tt == 0x29                                            # ST, STCX
+
+      if self.load:
+         self.addr = self.addr & 0xFFFFFFF0
+      elif self.store:
+         self.addr = self.addr & 0xFFFFFFE0
+         if self.be == None or self.data == None:
+            raise Exception('A2L2Trans: store must have BE and data')
+         else:
+            self.len = 0
+            self.storeStart = None
+            for i in range(len(self.be)):
+               if self.be[i] == '1':
+                  if self.storeStart is None:
+                     self.storeStart = i
+                  self.len += 1
+               elif self.storeStart is not None:
+                  break
+      else:
+         raise Exception(f'A2L2Trans: unsupported ttype={tt}')
+
+      self.ditc = tt == 0x22
+
+      if self.ieq1:
+         if tt == 0x00 or tt == 0x08:                    # IF, LD
+            if len == 7:
+               self.xfers = 2
+         elif tt == 0x22:                                # DITC
+               self.xfers = 4
+      else:
+         if self.load:
+            self.xfers = 4
+            self.xferCrit = ((self.addr & 0x30) >> 4) + 1
+            self.addr = self.addr & 0xFFFFFFC0
+
+   def readXfer(self):
+      # read() returns this qw crit-first if cacheable!
+      w0 = self.sim.mem.read(self.addr)
+      w1 = self.sim.mem.read(self.addr+4)
+      w2 = self.sim.mem.read(self.addr+8)
+      w3 = self.sim.mem.read(self.addr+12)
+      beatNum = self.beatNum
+      if self.beatNum < self.xfers:
+         self.beatNum += 1
+         self.cycD += 1
+         self.addr += 16        #wtf this is wrong - going to need to schedule the pattern when the trans is created!!!!!!!!!!!!!!!!!!!!!!!!
+      return w0,w1,w2,w3,beatNum
+
+   def doStore(self):
+      addr = ((self.addr + self.storeStart) >> 2) << 2
+      dataStart = self.storeStart*2
+      if self.len == 1:
+         word = self.sim.mem.read(addr)
+         byte = self.addr & 0x3
+         if byte == 0:
+            mask = 0xFFFFFF00
+         elif byte == 1:
+            mask = 0xFFFF00FF
+         elif byte == 2:
+            mask = 0xFF00FFFF
+         else:
+            mask = 0x00FFFFFF
+         word = (word & mask) | (int(self.data[dataStart:dataStart+2], 16) << (byte*2))
+         self.sim.mem.write(addr, word)
+
+      elif self.len == 2:
+         word = self.sim.mem.read(addr)
+         hw = (self.addr & 0x2) >> 1
+         if hw == 0:
+            mask = 0xFFFF0000
+         else:
+            mask = 0x0000FFFF
+         word = (word & mask) | (int(self.data[dataStart:dataStart+4], 16) << (hw*4))
+         self.sim.mem.write(addr, word)
+
+      elif self.len == 4:
+         self.sim.mem.write(addr, int(self.data[dataStart:dataStart+8], 16))
+
+      elif self.len == 8:
+         self.sim.mem.write(addr, int(self.data[dataStart:dataStart+16], 16))
+         self.sim.mem.write(addr+4, int(self.data[dataStart+16:dataStart+32], 16))
+
+      elif self.len == 16:
+         self.sim.mem.write(addr, int(self.data[0:8], 16))
+         self.sim.mem.write(addr+4, int(self.data[8:16], 16))
+         self.sim.mem.write(addr+8, int(self.data[16:24], 16))
+         self.sim.mem.write(addr+12, int(self.data[24:32], 16))
+
+      elif self.len == 32:
+         self.sim.mem.write(addr, int(self.data[0:8], 16))
+         self.sim.mem.write(addr+4, int(self.data[8:16], 16))
+         self.sim.mem.write(addr+8, int(self.data[16:24], 16))
+         self.sim.mem.write(addr+12, int(self.data[24:32], 16))
+         self.sim.mem.write(addr+16, int(self.data[32:40], 16))
+         self.sim.mem.write(addr+20, int(self.data[40:48], 16))
+         self.sim.mem.write(addr+24, int(self.data[48:56], 16))
+         self.sim.mem.write(addr+28, int(self.data[56:64], 16))
+
+      else:
+            raise Exception(f'A2L2Trans: unsupported store len={self.len}')
+
+
+# ------------------------------------------------------------------------------------------------
+# Functions
+
+def hex(n, pad=0):
+   if pad:
+      return f'000000000000000000000000{n.value.hex()[2:].upper()}'[-pad:]
+   else:
+      return n.value.hex()[2:].upper()
+
+# ------------------------------------------------------------------------------------------------
+# Tasks
+
+async def A2L2Driver(dut, sim):
+   """A2L2 node interface"""
+
+   transTypes = {
+      '00': 'IFETCH',
+      '08': 'LOAD',
+      '20': 'STORE'
+   }
+
+   ok = True
+   readPending = []
+   countReads = 0
+   mem = {}
+   sim.msg('A2L2 Driver: started.')
+
+   dut.an_ac_flh2l2_gate.value = 0
+
+   while ok and not sim.done:
+
+      await RisingEdge(dut.clk_1x)
+
+      dut.an_ac_req_ld_pop.value = 0
+      dut.an_ac_req_st_pop.value = 0
+      dut.an_ac_req_st_gather.value = 0
+
+      dut.an_ac_reld_data_coming.value = 0
+      dut.an_ac_reld_data_vld.value = 0
+      dut.an_ac_reld_ecc_err.value = 0
+      dut.an_ac_reld_ecc_err_ue.value = 0
+      dut.an_ac_reld_ditc.value = 0
+      dut.an_ac_reld_l1_dump.value = 0
+      dut.an_ac_req_spare_ctrl_a1.value = 0
+
+      if sim.threads == 1:
+         dut.an_ac_reservation_vld.value = 0
+         dut.an_ac_stcx_complete.value = 0
+         dut.an_ac_stcx_pass.value = 0
+      else:
+         for i in range(sim.threads):
+            dut.an_ac_reservation_vld[i].value = 0
+            dut.an_ac_stcx_complete[i].value = 0
+            dut.an_ac_stcx_pass[i].value = 0
+
+      dut.an_ac_sync_ack.value = 0
+      dut.an_ac_icbi_ack.value = 0
+      dut.an_ac_back_inv.value = 0
+
+      # bummer IndexError: Slice indexing is not supported
+      #dut.an_ac_reld_data[0:31].value = 0x48000000
+      #dut.an_ac_reld_data[32:63].value = 0x48000000
+      #dut.an_ac_reld_data[64:95].value = 0x48000000
+      #dut.an_ac_reld_data[96:127].value = 0x48000000
+      # bummer TypeError: Unsupported type for value assignment: <class 'str'> ('48000000480000004800000048000000')
+      #dut.an_ac_reld_data.value = '48000000480000004800000048000000'
+      #v = 0x48000000
+      # bummer TypeError: Unsupported type for value assignment: <class 'str'> ('01001000000000000000000000000000010010000000000000000000000000000100100000000000000000000000000001001000000000000000000000000000')
+      #dut.an_ac_reld_data.value = f'{v:0>32b}{v:0>32b}{v:0>32b}{v:0>32b}'
+      # otay!
+      #v1 = cocotb.binary.BinaryValue()
+      #v1.assign(f'{v:0>32b}{v:0>32b}{v:0>32b}{v:0>32b}')
+      #dut.an_ac_reld_data.value = v1.value
+
+      if dut.ac_an_req.value:             # should first check ac_an_req_pwr_token prev cyc
+
+         tt = hex(dut.ac_an_req_ttype, 2)
+         transType = transTypes[tt]
+         tid = hex(dut.ac_an_req_thread)
+         ra = hex(dut.ac_an_req_ra, 8)
+         tag = hex(dut.ac_an_req_ld_core_tag, 2)
+         lenEnc = hex(dut.ac_an_req_ld_xfr_len)
+         le = 'LE ' if dut.ac_an_req_endian.value else ''
+         wimg_w = dut.ac_an_req_wimg_w.value
+         wimg_i = dut.ac_an_req_wimg_i.value
+         wimg_m = dut.ac_an_req_wimg_m.value
+         wimg_g = dut.ac_an_req_wimg_g.value
+         wimg = 0
+         if wimg_w:
+            wimg += 8
+         if wimg_i:
+            wimg += 4
+         if wimg_m:
+            wimg += 2
+         if wimg_g:
+            wimg += 1
+
+         if transType == 'IFETCH' or transType == 'LOAD':
+            # when allowing out-of-order, schedule reld once added
+            if len(readPending) == 0:
+               reldCyc = sim.cycle + 6                   # const for now
+            else:
+               reldCyc = readPending[-1].cycD + 4        # worst-case const for now
+            trans = A2L2Trans(sim, tid, int(tt, 16), int(tag, 16), int(ra, 16), int(lenEnc, 16), wimg, reldCyc)
+            readPending.append(trans)
+            sim.msg(f'T{tid} {transType} {ra} tag={tag} len={trans.len} {le}WIMG:{wimg:X} reld data:{trans.cycD}')
+         elif transType == 'STORE':
+            # should verify st_data_pwr_token prev cycle
+            be = hex(dut.ac_an_st_byte_enbl, 8)
+            data = hex(dut.ac_an_st_data, 64)
+            trans = A2L2Trans(sim, tid, int(tt, 16), int(tag, 16), int(ra, 16), int(lenEnc, 16), wimg, None, be=be, data=data)
+            sim.msg(f'T{tid} {transType} {ra} tag={tag} len={trans.len} be={be} data={data} {le}WIMG:{wimg:X}')
+            trans.doStore()
+            #assert False, 'got a store'
+
+      # data early indicator (d-3)
+      dut.an_ac_reld_data_coming.value = 0
+      for i in range(len(readPending)):
+         trans = readPending[i]
+         if trans.cycC == sim.cycle:
+            dut.an_ac_reld_data_coming.value = 1
+            if trans.xferNum == 0 and trans.xfers == 4:  # 4 beats b2b - need diff scheduling for all modes
+               trans.cycC += 2
+
+      # data valid indicator (d-2)
+      dut.an_ac_reld_data_vld.value = 0
+      dut.an_ac_reld_core_tag.value = 0x1F
+      dut.an_ac_reld_ditc.value = 1
+      dut.an_ac_reld_qw.value = 3
+      dut.an_ac_reld_crit_qw.value = 1
+
+      for i in range(len(readPending)):
+         trans = readPending[i]
+         if trans.cycV == sim.cycle:
+            trans.xferNum += 1
+            dut.an_ac_reld_data_vld.value = 1
+            dut.an_ac_reld_core_tag.value = trans.tag
+            dut.an_ac_reld_ditc.value = 1 if trans.ditc else 0
+            dut.an_ac_reld_qw.value = trans.xferNum - 1
+            dut.an_ac_reld_crit_qw.value = 1 if trans.xferNum == trans.xferCrit else 0
+            if trans.xferNum < 4 and trans.xfers == 4:
+               trans.cycV += 1
+
+      # data beat
+      if len(readPending) > 0 and readPending[0].cycD == sim.cycle:   # ordered
+
+         trans = readPending[0]
+         w0,w1,w2,w3,beatNum = trans.readXfer()
+
+         v1 = cocotb.binary.BinaryValue()
+         v1.assign(f'{w0:0>32b}{w1:0>32b}{w2:0>32b}{w3:0>32b}')
+         dut.an_ac_reld_data.value = v1.value
+
+         sim.msg(f'RELD tag={trans.tag:02X} {w0:08X}{w1:08X}{w2:08X}{w3:08X} {beatNum}of{trans.xfers}{" crit" if beatNum == trans.xferCrit else ""}')
+
+         if beatNum == trans.xfers:
+            trans.done = True
+            countReads += 1   #wtf do this in monitor
+            if len(readPending) == 1:
+               readPending = []
+            else:
+               readPending = readPending[1:]
+            dut.an_ac_req_ld_pop.value = 1   #wtf can randomize, etc.
+
+
+# A2L2 Checker
+# check protocol, etc.
+async def A2L2Checker(dut, sim):
+   """A2L2 interface checker """
+
+   me = 'A2L2 Checker'
+   ok = True
+   sim.msg(f'{me}: started.')
+
+   while ok:
+      await RisingEdge(dut.clk_1x)
+
+
+# A2L2 Monitor
+# count transactions, etc.
+# fail on bad addresses
+async def A2L2Monitor(dut, sim):
+   """A2L2 interface monitor"""
+
+   me = 'A2L2 Monitor'
+   ok = True
+   start = len(sim.config.a2l2.badAddr) > 0
+   sim.msg(f'{me}: started.')
+
+   while start and ok:
+
+      await RisingEdge(dut.clk_1x)
+
+      if dut.ac_an_req.value:             # should first check ac_an_req_pwr_token prev cyc
+
+         tt = hex(dut.ac_an_req_ttype, 2)
+         if tt == '00':    #wtf someone should make this a enum/class
+            ra = dut.ac_an_req_ra.value.integer
+            for i in range(len(sim.config.a2l2.badAddr)):
+               blk = sim.config.a2l2.badAddr[i]
+               if 'I' in blk[2].upper():
+                  blkStart = int(blk[0], 16)
+                  blkEnd = int(blk[1], 16)
+                  if ra >= blkStart and ra <= blkEnd:
+                     ok = False
+                     assert False, (f'{me}: Bad IFetch @={ra:08X}')  #wtf want this to end back in main code for summary
+
+class A2L2:
+   driver = A2L2Driver
+   checker = A2L2Checker
+   monitor = A2L2Monitor
+
+   def __init__(self):
+      pass

dev/sim/coco/Makefile.icarus

@@ -0,0 +1,49 @@
+# a2o tb
+# make -f Makefile.icarus build  # rebuild and sim and fst
+# make -f Makefile.icarus run    # sim and fst
+# make -f Makefile.icarus        # sim
+
+#COCOTB_LOG_LEVEL=DEBUG
+#GPI_EXTRA=vpi
+
+#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM
+
+#SIM_BUILD ?= build
+SIM ?= icarus
+
+# options
+#COCOTB_HDL_TIMEUNIT ?= 1ns
+#COCOTB_HDL_TIMEPRECISION ?= 1ps
+#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM
+
+# icarus
+#
+# includes are needed for *.vh
+# unisims is for FPGA RAMs
+# coco forces -g2012 for some reason, and appends it after COMPILE_ARGS below! issue #781
+
+VERILOG_ROOT = ../../verilog
+
+COMPILE_ARGS = -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work
+
+# other options
+
+# rtl
+TOPLEVEL_LANG = verilog
+# top-level to enable trace, etc.
+VERILOG_SOURCES = ./cocotb_icarus.v
+TOPLEVEL = cocotb_icarus
+
+# python test
+MODULE = tb
+
+# cocotb make rules
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+build: clean sim fst
+
+run: sim fst
+
+fst:
+	vcd2fst wtf-coco.vcd wtf-coco.fst
+	rm wtf-coco.vcd

dev/sim/coco/Makefile.icarus.smt2

@@ -0,0 +1,44 @@
+# a2o smt2 tb
+# make -f Makefile.icarus build  # rebuild and sim and fst
+# make -f Makefile.icarus run    # sim and fst
+# make -f Makefile.icarus        # sim
+
+SIM_BUILD ?= build_smt2
+SIM ?= icarus
+
+# options
+#COCOTB_HDL_TIMEUNIT ?= 1ns
+#COCOTB_HDL_TIMEPRECISION ?= 1ps
+#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM
+
+# icarus
+#
+# includes are needed for *.vh
+# unisims is for FPGA RAMs
+# coco forces -g2012 for some reason, and appends it after COMPILE_ARGS below! issue #781
+
+VERILOG_ROOT = ../../verilog
+
+COMPILE_ARGS = -I$(VERILOG_ROOT)/smt2 -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work
+
+# other options
+
+# rtl
+TOPLEVEL_LANG = verilog
+# top-level to enable trace, etc.
+VERILOG_SOURCES = ./cocotb_icarus.v
+TOPLEVEL = cocotb_icarus
+
+# python test
+MODULE = tb
+
+# cocotb make rules
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+build: clean sim fst
+
+run: sim fst
+
+fst:
+	vcd2fst wtf-coco.vcd wtf-coco.fst
+	rm wtf-coco.vcd

dev/sim/coco/Makefile.sweetpea

@@ -0,0 +1,45 @@
+# a2o tb
+# make -f Makefile.icarus build  # rebuild and sim and fst
+# make -f Makefile.icarus run    # sim and fst
+# make -f Makefile.icarus        # sim
+
+#COCOTB_LOG_LEVEL=DEBUG
+#GPI_EXTRA=vpi
+
+#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM
+
+SIM_BUILD ?= build_sweetpea
+SIM ?= icarus
+
+# options
+#COCOTB_HDL_TIMEUNIT ?= 1ns
+#COCOTB_HDL_TIMEPRECISION ?= 1ps
+#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM
+
+# icarus
+
+VERILOG_ROOT = ../../verilog
+
+COMPILE_ARGS = -I$(VERILOG_ROOT)/sweetpea -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work
+
+# other options
+
+# rtl
+TOPLEVEL_LANG = verilog
+# top-level to enable trace, etc.
+VERILOG_SOURCES = ./cocotb_icarus.v
+TOPLEVEL = cocotb_icarus
+
+# python test
+MODULE = tb
+
+# cocotb make rules
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+build: clean sim fst
+
+run: sim fst
+
+fst:
+	vcd2fst wtf-coco.vcd wtf-coco.fst
+	rm wtf-coco.vcd

dev/sim/coco/Makefile.verilator

@@ -0,0 +1,30 @@
+# a2o tb
+
+SIM_BUILD ?= sim_build_verilator
+SIM ?= verilator
+
+# set precision
+#COCOTB_HDL_TIMEPRECISION ?= 1ns
+
+# verilator
+COMPILE_ARGS = --error-limit 1 --language 1364-2001 -Wno-fatal -Wno-LITENDIAN -Iverilog/work -Iverilog/trilib -Iverilog/unisims
+
+# coverage
+#EXTRA_ARGS += --coverage
+# tracing
+EXTRA_ARGS += --trace
+
+# rtl
+TOPLEVEL_LANG = verilog
+VERILOG_SOURCES += verilog/trilib_clk1x/*.v
+VERILOG_SOURCES += verilog/trilib/*.v
+VERILOG_SOURCES += verilog/work/*.v
+
+# rtl top
+TOPLEVEL = c
+
+# python test
+MODULE = tbv
+
+# cocotb make rules
+include $(shell cocotb-config --makefiles)/Makefile.sim

dev/sim/coco/OPEnv.py

@@ -0,0 +1,117 @@
+# OP Environment
+
+import cocotb
+from cocotb.triggers import Timer
+from cocotb.handle import Force
+from cocotb.handle import Release
+
+from dotmap import DotMap
+
+# ------------------------------------------------------------------------------------------------
+# Classes
+
+class Sim(DotMap):
+
+   def msg(self, m):
+     self.dut._log.info(f'[{self.cycle:08d}] {m}')  #wtf do multiline if /n in m
+
+   def __init__(self, dut, cfg=None):
+      super().__init__()
+      self.dut = dut
+      # defaults
+      self.memFiles = ['../mem/boot_ieq1.bin.hex'] #wtf cmdline parm
+      self.threads = None
+      self.resetCycle = 10
+      self.hbCycles = 100
+      self.clk2x = True
+      self.clk4x = False
+      self.resetAddr = 0xFFFFFFFC
+      self.resetOp = 0x48000002
+      self.maxCycles = 1500
+      self.memFiles = None
+      self.config = DotMap()
+      self.config.core = DotMap({
+         'creditsLd': None,
+         'creditsSt': None,
+         'creditsLdStSingle': False
+      })
+      self.config.a2l2 = DotMap({
+         'badAddr': [('E0','E0', 'IRW')]
+      })
+      # json
+      if cfg is not None:
+         pass
+
+      # runtime
+      self.cycle = 0
+      self.ok = True
+      self.fail = None
+      self.done = False
+
+      if self.threads is None:
+         try:
+            v = dut.an_ac_pm_thread_stop[1].value
+            self.threads = 2
+         except:
+            self.threads = 1
+         self.msg(f'Set threads={self.threads}.')
+
+class TransQ(DotMap):
+   def __init__(self):
+      super().__init__()
+
+class Memory(DotMap):
+
+   def __init__(self, sim, default=0, logStores=True):
+      super().__init__()
+      self.sim = sim
+      self.data = {}
+      self.le = False
+      self.default = default  # default word data for unloaded
+      self.logStores = logStores
+
+   def loadFile(self, filename, format='ascii', addr=0, le=0):
+      # format # binary, ascii, ascii w/addr
+      # le: reverse bytes
+      try:
+         if format == 'ascii':
+            with open(filename, 'r') as f:
+               lines = f.readlines()
+               for line in lines:
+                  self.data[addr] = int(line, 16)  # key is int
+                  addr += 4
+         elif format == 'binary':
+            pass
+         elif format == 'addrdata':
+            pass
+      except Exception as e:
+         self.sim.msg(f'Error reading {filename}:\n{e}')
+         raise IOError
+
+   # word-aligned byte address
+   def read(self, addr):
+      try:
+         addr = addr + 0
+      except:
+         addr = int(addr, 16)
+      if addr in self.data:
+         return self.data[addr]
+      else:
+         return self.default
+
+   # word-aligned byte address + data
+   def write(self, addr, data):
+      try:
+         addr = addr + 0
+      except:
+         addr = int(addr, 16)
+      try:
+         data = data + 0
+      except:
+         data = int(data, 16)
+      if self.logStores:
+         if addr not in self.data:
+            self.sim.msg(f'Mem Update: @{addr:08X} XXXXXXXX->{data:08X}')
+         else:
+            self.sim.msg(f'Mem Update: @{addr:08X} {self.data[addr]:08X}->{data:08X}')
+      self.data[addr] = data

dev/sim/coco/boot.lst

@@ -0,0 +1,913 @@
+   1              	# © IBM Corp. 2020
+   2              	# Licensed under and subject to the terms of the CC-BY 4.0
+   3              	# license (https://creativecommons.org/licenses/by/4.0/legalcode).
+   4              	# Additional rights, including the right to physically implement a softcore
+   5              	# that is compliant with the required sections of the Power ISA
+   6              	# Specification, will be available at no cost via the OpenPOWER Foundation.
+   7              	# This README will be updated with additional information when OpenPOWER's
+   8              	# license is available.
+   9              	
+  10              	# boot kernel
+  11              	#  set up translations
+  12              	#  set up timer facilities
+  13              	#  set up threads
+  14              	#  call user code
+  15              	#  process user rc
+  16              	
+  17              	# todo:
+  18              	# 1. skip_printf_init flag should be threaded
+  19              	
+  20              	.include "defines.s"
+   1              	# © IBM Corp. 2020
+   2              	# Licensed under and subject to the terms of the CC-BY 4.0
+   3              	# license (https://creativecommons.org/licenses/by/4.0/legalcode). 
+   4              	# Additional rights, including the right to physically implement a softcore 
+   5              	# that is compliant with the required sections of the Power ISA 
+   6              	# Specification, will be available at no cost via the OpenPOWER Foundation. 
+   7              	# This README will be updated with additional information when OpenPOWER's 
+   8              	# license is available.
+   9              	
+  10              	#-----------------------------------------
+  11              	# Defines
+  12              	#-----------------------------------------
+  13              	
+  14              	# Regs
+  15              	
+  16              	.set    r0,  0
+  17              	.set    r1,  1
+  18              	.set    r2,  2
+  19              	.set    r3,  3
+  20              	.set    r4,  4
+  21              	.set    r5,  5
+  22              	.set    r6,  6
+  23              	.set    r7,  7
+  24              	.set    r8,  8
+  25              	.set    r9,  9
+  26              	.set    r10,10
+  27              	.set    r11,11
+  28              	.set    r12,12
+  29              	.set    r13,13
+  30              	.set    r14,14
+  31              	.set    r15,15
+  32              	.set    r16,16
+  33              	.set    r17,17
+  34              	.set    r18,18
+  35              	.set    r19,19
+  36              	.set    r20,20
+  37              	.set    r21,21
+  38              	.set    r22,22
+  39              	.set    r23,23
+  40              	.set    r24,24
+  41              	.set    r25,25
+  42              	.set    r26,26
+  43              	.set    r27,27
+  44              	.set    r28,28
+  45              	.set    r29,29
+  46              	.set    r30,30
+  47              	.set    r31,31
+  48              	
+  49              	.set    f0,  0
+  50              	.set    f1,  1
+  51              	.set    f2,  2
+  52              	.set    f3,  3
+  53              	.set    f4,  4
+  54              	.set    f5,  5
+  55              	.set    f6,  6
+  56              	.set    f7,  7
+  57              	.set    f8,  8
+  58              	.set    f9,  9
+  59              	.set    f10,10
+  60              	.set    f11,11
+  61              	.set    f12,12
+  62              	.set    f13,13
+  63              	.set    f14,14
+  64              	.set    f15,15
+  65              	.set    f16,16
+  66              	.set    f17,17
+  67              	.set    f18,18
+  68              	.set    f19,19
+  69              	.set    f20,20
+  70              	.set    f21,21
+  71              	.set    f22,22
+  72              	.set    f23,23
+  73              	.set    f24,24
+  74              	.set    f25,25
+  75              	.set    f26,26
+  76              	.set    f27,27
+  77              	.set    f28,28
+  78              	.set    f29,29
+  79              	.set    f30,30
+  80              	.set    f31,31
+  81              	
+  82              	.set    cr0, 0
+  83              	.set    cr1, 1
+  84              	.set    cr2, 2
+  85              	.set    cr3, 3
+  86              	.set    cr4, 4
+  87              	.set    cr5, 5
+  88              	.set    cr6, 6
+  89              	.set    cr7, 7
+  90              	
+  91              	# SPR numbers
+  92              	
+  93              	.set    srr0, 26
+  94              	.set    srr1, 27
+  95              	.set    epcr, 307
+  96              	.set    tar, 815
+  97              	
+  98              	.set    dbsr, 304
+  99              	.set    dbcr0, 308
+ 100              	.set    dbcr1, 309
+ 101              	.set    dbcr2, 310
+ 102              	.set    dbcr3, 848
+ 103              	
+ 104              	.set    ivpr, 63
+ 105              	
+ 106              	.set    iucr0, 1011
+ 107              	.set    iucr1, 883
+ 108              	.set    iucr2, 884
+ 109              	
+ 110              	.set    iudbg0, 888
+ 111              	.set    iudbg1, 889
+ 112              	.set    iudbg2, 890
+ 113              	.set    iulfsr, 891
+ 114              	.set    iullcr, 892
+ 115              	
+ 116              	.set    mmucr0, 1020
+ 117              	.set    mmucr1, 1021
+ 118              	.set    mmucr2, 1022
+ 119              	.set    mmucr3, 1023
+ 120              	
+ 121              	.set    tb, 268
+ 122              	.set    tbl, 284
+ 123              	.set    tbh, 285
+ 124              	
+ 125              	.set    dec, 22
+ 126              	.set    udec, 550
+ 127              	.set    tsr, 336
+ 128              	.set    tcr, 340
+ 129              	
+ 130              	.set    xucr0, 1014
+ 131              	.set    xucr1, 851
+ 132              	.set    xucr2, 1016
+ 133              	.set    xucr3, 852
+ 134              	.set    xucr4, 853
+ 135              	
+ 136              	.set    tens, 438
+ 137              	.set    tenc, 439
+ 138              	.set    tensr, 437
+ 139              	
+ 140              	.set    pid, 48
+ 141              	.set    pir, 286
+ 142              	.set    pvr, 287
+ 143              	.set    tir, 446
+ 144              	
+  21              	
+  22              	.section .text
+  23              	start:
+  24              	
+  25              	int_000:
+  26 0000 48000400 	      b         boot_start
+  27              	
+  28              	# critical input
+  29 0004 4800001C 	.align 5
+  29      60000000 
+  29      60000000 
+  29      60000000 
+  29      60000000 
+  30              	int_020:
+  31 0020 48000000 	      b         .
+  32              	
+  33              	# debug
+  34 0024 4800001C 	.align 5
+  34      60000000 
+  34      60000000 
+  34      60000000 
+  34      60000000 
+  35              	int_040:
+  36 0040 48000000 	      b         .
+  37              	
+  38              	# dsi
+  39 0044 4800001C 	.align 5
+  39      60000000 
+  39      60000000 
+  39      60000000 
+  39      60000000 
+  40              	int_060:
+  41 0060 48000000 	      b         .
+  42              	
+  43              	# isi
+  44 0064 4800001C 	.align 5
+  44      60000000 
+  44      60000000 
+  44      60000000 
+  44      60000000 
+  45              	int_080:
+  46 0080 48000000 	      b         .
+  47              	
+  48              	# external
+  49 0084 4800001C 	.align 5
+  49      60000000 
+  49      60000000 
+  49      60000000 
+  49      60000000 
+  50              	int_0A0:
+  51 00a0 48000000 	      b         .
+  52              	
+  53              	# alignment
+  54 00a4 4800001C 	.align 5
+  54      60000000 
+  54      60000000 
+  54      60000000 
+  54      60000000 
+  55              	int_0C0:
+  56 00c0 48000000 	      b         .
+  57              	
+  58              	# program
+  59 00c4 4800001C 	.align 5
+  59      60000000 
+  59      60000000 
+  59      60000000 
+  59      60000000 
+  60              	int_0E0:
+  61 00e0 48000000 	      b         .
+  62              	
+  63              	# fp unavailable
+  64 00e4 4800001C 	.align 5
+  64      60000000 
+  64      60000000 
+  64      60000000 
+  64      60000000 
+  65              	int_100:
+  66 0100 48000000 	      b         .
+  67              	
+  68              	# sc
+  69 0104 4800001C 	.align 5
+  69      60000000 
+  69      60000000 
+  69      60000000 
+  69      60000000 
+  70              	int_120:
+  71 0120 48000CE0 	      b         int_120_handler
+  72              	
+  73              	# apu unavailable
+  74 0124 4800001C 	.align 5
+  74      60000000 
+  74      60000000 
+  74      60000000 
+  74      60000000 
+  75              	int_140:
+  76 0140 48000000 	      b         .
+  77              	
+  78              	# decrementer
+  79 0144 4800001C 	.align 5
+  79      60000000 
+  79      60000000 
+  79      60000000 
+  79      60000000 
+  80              	int_160:
+  81 0160 48000000 	      b         .
+  82              	
+  83              	# fit
+  84 0164 4800001C 	.align 5
+  84      60000000 
+  84      60000000 
+  84      60000000 
+  84      60000000 
+  85              	int_180:
+  86 0180 48000000 	      b         .
+  87              	
+  88              	# watchdog
+  89 0184 4800001C 	.align 5
+  89      60000000 
+  89      60000000 
+  89      60000000 
+  89      60000000 
+  90              	int_1A0:
+  91 01a0 48000000 	      b         .
+  92              	
+  93              	# dtlb
+  94 01a4 4800001C 	.align 5
+  94      60000000 
+  94      60000000 
+  94      60000000 
+  94      60000000 
+  95              	int_1C0:
+  96 01c0 48000000 	      b         .
+  97              	
+  98              	# itlb
+  99 01c4 4800001C 	.align 5
+  99      60000000 
+  99      60000000 
+  99      60000000 
+  99      60000000 
+ 100              	int_1E0:
+ 101 01e0 48000000 	      b         .
+ 102              	
+ 103              	# vector unavailable
+ 104 01e4 4800001C 	.align 5
+ 104      60000000 
+ 104      60000000 
+ 104      60000000 
+ 104      60000000 
+ 105              	int_200:
+ 106 0200 48000000 	      b         .
+ 107              	
+ 108              	#
+ 109 0204 4800001C 	.align 5
+ 109      60000000 
+ 109      60000000 
+ 109      60000000 
+ 109      60000000 
+ 110              	int_220:
+ 111 0220 48000000 	      b         .
+ 112              	
+ 113              	#
+ 114 0224 4800001C 	.align 5
+ 114      60000000 
+ 114      60000000 
+ 114      60000000 
+ 114      60000000 
+ 115              	int_240:
+ 116 0240 48000000 	      b         .
+ 117              	
+ 118              	#
+ 119 0244 4800001C 	.align 5
+ 119      60000000 
+ 119      60000000 
+ 119      60000000 
+ 119      60000000 
+ 120              	int_260:
+ 121 0260 48000000 	      b         .
+ 122              	
+ 123              	# doorbell
+ 124 0264 4800001C 	.align 5
+ 124      60000000 
+ 124      60000000 
+ 124      60000000 
+ 124      60000000 
+ 125              	int_280:
+ 126 0280 48000000 	      b         .
+ 127              	
+ 128              	# doorbell critical
+ 129 0284 4800001C 	.align 5
+ 129      60000000 
+ 129      60000000 
+ 129      60000000 
+ 129      60000000 
+ 130              	int_2A0:
+ 131 02a0 48000000 	      b         .
+ 132              	
+ 133              	# doorbell guest
+ 134 02a4 4800001C 	.align 5
+ 134      60000000 
+ 134      60000000 
+ 134      60000000 
+ 134      60000000 
+ 135              	int_2C0:
+ 136 02c0 48000000 	      b         .
+ 137              	
+ 138              	# doorbell guest critical
+ 139 02c4 4800001C 	.align 5
+ 139      60000000 
+ 139      60000000 
+ 139      60000000 
+ 139      60000000 
+ 140              	int_2E0:
+ 141 02e0 48000000 	      b         .
+ 142              	
+ 143              	# hvsc
+ 144 02e4 4800001C 	.align 8
+ 144      60000000 
+ 144      60000000 
+ 144      60000000 
+ 144      60000000 
+ 145              	int_300:
+ 146 0300 48000A00 	      b         int_300_handler
+ 147              	
+ 148              	# hvpriv
+ 149 0304 4800001C 	.align 5
+ 149      60000000 
+ 149      60000000 
+ 149      60000000 
+ 149      60000000 
+ 150              	int_320:
+ 151 0320 48000000 	      b         .
+ 152              	
+ 153              	# lrat
+ 154 0324 4800001C 	.align 5
+ 154      60000000 
+ 154      60000000 
+ 154      60000000 
+ 154      60000000 
+ 155              	int_340:
+ 156 0340 48000000 	      b         .
+ 157              	
+ 158              	# -------------------------------------------------------------------------------------------------
+ 159              	# initial translation
+ 160              	# both erats:
+ 161              	# 00000000 1M: (boot)
+ 162              	# 10000000 1M: (test)
+ 163              	
+ 164 0344 480000BC 	.align 8
+ 164      60000000 
+ 164      60000000 
+ 164      60000000 
+ 164      60000000 
+ 165              	boot_start:
+ 166              	
+ 167 0400 7CBE6AA6 	      mfspr     r5,tir           # who am i?
+ 168 0404 2C250000 	      cmpdi     r5,0x00          # skip unless T0
+ 169 0408 408200EC 	      bne       init_t123
+ 170              	
+ 171 040c 3C608C00 	      lis       r3,0x8C00        # 32=ecl 36:37=tlbsel (10=i, 11=d)
+ 172              	# derat 31 @00000000
+ 173              	
+ 174 0410 3800001F 	      li        r0,0x001F        # entry #31
+ 175 0414 38400015 	      li        r2,0x0015        # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
+ 176 0418 38800000 	      li        r4,0             # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
+ 177 041c 3900025F 	      li        r8,0x025F        # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63   s
+ 178              	
+ 179 0420 7C7CFBA6 	      mtspr     mmucr0,r3
+ 180 0424 7C4011A6 	      eratwe    r2,r0,2
+ 181 0428 7C8009A6 	      eratwe    r4,r0,1
+ 182 042c 7D0001A6 	      eratwe    r8,r0,0
+ 183 0430 4C00012C 	      isync
+ 184              	
+ 185 0434 81400A08 	      lwz       r10,CONFIG+S_ERATW2(r0)  # load parms for erat settings
+ 186              	
+ 187              	# derat 30  @100000000
+ 188              	
+ 189 0438 3800001E 	      li        r0,0x001E        # entry #30
+ 190 043c 3C801000 	      lis       r4,0x1000        # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
+ 191 0440 3900025F 	      li        r8,0x025F        # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63   s
+ 192 0444 65081000 	      oris      r8,r8,0x1000
+ 193              	
+ 194 0448 7D4011A6 	      eratwe    r10,r0,2
+ 195 044c 7C8009A6 	      eratwe    r4,r0,1
+ 196 0450 7D0001A6 	      eratwe    r8,r0,0
+ 197 0454 4C00012C 	      isync
+ 198              	
+ 199 0458 3C608800 	      lis       r3,0x8800        # 32=ecl 36:37=tlbsel (10=i, 11=d)
+ 200              	# ierat 15  @00000000
+ 201              	
+ 202 045c 3800000F 	      li        r0,0x000F        # entry #15
+ 203 0460 3840003F 	      li        r2,0x003F        # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
+ 204 0464 38800000 	      li        r4,0             # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
+ 205 0468 3900025F 	      li        r8,0x025F        # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63   s
+ 206              	
+ 207 046c 7C7CFBA6 	      mtspr     mmucr0,r3
+ 208 0470 7C4011A6 	      eratwe    r2,r0,2
+ 209 0474 7C8009A6 	      eratwe    r4,r0,1
+ 210 0478 7D0001A6 	      eratwe    r8,r0,0
+ 211 047c 4C00012C 	      isync
+ 212              	
+ 213              	 # *** leave the init'd entry 14 for MT access to FFFFFFC0
+ 214              	 # ierat 13  @10000000
+ 215              	
+ 216 0480 3800000D 	      li        r0,0x000D        # entry #13
+ 217 0484 3C801000 	      lis       r4,0x1000        # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
+ 218 0488 3900025F 	      li        r8,0x025F        # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63   s
+ 219 048c 65081000 	      oris      r8,r8,0x1000
+ 220              	
+ 221 0490 7D4011A6 	      eratwe    r10,r0,2
+ 222 0494 7C8009A6 	      eratwe    r4,r0,1
+ 223 0498 7D0001A6 	      eratwe    r8,r0,0
+ 224 049c 4C00012C 	      isync
+ 225              	
+ 226              	# -------------------------------------------------------------------------------------------------
+ 227              	# init
+ 228              	#
+ 229              	
+ 230              	# T0-only
+ 231              	# set up any core facilities, then enable the others if config'd
+ 232              	init_t0:
+ 233              	
+ 234              	# switch to 64b
+ 235              	
+ 236 04a0 81400A00 	      lwz       r10,CONFIG+S_MSR(r0)
+ 237 04a4 7D400124 	      mtmsr     r10
+ 238 04a8 4C00012C 	      isync
+ 239              	
+ 240              	# other init
+ 241              	
+ 242 04ac 3C200300 	      lis       r1,0x0300        # icm=gicm=1
+ 243 04b0 7C334BA6 	      mtspr     epcr,r1
+ 244              	
+ 245              	# set up timer facs
+ 246              	
+ 247 04b4 38200000 	      li        r1,0             # clear
+ 248 04b8 7C3603A6 	      mtspr     dec,r1
+ 249 04bc 7C3D43A6 	      mtspr     tbh,r1
+ 250 04c0 7C3C43A6 	      mtspr     tbl,r1
+ 251              	
+ 252 04c4 3C40FE00 	      lis       r2,0xFE00        # mask: clear enw,wis,wrs,dis,fis,udis
+ 253 04c8 7C5053A6 	      mtspr     tsr,r2
+ 254              	
+ 255 04cc 7C56FAA6 	      mfspr     r2,xucr0
+ 256 04d0 70420200 	      andi.     r2,r2,0x0200     # set tcs=0
+ 257 04d4 7C56FBA6 	      mtspr     xucr0,r2
+ 258              	
+ 259 04d8 7C3053A6 	      mtspr     tsr,r1           # clear tsr
+ 260 04dc 7C3453A6 	      mtspr     tcr,r1           # disable all timers
+ 261              	
+ 262              	# set thread configuration
+ 263              	
+ 264 04e0 80200A04 	      lwz       r1,CONFIG+S_FLAGS(r0)
+ 265 04e4 7021000F 	      andi.     r1,r1,0xF
+ 266 04e8 7C366BA6 	      mtspr     tens,r1          # 60:63 = tid 3:0 enabled
+ 267              	      #not       r1,r1
+ 268              	      #mtspr     tenc,r1         # in case T0 is marked disabled
+ 269 04ec 4C00012C 	      isync
+ 270              	
+ 271 04f0 48000014 	      b         boot_complete
+ 272              	
+ 273              	# except T0
+ 274              	# just worry about myself
+ 275              	
+ 276              	init_t123:
+ 277              	
+ 278              	# switch to 64b
+ 279              	
+ 280 04f4 81400A00 	      lwz       r10,CONFIG+S_MSR(r0)
+ 281 04f8 7D400124 	      mtmsr     r10
+ 282 04fc 4C00012C 	      isync
+ 283              	
+ 284 0500 48000004 	      b         boot_complete
+ 285              	
+ 286              	# -------------------------------------------------------------------------------------------------
+ 287              	boot_complete:
+ 288              	
+ 289              	# set up thread and hop to it
+ 290              	
+ 291 0504 80200A04 	      lwz       r1,CONFIG+S_FLAGS(r0)
+ 292 0508 74218000 	      andis.    r1,r1,0x8000     # 1=skip initial printf init
+ 293 050c 40820008 	      bne       boot_complete_1
+ 294 0510 480006F1 	      bl        printf_reset     # wipe buffer
+ 295              	
+ 296              	boot_complete_1:
+ 297              	
+ 298 0514 80200A04 	      lwz       r1,CONFIG+S_FLAGS(r0)
+ 299 0518 3C407FFF 	      lis       r2,0x7FFF        # clear printf flag
+ 300 051c 6042FFFF 	      ori       r2,r2,0xFFFF
+ 301 0520 7C211038 	      and       r1,r1,r2
+ 302 0524 90200A04 	      stw       r1,CONFIG+S_FLAGS(r0)
+ 303              	
+ 304 0528 7CBE6AA6 	      mfspr     r5,tir           # who am i?
+ 305 052c 78A53664 	      sldi      r5,r5,6          # 64B offset
+ 306 0530 38A50A80 	      addi      r5,r5,CONFIG+T_CONFIG
+ 307              	
+ 308 0534 81650000 	      lwz       r11,T_MSR(r5)
+ 309 0538 E9850008 	      ld        r12,T_STACK(r5)
+ 310 053c E9A50010 	      ld        r13,T_ENTRY(r5)
+ 311              	
+ 312 0540 80200A04 	      lwz       r1,CONFIG+S_FLAGS(r0)
+ 313 0544 70210010 	      andi.     r1,r1,FLAG_EOT_SC
+ 314 0548 4182001C 	      beq       eot_blr
+ 315              	
+ 316              	eot_sc:
+ 317              	
+ 318 054c 80400A0C 	      lwz       r2,CONFIG+S_EOT_SC(r0)
+ 319 0550 3C204400 	      lis       r1,0x4400        # 'sc 1'
+ 320 0554 60210012 	      ori       r1,r1,0022
+ 321 0558 F8220000 	      std       r1,0x0(r2)
+ 322 055c 7C2803A6 	      mtlr      r1               # prog will blr to sc
+ 323 0560 48000014 	      b         process_start
+ 324              	
+ 325              	eot_blr:
+ 326              	
+ 327 0564 48000005 	      bl        4
+ 328 0568 7C2802A6 	      mflr      r1
+ 329 056c 38210030 	      addi      r1,r1,0x30       # !!!!!!!!!!!!!!! <-- WARNING!
+ 330 0570 7C2803A6 	      mtlr      r1               # prog will blr to exec_complete
+ 331              	
+ 332              	process_start:
+ 333              	
+ 334 0574 7D7B03A6 	      mtspr     srr1,r11         # msr
+ 335 0578 7DBA03A6 	      mtspr     srr0,r13         # @entry
+ 336 057c 7D816378 	      mr        r1,r12           # @stack
+ 337 0580 7C7E6AA6 	      mfspr     r3,tir           # tid - main(tid) if yall want it
+ 338              	
+ 339 0584 7C4C42A6 	      mfspr     r2,tb
+ 340 0588 F8450030 	      std       r2,T_TIMER_START(r5)
+ 341 058c 4C000064 	      rfi
+ 342 0590 60000000 	      nop                        # !!!!!!!!!!!!!!! pads for lr calc
+ 343 0594 60000000 	      nop
+ 344 0598 60000000 	      nop
+ 345              	
+ 346              	# -------------------------------------------------------------------------------------------------
+ 347              	exec_complete:
+ 348              	# allow blr to here, or it will be entered by sc directly
+ 349              	
+ 350              	# user blr'd here...
+ 351 059c 44000022 	      sc        1                # hvsc back to sup state
+ 352              	
+ 353              	exec_complete_sup:
+ 354 05a0 7CBE6AA6 	      mfspr     r5,tir           # who am i?
+ 355 05a4 78A53664 	      sldi      r5,r5,6          # 64B offset
+ 356 05a8 38A50A80 	      addi      r5,r5,CONFIG+T_CONFIG
+ 357              	
+ 358 05ac 7C4C42A6 	      mfspr     r2,tb
+ 359 05b0 F8450038 	      std       r2,T_TIMER_END(r5)
+ 360              	
+ 361 05b4 2C230000 	      cmpdi     r3,0             # check rc
+ 362 05b8 41820148 	      beq       pass
+ 363 05bc 48000044 	      b         fail
+ 364              	
+ 365              	# -------------------------------------------------------------------------------------------------
+ 366              	# dead zone
+ 367 05c0 48000040 	.align 8
+ 367      60000000 
+ 367      60000000 
+ 367      60000000 
+ 367      60000000 
+ 368              	fail:
+ 369 0600 48000000 	      b         .
+ 370              	
+ 371              	# -------------------------------------------------------------------------------------------------
+ 372              	# happy ending
+ 373 0604 480000FC 	.align 8
+ 373      60000000 
+ 373      60000000 
+ 373      60000000 
+ 373      60000000 
+ 374              	pass:
+ 375 0700 48000000 	      b         .
+ 376              	
+ 377              	# -------------------------------------------------------------------------------------------------
+ 378              	
+ 379              	# dec
+ 380 0704 480000FC 	.align 11
+ 380      60000000 
+ 380      60000000 
+ 380      60000000 
+ 380      60000000 
+ 381              	int_800:
+ 382 0800 48000000 	      b         .
+ 383              	
+ 384              	# perf
+ 385 0804 4800001C 	.align 5
+ 385      60000000 
+ 385      60000000 
+ 385      60000000 
+ 385      60000000 
+ 386              	int_820:
+ 387 0820 48000000 	      b         .
+ 388              	
+ 389              	.set CONFIG,0x0A00
+ 390              	# -------------------------------------------------------------------------------------------------
+ 391              	# config info
+ 392 0824 480001DC 	.align 9
+ 392      60000000 
+ 392      60000000 
+ 392      60000000 
+ 392      60000000 
+ 393              	
+ 394 0a00 8002B000 	      .long  0x8002B000          # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
+ 395 0a04 80000001 	      .long  0x80000001          # flags: skip_printf_init=0 eot_sc=27 thr_en=28:31(T3:T0)
+ 396 0a08 000000BF 	      .long  0x000000BF          # erat w2 (test)   # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wi
+ 397 0a0c 10000000 	      .long  0x10000000          # @user eot sc
+ 398              	
+ 399              	# per-thread configs (64B each)
+ 400 0a10 48000070 	.align 7
+ 400      60000000 
+ 400      60000000 
+ 400      60000000 
+ 400      60000000 
+ 401 0a80 8002F000 	      .long  0x8002F000          # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
+ 402 0a84 00000000 	      .long  0x00000000          #
+ 403 0a88 00000000 	      .long  0x00000000          #
+ 404 0a8c 1003FF00 	      .long  0x1003FF00          # @stack
+ 405 0a90 00000000 	      .long  0x00000000          #
+ 406 0a94 100004B0 	      .long  0x100004B0          # @entry
+ 407 0a98 00000000 	      .long  0
+ 408 0a9c 10030000 	      .long  0x10030000          # @print_start
+ 409 0aa0 00000000 	      .long  0
+ 410 0aa4 10031FFF 	      .long  0x10031FFF          # @print_end
+ 411 0aa8 00000000 	      .long  0
+ 412 0aac 10030000 	      .long  0x10030000          # print ptr
+ 413 0ab0 00000000 	      .quad  0                   # start tb
+ 413      00000000 
+ 414 0ab8 00000000 	      .quad  0                   # end tb
+ 414      00000000 
+ 415              	
+ 416 0ac0 8002F000 	      .long  0x8002F000          # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
+ 417 0ac4 00000000 	      .long  0x00000000          #
+ 418 0ac8 00000000 	      .long  0x00000000          #
+ 419 0acc 1003DF00 	      .long  0x1003DF00          # @stack
+ 420 0ad0 00000000 	      .long  0x00000000          #
+ 421 0ad4 100004B0 	      .long  0x100004B0          # @entry
+ 422 0ad8 00000000 	      .long  0
+ 423 0adc 10032000 	      .long  0x10032000          # @print_start
+ 424 0ae0 00000000 	      .long  0
+ 425 0ae4 10033FFF 	      .long  0x10033FFF          # @print_end
+ 426 0ae8 00000000 	      .long  0
+ 427 0aec 10032000 	      .long  0x10032000          # print ptr
+ 428 0af0 00000000 	      .quad  0                   # start tb
+ 428      00000000 
+ 429 0af8 00000000 	      .quad  0                   # end tb
+ 429      00000000 
+ 430              	
+ 431 0b00 8002F000 	      .long  0x8002F000          # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
+ 432 0b04 00000000 	      .long  0x00000000          # flags
+ 433 0b08 00000000 	      .long  0x00000000          #
+ 434 0b0c 1003BF00 	      .long  0x1003BF00          # @stack
+ 435 0b10 00000000 	      .long  0x00000000          #
+ 436 0b14 100004B0 	      .long  0x100004B0          # @entry
+ 437 0b18 00000000 	      .long  0
+ 438 0b1c 10034000 	      .long  0x10034000          # @print_start
+ 439 0b20 00000000 	      .long  0
+ 440 0b24 10035FFF 	      .long  0x10035FFF          # @print_end
+ 441 0b28 00000000 	      .long  0
+ 442 0b2c 10034000 	      .long  0x10034000          # print ptr
+ 443 0b30 00000000 	      .quad  0                   # start tb
+ 443      00000000 
+ 444 0b38 00000000 	      .quad  0                   # end tb
+ 444      00000000 
+ 445              	
+ 446 0b40 8002F000 	      .long  0x8002F000          # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
+ 447 0b44 00000000 	      .long  0x00000000          # flags
+ 448 0b48 00000000 	      .long  0x00000000          #
+ 449 0b4c 10039F00 	      .long  0x10039F00          # @stack
+ 450 0b50 00000000 	      .long  0x00000000          #
+ 451 0b54 100004B0 	      .long  0x100004B0          # @entry
+ 452 0b58 00000000 	      .long  0
+ 453 0b5c 10036000 	      .long  0x10036000          # @print_start
+ 454 0b60 00000000 	      .long  0
+ 455 0b64 10037FFF 	      .long  0x10037FFF          # @print_end
+ 456 0b68 00000000 	      .long  0
+ 457 0b6c 10036000 	      .long  0x10036000          # print ptr
+ 458 0b70 00000000 	      .quad  0                   # start tb
+ 458      00000000 
+ 459 0b78 00000000 	      .quad  0                   # end tb
+ 459      00000000 
+ 460              	
+ 461              	
+ 462              	.set S_MSR,0x00
+ 463              	.set S_FLAGS,0x04
+ 464              	.set S_ERATW2,0x08
+ 465              	.set S_EOT_SC,0x0C
+ 466              	
+ 467              	.set T_CONFIG,0x80
+ 468              	.set T_MSR,0x00
+ 469              	.set T_FLAGS,0x04
+ 470              	.set T_STACK,0x08
+ 471              	.set T_ENTRY,0x10
+ 472              	.set T_TIMER_START,0x30
+ 473              	.set T_TIMER_END,0x38
+ 474              	.set T_PRINTSTART, 0x18
+ 475              	.set T_PRINTEND, 0x20
+ 476              	.set T_PRINTF, 0x28
+ 477              	.set FLAG_EOT_SC,0x10
+ 478              	
+ 479              	
+ 480              	# -------------------------------------------------------------------------------------------------
+ 481              	# other stuff
+ 482 0b80 48000080 	.align 10
+ 482      60000000 
+ 482      60000000 
+ 482      60000000 
+ 482      60000000 
+ 483              	
+ 484              	# clear buffer and reset pointer to start
+ 485              	.align 6
+ 486              	printf_reset:
+ 487              	
+ 488 0c00 7CBE6AA6 	      mfspr     r5,tir           # who am i?
+ 489 0c04 78A53664 	      sldi      r5,r5,6          # 64B offset
+ 490 0c08 38A50A80 	      addi      r5,r5,CONFIG+T_CONFIG
+ 491              	
+ 492 0c0c 38C50018 	      addi      r6,r5,T_PRINTSTART
+ 493 0c10 E8E60000 	      ld        r7,0(r6)         # buffer start
+ 494 0c14 38C50020 	      addi      r6,r5,T_PRINTEND
+ 495 0c18 E9060000 	      ld        r8,0(r6)         # buffer end
+ 496 0c1c 7D074050 	      sub       r8,r8,r7
+ 497 0c20 39080001 	      addi      r8,r8,1          # num bytes
+ 498              	
+ 499 0c24 7D0903A6 	      mtctr     r8
+ 500 0c28 38C00000 	      li        r6,0
+ 501 0c2c 7CE83B78 	      mr        r8,r7
+ 502              	printf_reset_clr:
+ 503 0c30 98C80000 	      stb       r6,0(r8)
+ 504 0c34 39080001 	      addi      r8,r8,1
+ 505 0c38 4200FFF8 	      bdnz      printf_reset_clr
+ 506              	
+ 507 0c3c 39050028 	      addi      r8,r5,T_PRINTF
+ 508 0c40 F8E80000 	      std       r7,0(r8)         # reset ptr
+ 509              	
+ 510 0c44 4E800020 	      blr
+ 511              	
+ 512              	
+ 513              	# hvsc
+ 514 0c48 480000B8 	.align 8
+ 514      60000000 
+ 514      60000000 
+ 514      60000000 
+ 514      60000000 
+ 515              	# go to exec_complete_sup in sup mode
+ 516              	int_300_handler:
+ 517              	
+ 518 0d00 80000A00 	      lwz       r0,CONFIG+S_MSR(r0)
+ 519 0d04 7C000124 	      mtmsr     r0
+ 520 0d08 4C00012C 	      isync
+ 521 0d0c 4BFFF894 	      b         exec_complete_sup
+ 522              	
+ 523              	# sc
+ 524 0d10 480000F0 	.align 8
+ 524      60000000 
+ 524      60000000 
+ 524      60000000 
+ 524      60000000 
+ 525              	# r3 is id, remaining are function-specific
+ 526              	# not preserving r0, r3-r9 right now
+ 527              	#
+ 528              	# 0001 whoami
+ 529              	# 0010 tick
+ 530              	# 0100 putchar r4=c
+ 531              	# 0106 printf_mode *NI*
+ 532              	# 0107 printf_rst
+ 533              	#
+ 534              	int_120_handler:
+ 535              	
+ 536 0e00 7C0802A6 	      mflr      r0
+ 537              	
+ 538 0e04 2C230001 	      cmpdi     r3,0x0001
+ 539 0e08 41820038 	      beq       sc_whoami
+ 540 0e0c 2C230010 	      cmpdi     r3,0x0010
+ 541 0e10 41820070 	      beq       sc_tick
+ 542 0e14 2C230100 	      cmpdi     r3,0x100
+ 543 0e18 418200A8 	      beq       sc_putchar
+ 544 0e1c 2C230107 	      cmpdi     r3,0x107
+ 545 0e20 41820120 	      beq       sc_printf_rst
+ 546              	
+ 547 0e24 3860FFFF 	      li        r3,-1
+ 548 0e28 7C0803A6 	      mtlr      r0
+ 549 0e2c 4C000064 	      rfi
+ 550              	
+ 551              	# thread id
+ 552 0e30 60000000 	.align 6
+ 552      60000000 
+ 552      60000000 
+ 552      60000000 
+ 553              	sc_whoami:
+ 554 0e40 7C7E6AA6 	      mfspr     r3,tir
+ 555 0e44 4C000064 	      rfi
+ 556              	
+ 557              	# tb
+ 558 0e48 48000038 	.align 6
+ 558      60000000 
+ 558      60000000 
+ 558      60000000 
+ 558      60000000 
+ 559              	sc_tick:
+ 560 0e80 7C6C42A6 	      mfspr     r3,tb
+ 561 0e84 4C000064 	      rfi
+ 562              	
+ 563              	# wrap buffer; could add flag to stop when full, or reset
+ 564 0e88 48000038 	.align 6
+ 564      60000000 
+ 564      60000000 
+ 564      60000000 
+ 564      60000000 
+ 565              	sc_putchar:
+ 566              	
+ 567 0ec0 7CBE6AA6 	      mfspr     r5,tir           # who am i?
+ 568 0ec4 78A53664 	      sldi      r5,r5,6          # 64B offset
+ 569 0ec8 38A50A80 	      addi      r5,r5,CONFIG+T_CONFIG
+ 570              	
+ 571 0ecc 38C50028 	      addi      r6,r5,T_PRINTF
+ 572 0ed0 E8E60000 	      ld        r7,0(r6)         # buffer ptr
+ 573 0ed4 98870000 	      stb       r4,0(r7)         # store char
+ 574 0ed8 38E70001 	      addi      r7,r7,1
+ 575              	
+ 576 0edc 39050020 	      addi      r8,r5,T_PRINTEND
+ 577 0ee0 E9080000 	      ld        r8,0(r8)         # buffer end
+ 578 0ee4 7C274000 	      cmpd      r7,r8
+ 579 0ee8 38600000 	      li        r3,0             # rc=normal
+ 580 0eec 40810010 	      ble       sc_putchar_ok
+ 581 0ef0 39050018 	      addi      r8,r5,T_PRINTSTART
+ 582 0ef4 E8E80000 	      ld        r7,0(r8)         # buffer start
+ 583 0ef8 3860FFFF 	      li        r3,-1            # rc=full
+ 584              	sc_putchar_ok:
+ 585 0efc F8E60000 	      std       r7,0(r6)         # save ptr
+ 586              	
+ 587 0f00 4C000064 	      rfi
+ 588              	
+ 589              	# clear buffer and reset pointer to start
+ 590 0f04 4800003C 	.align 6
+ 590      60000000 
+ 590      60000000 
+ 590      60000000 
+ 590      60000000 
+ 591              	sc_printf_rst:
+ 592              	
+ 593 0f40 7C6902A6 	      mfctr     r3
+ 594              	
+ 595 0f44 4BFFFCBD 	      bl        printf_reset
+ 596              	
+ 597 0f48 7C6903A6 	      mtctr     r3
+ 598 0f4c 7C0803A6 	      mtlr      r0
+ 599 0f50 38600000 	      li        r3,0
+ 600              	
+ 601 0f54 4C000064 	      rfi
+ 602              	

dev/sim/coco/build_smt2/cmds.f

@@ -0,0 +1 @@
++timescale+1ns/1ps

dev/sim/coco/build_sweetpea/cmds.f

@@ -0,0 +1 @@
++timescale+1ns/1ps

dev/sim/coco/cocotb_icarus.v

@@ -0,0 +1,321 @@
+
+`include "tri_a2o.vh"
+
+`timescale 1ns/1ps
+
+// might add some sim-only lines to enable clks, etc.
+
+module cocotb_icarus (
+
+	 input[0:`NCLK_WIDTH-1] nclk,
+	 input                                                  scan_in,
+	 output                                                 scan_out,
+
+	 // Pervasive clock control
+	 input                                                  an_ac_rtim_sl_thold_8,
+	 input                                                  an_ac_func_sl_thold_8,
+	 input                                                  an_ac_func_nsl_thold_8,
+	 input                                                  an_ac_ary_nsl_thold_8,
+	 input                                                  an_ac_sg_8,
+	 input                                                  an_ac_fce_8,
+	 input [0:7]                                            an_ac_abst_scan_in,
+
+	 // L2 LARX/STCX
+  	 input [0:`THREADS-1]                                   an_ac_reservation_vld,
+	 input [0:`THREADS-1]                                   an_ac_stcx_complete,
+	 input [0:`THREADS-1]                                   an_ac_stcx_pass,
+
+	 // ICBI ACK Interface
+	 input                                                  an_ac_icbi_ack,
+	 input [0:1]                                            an_ac_icbi_ack_thread,
+
+	 // Back invalidate interface
+	 input                                                  an_ac_back_inv,
+	 input [64-`REAL_IFAR_WIDTH:63]                         an_ac_back_inv_addr,
+	 input [0:4]                                            an_ac_back_inv_target,		// connect to bit(0)
+	 input                                                  an_ac_back_inv_local,
+	 input                                                  an_ac_back_inv_lbit,
+	 input                                                  an_ac_back_inv_gs,
+	 input                                                  an_ac_back_inv_ind,
+	 input [0:7]                                            an_ac_back_inv_lpar_id,
+	 output                                                 ac_an_back_inv_reject,
+	 output [0:7]                                           ac_an_lpar_id,
+
+	 // L2 Reload Inputs
+	 input                                                  an_ac_reld_data_vld,		// reload data is coming next cycle
+	 input [0:4]                                            an_ac_reld_core_tag,		// reload data destinatoin tag (which load queue)
+	 input [0:127]                                          an_ac_reld_data,		// Reload Data
+	 input [58:59]                                          an_ac_reld_qw,		// quadword address of reload data beat
+	 input                                                  an_ac_reld_ecc_err,		// Reload Data contains a Correctable ECC error
+	 input                                                  an_ac_reld_ecc_err_ue,		// Reload Data contains an Uncorrectable ECC error
+	 input                                                  an_ac_reld_data_coming,
+	 input                                                  an_ac_reld_ditc,
+	 input                                                  an_ac_reld_crit_qw,
+	 input                                                  an_ac_reld_l1_dump,
+	 input [0:3]                                            an_ac_req_spare_ctrl_a1,		// spare control bits from L2
+
+	 // load/store credit control
+	 input                                                  an_ac_flh2l2_gate,		// Gate L1 Hit forwarding SPR config bit
+	 input                                                  an_ac_req_ld_pop,		// credit for a load (L2 can take a load command)
+	 input                                                  an_ac_req_st_pop,		// credit for a store (L2 can take a store command)
+	 input                                                  an_ac_req_st_gather,		// credit for a store due to L2 gathering of store commands
+	 input [0:`THREADS-1]                                   an_ac_sync_ack,
+
+	 //SCOM Satellite
+	 input [0:3]                                            an_ac_scom_sat_id,
+	 input                                                  an_ac_scom_dch,
+	 input                                                  an_ac_scom_cch,
+	 output                                                 ac_an_scom_dch,
+	 output                                                 ac_an_scom_cch,
+
+	 // FIR and Error Signals
+	 output [0:`THREADS-1]                                  ac_an_special_attn,
+	 output [0:2]                                           ac_an_checkstop,
+	 output [0:2]                                           ac_an_local_checkstop,
+	 output [0:2]                                           ac_an_recov_err,
+	 output                                                 ac_an_trace_error,
+    output                                                 ac_an_livelock_active,
+	 input                                                  an_ac_checkstop,
+	 input [0:`THREADS-1]                                   an_ac_external_mchk,
+
+	 // Perfmon Event Bus
+	 output [0:4*`THREADS-1]                                ac_an_event_bus0,
+	 output [0:4*`THREADS-1]                                ac_an_event_bus1,
+
+	 // Reset related
+	 input                                                  an_ac_reset_1_complete,
+	 input                                                  an_ac_reset_2_complete,
+	 input                                                  an_ac_reset_3_complete,
+	 input                                                  an_ac_reset_wd_complete,
+
+	 // Power Management
+	 output [0:`THREADS-1]                                  ac_an_pm_thread_running,
+	 input [0:`THREADS-1]                                   an_ac_pm_thread_stop,
+	 input [0:`THREADS-1]                                   an_ac_pm_fetch_halt,
+	 output                                                 ac_an_power_managed,
+	 output                                                 ac_an_rvwinkle_mode,
+
+	 // Clock, Test, and LCB Controls
+	 input                                                  an_ac_gsd_test_enable_dc,
+	 input                                                  an_ac_gsd_test_acmode_dc,
+	 input                                                  an_ac_ccflush_dc,
+	 input                                                  an_ac_ccenable_dc,
+	 input                                                  an_ac_lbist_en_dc,
+	 input                                                  an_ac_lbist_ip_dc,
+	 input                                                  an_ac_lbist_ac_mode_dc,
+	 input                                                  an_ac_scan_diag_dc,
+	 input                                                  an_ac_scan_dis_dc_b,
+
+	 //Thold input to clock control macro
+	 input [0:8]                                            an_ac_scan_type_dc,
+
+	 // Pervasive
+	 output                                                 ac_an_reset_1_request,
+	 output                                                 ac_an_reset_2_request,
+	 output                                                 ac_an_reset_3_request,
+	 output                                                 ac_an_reset_wd_request,
+	 input                                                  an_ac_lbist_ary_wrt_thru_dc,
+	 input [0:`THREADS-1]                                   an_ac_sleep_en,
+	 input [0:`THREADS-1]                                   an_ac_ext_interrupt,
+	 input [0:`THREADS-1]                                   an_ac_crit_interrupt,
+	 input [0:`THREADS-1]                                   an_ac_perf_interrupt,
+	 input [0:`THREADS-1]                                   an_ac_hang_pulse,
+	 input                                                  an_ac_tb_update_enable,
+	 input                                                  an_ac_tb_update_pulse,
+	 input [0:3]                                            an_ac_chipid_dc,
+	 input [0:7]                                            an_ac_coreid,
+	 output [0:`THREADS-1]                                  ac_an_machine_check,
+	 input                                                  an_ac_debug_stop,
+	 output [0:`THREADS-1]                                  ac_an_debug_trigger,
+	 input [0:`THREADS-1]                                   an_ac_uncond_dbg_event,
+	 output [0:31]                                          ac_an_debug_bus,
+	 output                                                 ac_an_coretrace_first_valid,	// coretrace_ctrls[0]
+	 output							                             ac_an_coretrace_valid,		// coretrace_ctrls[1]
+	 output	[0:1]						                          ac_an_coretrace_type,		// coretrace_ctrls[2:3]
+
+	 // L2 Outputs
+	 output                                                 ac_an_req_pwr_token,		// power token for command coming next cycle
+	 output                                                 ac_an_req,		// command request valid
+	 output [64-`REAL_IFAR_WIDTH:63]                        ac_an_req_ra,		// real address for request
+	 output [0:5]                                           ac_an_req_ttype,		// command (transaction) type
+	 output [0:2]                                           ac_an_req_thread,		// encoded thread ID
+	 output                                                 ac_an_req_wimg_w,		// write-through
+	 output                                                 ac_an_req_wimg_i,		// cache-inhibited
+	 output                                                 ac_an_req_wimg_m,		// memory coherence required
+	 output                                                 ac_an_req_wimg_g,		// guarded memory
+	 output [0:3]                                           ac_an_req_user_defined,		// User Defined Bits
+	 output [0:3]                                           ac_an_req_spare_ctrl_a0,		// Spare bits
+	 output [0:4]                                           ac_an_req_ld_core_tag,		// load command tag (which load Q)
+	 output [0:2]                                           ac_an_req_ld_xfr_len,		// transfer length for non-cacheable load
+	 output [0:31]                                          ac_an_st_byte_enbl,		// byte enables for store data
+	 output [0:255]                                         ac_an_st_data,		// store data
+	 output                                                 ac_an_req_endian,		// endian mode (0=big endian, 1=little endian)
+	 output                                                 ac_an_st_data_pwr_token		// store data power token
+);
+
+c c0(
+      //  generic map (
+      //       EXPAND_TYPE         => EXPAND_TYPE
+      //  );
+
+      .nclk(nclk),
+      .scan_in(scan_in),
+      .scan_out(scan_out),
+
+      // Pervasive clock control
+      .an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8),
+      .an_ac_func_sl_thold_8(an_ac_func_sl_thold_8),
+      .an_ac_func_nsl_thold_8(an_ac_func_nsl_thold_8),
+      .an_ac_ary_nsl_thold_8(an_ac_ary_nsl_thold_8),
+      .an_ac_sg_8(an_ac_sg_8),
+      .an_ac_fce_8(an_ac_fce_8),
+      .an_ac_abst_scan_in(an_ac_abst_scan_in),
+
+      // L2 STCX complete
+      .an_ac_stcx_complete(an_ac_stcx_complete),
+      .an_ac_stcx_pass(an_ac_stcx_pass),
+
+      // ICBI ACK Interface
+      .an_ac_icbi_ack(an_ac_icbi_ack),
+      .an_ac_icbi_ack_thread(an_ac_icbi_ack_thread),
+
+      // Back invalidate interface
+      .an_ac_back_inv(an_ac_back_inv),
+      .an_ac_back_inv_addr(an_ac_back_inv_addr),
+      .an_ac_back_inv_target(an_ac_back_inv_target),
+      .an_ac_back_inv_local(an_ac_back_inv_local),
+      .an_ac_back_inv_lbit(an_ac_back_inv_lbit),
+      .an_ac_back_inv_gs(an_ac_back_inv_gs),
+      .an_ac_back_inv_ind(an_ac_back_inv_ind),
+      .an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id),
+      .ac_an_back_inv_reject(ac_an_back_inv_reject),
+      .ac_an_lpar_id(ac_an_lpar_id),
+
+      // L2 Reload Inputs
+      .an_ac_reld_data_vld(an_ac_reld_data_vld),
+      .an_ac_reld_core_tag(an_ac_reld_core_tag),
+      .an_ac_reld_data(an_ac_reld_data),
+      .an_ac_reld_qw(an_ac_reld_qw),
+      .an_ac_reld_ecc_err(an_ac_reld_ecc_err),
+      .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue),
+      .an_ac_reld_data_coming(an_ac_reld_data_coming),
+      .an_ac_reld_ditc(an_ac_reld_ditc),
+      .an_ac_reld_crit_qw(an_ac_reld_crit_qw),
+      .an_ac_reld_l1_dump(an_ac_reld_l1_dump),
+      .an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1),
+
+      // load/store credit control
+      .an_ac_flh2l2_gate(an_ac_flh2l2_gate),
+      .an_ac_req_ld_pop(an_ac_req_ld_pop),
+      .an_ac_req_st_pop(an_ac_req_st_pop),
+      .an_ac_req_st_gather(an_ac_req_st_gather),
+      .an_ac_sync_ack(an_ac_sync_ack),
+      .an_ac_pm_fetch_halt(an_ac_pm_fetch_halt),
+
+      //SCOM Satellite
+      .an_ac_scom_sat_id(an_ac_scom_sat_id),
+      .an_ac_scom_dch(an_ac_scom_dch),
+      .an_ac_scom_cch(an_ac_scom_cch),
+      .ac_an_scom_dch(ac_an_scom_dch),
+      .ac_an_scom_cch(ac_an_scom_cch),
+
+      // FIR and Error Signals
+      .ac_an_special_attn(ac_an_special_attn),
+      .ac_an_checkstop(ac_an_checkstop),
+      .ac_an_local_checkstop(ac_an_local_checkstop),
+      .ac_an_recov_err(ac_an_recov_err),
+      .ac_an_trace_error(ac_an_trace_error),
+      .ac_an_livelock_active(ac_an_livelock_active),
+      .an_ac_checkstop(an_ac_checkstop),
+      .an_ac_external_mchk(an_ac_external_mchk),
+
+      // Perfmon Event Bus
+      .ac_an_event_bus0(ac_an_event_bus0),
+      .ac_an_event_bus1(ac_an_event_bus1),
+
+      // Reset related
+      .an_ac_reset_1_complete(an_ac_reset_1_complete),
+      .an_ac_reset_2_complete(an_ac_reset_2_complete),
+      .an_ac_reset_3_complete(an_ac_reset_3_complete),
+      .an_ac_reset_wd_complete(an_ac_reset_wd_complete),
+
+      // Power Management
+      .ac_an_pm_thread_running(ac_an_pm_thread_running),
+      .an_ac_pm_thread_stop(an_ac_pm_thread_stop),
+      .ac_an_power_managed(ac_an_power_managed),
+      .ac_an_rvwinkle_mode(ac_an_rvwinkle_mode),
+
+      // Clock, Test, and LCB Controls
+      .an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc),
+      .an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc),
+      .an_ac_ccflush_dc(an_ac_ccflush_dc),
+      .an_ac_ccenable_dc(an_ac_ccenable_dc),
+      .an_ac_lbist_en_dc(an_ac_lbist_en_dc),
+      .an_ac_lbist_ip_dc(an_ac_lbist_ip_dc),
+      .an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc),
+      .an_ac_scan_diag_dc(an_ac_scan_diag_dc),
+      .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b),
+
+      //Thold input to clock control macro
+      .an_ac_scan_type_dc(an_ac_scan_type_dc),
+
+      // Pervasive
+      .ac_an_reset_1_request(ac_an_reset_1_request),
+      .ac_an_reset_2_request(ac_an_reset_2_request),
+      .ac_an_reset_3_request(ac_an_reset_3_request),
+      .ac_an_reset_wd_request(ac_an_reset_wd_request),
+      .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
+      .an_ac_reservation_vld(an_ac_reservation_vld),
+      .an_ac_sleep_en(an_ac_sleep_en),
+      .an_ac_ext_interrupt(an_ac_ext_interrupt),
+      .an_ac_crit_interrupt(an_ac_crit_interrupt),
+      .an_ac_perf_interrupt(an_ac_perf_interrupt),
+      .an_ac_hang_pulse(an_ac_hang_pulse),
+      .an_ac_tb_update_enable(an_ac_tb_update_enable),
+      .an_ac_tb_update_pulse(an_ac_tb_update_pulse),
+      .an_ac_chipid_dc(an_ac_chipid_dc),
+      .an_ac_coreid(an_ac_coreid),
+      .ac_an_machine_check(ac_an_machine_check),
+      .an_ac_debug_stop(an_ac_debug_stop),
+      .ac_an_debug_trigger(ac_an_debug_trigger),
+      .an_ac_uncond_dbg_event(an_ac_uncond_dbg_event),
+
+      // L2 Outputs
+      .ac_an_req_pwr_token(ac_an_req_pwr_token),
+      .ac_an_req(ac_an_req),
+      .ac_an_req_ra(ac_an_req_ra),
+      .ac_an_req_ttype(ac_an_req_ttype),
+      .ac_an_req_thread(ac_an_req_thread),
+      .ac_an_req_wimg_w(ac_an_req_wimg_w),
+      .ac_an_req_wimg_i(ac_an_req_wimg_i),
+      .ac_an_req_wimg_m(ac_an_req_wimg_m),
+      .ac_an_req_wimg_g(ac_an_req_wimg_g),
+      .ac_an_req_user_defined(ac_an_req_user_defined),
+      .ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0),
+      .ac_an_req_ld_core_tag(ac_an_req_ld_core_tag),
+      .ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len),
+      .ac_an_st_byte_enbl(ac_an_st_byte_enbl),
+      .ac_an_st_data(ac_an_st_data),
+      .ac_an_req_endian(ac_an_req_endian),
+      .ac_an_st_data_pwr_token(ac_an_st_data_pwr_token)
+   );
+
+initial begin
+  $dumpfile ("wtf-coco.vcd");
+  // you can do it by levels and also by module so could prune down
+  $dumpvars;
+  // need to explicitly specify arrays for icarus
+  // guess not: $dumpvars cannot dump a vpiMemory
+  //$dumpvars(0, c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q);
+  #1;
+end
+
+// see if coco lets me risingedge() these
+wire clk_1x, clk_2x, clk_4x, rst;
+
+assign clk_1x = nclk[0];
+assign clk_2x = nclk[2];
+assign clk_4x = nclk[3];
+assign rst = nclk[1];
+
+endmodule

dev/sim/coco/makegtkw

@@ -0,0 +1,310 @@
+#!/bin/python3
+
+# problems:
+#  some parse error causes it to ignore filters AND not let you add them (can be caused from gui); changing order
+#   of traces fixes it - maybe problem with my trans filter?
+
+import sys
+import os
+import io
+from dotmap import DotMap
+
+from vcd.gtkw import *
+
+gtkwFile = 'pyvcd.gtkw'
+#fo = io.StringIO(gtkwFile)
+fo = open(gtkwFile, 'w')
+gtkw = GTKWSave(fo)
+
+base = 'cocotb_icarus.'
+topIndicator = '!'  #wtf never need this?
+vectorNoBits = False
+core = 0
+
+# add zero and one signals to top level for use here
+zero = 'an_ac_sg_8'
+
+filterPath = '../gtkwave/'
+filterNull = filterPath + 'gtkf-nop.py'
+filterValid = filterPath + 'gtkf-valid.py'
+filterIBuf = filterPath + 'gtkf-ibuf.py'
+filterPPC = filterPath + 'gtkf-ppc.py'
+filterA2L2 = filterPath + 'gtkf-a2l2.py'
+filterR64 = filterPath + 'gtkf-64R.py'
+
+# need to indicate if signal is 'threaded' (vector) to gen diff netlists for diff smt modes
+
+
+# showVector should maybe be done by Combined that can take specific bits to use
+class Signal(DotMap):
+   def __init__(self, name, alias=None, color=None, highlight=False, rjustify=False, datafmt='bin', extraflags=GTKWFlag(0), translateFile=None, translateProc=None, transactionProc=None, bits=None, showVector=False):
+      super().__init__()
+      if name[0] != topIndicator:
+         name = base + name
+      else:
+         name = name[1:]
+      self.name = name
+      self.bits = bits
+      self.alias = alias
+      self.color = color
+      self.highlight = highlight
+      self.rjustify = rjustify
+      self.datafmt = datafmt
+      self.extraflags = extraflags
+      self.translateFile = translateFile
+      self.translateProc = translateProc
+      self.transactionProc = transactionProc
+      self.showVector = showVector
+
+   def add(self):
+      trace = self.name
+      bits = self.bits
+      if bits is not None:
+         if vectorNoBits:
+            trace = trace.split('[')[0]
+         if type(bits) is not list:
+            bits = [bits]
+         with gtkw.trace_bits(trace, showVector=self.showVector):
+            for i in range(len(bits)):
+               # for now - i guess highlight and filters might make sense
+               #gtkw.trace_bit(bits[i], trace, self.alias, self.color, self.datafmt, self.highlight, self.rjustify, self.extraflags, translate_filter_file=self.translateFile, translate_filter_proc=self.translateProc, transaction_filter_proc=self.transactionProc)
+               gtkw.trace_bit(bits[i], trace, self.alias, self.color)
+
+      else:
+         gtkw.trace(trace, self.alias, self.color, self.datafmt, self.highlight, self.rjustify, self.extraflags, translate_filter_file=self.translateFile, translate_filter_proc=self.translateProc, transaction_filter_proc=self.transactionProc)
+
+class Combined(DotMap):
+   def __init__(self, name, traces, color=None, highlight=False, rjustify=False, datafmt='bin', extraflags=GTKWFlag(0), translateFile=None, translateProc=None, transactionProc=None):
+      super().__init__()
+      self.name = name
+      self.traces = traces
+      self.color = color
+      self.highlight = highlight
+      self.rjustify = rjustify
+      self.datafmt = datafmt
+      self.extraflags = extraflags
+      self.translateFile = translateFile
+      self.translateProc = translateProc
+      self.transactionProc = transactionProc
+
+   def add(self):
+      trace = []
+      for t in self.traces:
+         trace.append(t.name)
+      gtkw.trace(trace, self.name, self.color, self.datafmt, self.highlight, self.rjustify, self.extraflags, translate_filter_file=self.translateFile, translate_filter_proc=self.translateProc, transaction_filter_proc=self.transactionProc)
+
+class Group(DotMap):
+   def __init__(self, name, traces, closed=True, highlight=False):
+      super().__init__()
+      self.name = name
+      self.traces = traces
+      self.closed = closed
+      self.highlight = highlight
+
+   def add(self):
+      if len(self.traces) > 0:
+         with gtkw.group(self.name, self.closed, self.highlight):
+            for j in range(len(self.traces)):
+               self.traces[j].add()
+
+   def addCombined(self, alias, color=None, highlight=False, rjustify=False, datafmt='bin', extraflags=GTKWFlag(0), translateFile=None, translateProc=None, transactionProc=None):
+      trace = []
+      for t in self.traces:
+         trace.append(t.name)
+      gtkw.trace(trace, alias, color, datafmt, highlight, rjustify, extraflags, translate_filter_file=translateFile, translate_filter_proc=translateProc, transaction_filter_proc=transactionProc)
+
+nodeMisc = Group('Misc', [
+   Signal(f'nclk[0:5]', alias='reset', bits=1, showVector=False),
+   Signal(f'nclk[0:5]', alias='clk1x', bits=0, showVector=False),
+   Signal(f'nclk[0:5]', alias='clk2x', bits=2, showVector=False),
+   Signal(f'an_ac_pm_thread_stop[0]')
+   #Signal('ac_an_checkstop[0:2]'),
+])
+#nodeMisc.add()
+# until gtkwave has a tiny nested indicator...
+for i in range(len(nodeMisc.traces)):
+   nodeMisc.traces[i].add()
+
+a2l2Req = Group('A2L2 Req', [
+   Signal(f'ac_an_req'),
+   Signal(f'ac_an_req_endian'),
+   Signal(f'ac_an_req_ld_core_tag[0:4]'),
+   Signal(f'ac_an_req_ld_xfr_len[0:2]'),
+   Signal(f'ac_an_req_pwr_token'),
+   Signal(f'ac_an_req_ra[22:63]'),
+   Signal(f'ac_an_req_ttype[0:5]'),
+   Signal(f'ac_an_req_wimg_w'),
+   Signal(f'ac_an_req_wimg_i'),
+   Signal(f'ac_an_req_wimg_m'),
+   Signal(f'ac_an_req_wimg_g')
+])
+
+a2l2Rsp = Group('A2L2 Rsp', [
+   Signal(f'an_ac_reld_data_coming'),
+   Signal(f'an_ac_reld_data_vld'),
+   Signal(f'an_ac_reld_qw[58:59]', datafmt='dec', rjustify=True),
+   Signal(f'an_ac_reld_crit_qw'),
+   Signal(f'an_ac_reld_data[0:127]', datafmt='hex')
+])
+
+a2l2Misc = Group('A2L2 Misc', [
+   Signal(f'ac_an_req_pwr_token'),
+   Signal(f'an_ac_req_ld_pop'),
+   Signal(f'c{core}.lq0.lsq.arb.load_cred_cnt_q[0:4]', datafmt='dec'),
+   Signal(f'an_ac_req_st_pop'),
+   Signal(f'an_ac_req_st_gather'),
+   Signal(f'c{core}.lq0.lsq.arb.store_cred_cnt_q[0:5]', datafmt='dec'),
+   Signal(f'an_ac_reservation_vld'),
+   Signal(f'an_ac_stcx_complete'),
+   Signal(f'an_ac_stcx_pass'),
+   Signal(f'an_ac_sync_ack'),
+   Signal(f'an_ac_icbi_ack')
+])
+
+ibuf = Group('IBuf', [
+   Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_valid_q[0:15]', datafmt='hex'),
+   Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_head_q[0:15]', datafmt='hex')
+])
+for i in range(16):
+   ibuf.traces.append(
+      Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[{i}].q[0:109]',translateProc=filterIBuf)
+   )
+
+#ibuf2 = Combined(f'IBuf[{i}]',
+#      [
+#      (Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_valid_q[0:15]', bits=[{i}]),
+#      Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[{i}].q[0:109]')) for i in range(16)
+#      ]
+#)
+
+
+pipe = []
+
+pipe.append(Combined('iu_xu_nia', [
+   Signal(f'c{core}.iuq0.iu_xu_t0_nia[0:61]'),
+   Signal(zero), # word-align
+   Signal(zero)
+], datafmt='hex'))
+
+pipe.append(ibuf)
+#pipe.append(ibuf2)
+
+for i in range(2):
+   pipe.append(Signal(f'c{core}.iu_rv_iu6_t0_i{i}_instr[0:31]', datafmt='hex', color=GTKWColor.green, translateProc=filterPPC))
+
+# match cycle with instr
+for i in range(2):
+   pipe.append(Combined(f'iu6_i{i}_itag_dispatched', [
+      Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_dispatched_d'),
+      Signal(zero),  # pad missing bit 0
+      Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i{i}_itag[1:6]')
+      ], color=GTKWColor.green, translateProc=filterValid))
+
+#for i in range(2):
+#   pipe.append(Combined(f'iu6_i{i}_itag', [
+#      Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_valop_q'),
+#      Signal(zero),  # pad missing bit 0
+#      Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_itag_q[1:6]')
+#      ], color=GTKWColor.blue, translateProc=filterValid))
+
+for i in range(2):
+   pipe.append(Combined(f'iu6_i{i}_itag_dispatched', [
+      Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_dispatched_q'),
+      Signal(zero),  # pad missing bit 0
+      Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_itag_q[1:6]')
+      ], color=GTKWColor.green, translateProc=filterValid))
+
+# eventually arrange all by ex
+for ex in range(1):
+   for rv in range(2):
+      for fx in range(2):
+         for src in range(1,4):
+            pipe.append(Combined(f'rv0_fx{fx}_ex{ex}_s{src}', [
+               Signal(f'c{core}.rv_fx{fx}_ex{ex}_s{src}_v'),
+               Signal(f'c{core}.rv0.rf_byp.fx{fx}_ex{ex}_s{src}_itag_q[0:6]')
+            ], color=GTKWColor.blue, translateProc=filterValid))
+
+for ex in range(6):
+   for fx in range(2):
+         pipe.append(Combined(f'fx{fx}_ex{ex}', [
+            Signal(f'c{core}.xu0.xu{fx}.dec.ex{ex}_val_q[0]'),
+            Signal(f'c{core}.xu0.xu{fx}.dec.ex{ex}_itag_q[0:6]')
+         ], color=GTKWColor.blue, translateProc=filterValid))
+
+for ex in range(4):
+   pipe.append(Combined(f'br_ex{ex}_bta', [
+         Signal(f'c{core}.xu0.xu0.br.ex{ex}_bta_val_q'),
+         Signal(f'c{core}.xu0.xu0.br.ex{ex}_pred_bta_q[42:61]'),
+         Signal(zero),  # word-align
+         Signal(zero)
+   ], color=GTKWColor.blue, translateProc=filterValid))
+
+
+for i in range(2):
+   pipe.append(Combined(f'cp2 i{i}_completed_itag', [
+      Signal(f'c{core}.iu_lq_i{i}_completed'),
+      Signal(f'c{core}.iu_lq_t0_i{i}_completed_itag[0:6]'),
+   ], color=GTKWColor.green, translateProc=filterValid))
+
+for i in range(2):
+   pipe.append(Combined(f'cp2 i{i}_completed_ifar', [
+      Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp2_i{i}_complete_q'),
+      Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i{i}_ifar[42:61]'),
+      Signal(zero), # word-align
+      Signal(zero)
+   ], color=GTKWColor.green, translateProc=filterValid))
+
+# or add more stuff and make transaction
+for i in range(2):
+   pipe.append(Combined(f'cp2 i{i}_completed_itag/ifar', [
+      Signal(f'c{core}.iu_lq_i{i}_completed'),
+      Signal(zero),  # pad itag
+      Signal(f'c{core}.iu_lq_t0_i{i}_completed_itag[0:6]'),
+      Signal(zero),  # pad ifar
+      Signal(zero),  # pad
+      Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i{i}_ifar[42:61]'),
+      Signal(zero), # word-align
+      Signal(zero)
+   ], color=GTKWColor.green, translateProc=filterValid))
+
+
+pipe = Group('Pipe', pipe, closed=False)
+
+
+threads = 1
+sprs = [None] * threads
+for i in range(threads):
+   sprs[i] = Group(f't{i} SPR', [
+      Signal(f'c{core}.xu0.spr.threads.thread[{i}].xu_spr_tspr.srr0_do[0:64]', datafmt='bin', translateProc=filterR64),
+      Signal(f'c{core}.xu0.spr.threads.thread[{i}].xu_spr_tspr.srr1_do[0:64]', datafmt='bin', translateProc=filterR64)
+   ], closed=False)
+
+a2l2Req.add()
+a2l2Rsp.add()
+a2l2Misc.add()
+
+# move this after and it works
+#a2l2Req.addCombined('A2L2 Trans (Req)', transactionProc=filterA2L2)
+
+pipe.add()
+sprs[0].add()
+
+a2l2Req.addCombined('A2L2 Trans (Req)', transactionProc=filterA2L2)
+
+#for i in range(len(groups)):
+#   groups[i].add()
+
+
+#gtkw.comment('Test pyvcd')
+#gtkw.savefile(gtkwFile)
+#gtkw.zoom_markers()
+#gtkw.pos()
+
+gtkw.sst_expanded(True)
+gtkw.size(3000, 1500)
+gtkw.treeopen(base)
+gtkw.signals_width(600)
+gtkw.pattern_trace(True)
+
+
+fo.close()

dev/sim/coco/pyvcd.gtkw

@@ -0,0 +1,255 @@
+@800200
+-
+@28
++{reset} (1)cocotb_icarus.nclk[0:5]
+@1001200
+-group_end
+@800200
+-
+@28
++{clk1x} (0)cocotb_icarus.nclk[0:5]
+@1001200
+-group_end
+@800200
+-
+@28
++{clk2x} (2)cocotb_icarus.nclk[0:5]
+@1001200
+-group_end
+@8
+cocotb_icarus.an_ac_pm_thread_stop[0]
+@c00200
+-A2L2 Req
+@8
+cocotb_icarus.ac_an_req
+cocotb_icarus.ac_an_req_endian
+cocotb_icarus.ac_an_req_ld_core_tag[0:4]
+cocotb_icarus.ac_an_req_ld_xfr_len[0:2]
+cocotb_icarus.ac_an_req_pwr_token
+cocotb_icarus.ac_an_req_ra[22:63]
+cocotb_icarus.ac_an_req_ttype[0:5]
+cocotb_icarus.ac_an_req_wimg_w
+cocotb_icarus.ac_an_req_wimg_i
+cocotb_icarus.ac_an_req_wimg_m
+cocotb_icarus.ac_an_req_wimg_g
+@1401200
+-A2L2 Req
+@c00200
+-A2L2 Rsp
+@8
+cocotb_icarus.an_ac_reld_data_coming
+cocotb_icarus.an_ac_reld_data_vld
+@24
+cocotb_icarus.an_ac_reld_qw[58:59]
+@8
+cocotb_icarus.an_ac_reld_crit_qw
+@2
+cocotb_icarus.an_ac_reld_data[0:127]
+@1401200
+-A2L2 Rsp
+@c00200
+-A2L2 Misc
+@8
+cocotb_icarus.ac_an_req_pwr_token
+cocotb_icarus.an_ac_req_ld_pop
+@4
+cocotb_icarus.c0.lq0.lsq.arb.load_cred_cnt_q[0:4]
+@8
+cocotb_icarus.an_ac_req_st_pop
+cocotb_icarus.an_ac_req_st_gather
+@4
+cocotb_icarus.c0.lq0.lsq.arb.store_cred_cnt_q[0:5]
+@8
+cocotb_icarus.an_ac_reservation_vld
+cocotb_icarus.an_ac_stcx_complete
+cocotb_icarus.an_ac_stcx_pass
+cocotb_icarus.an_ac_sync_ack
+cocotb_icarus.an_ac_icbi_ack
+@1401200
+-A2L2 Misc
+@800200
+-Pipe
+@2
+#{iu_xu_nia} (0)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (1)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (2)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (3)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (4)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (5)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (6)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (7)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (8)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (9)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (10)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (11)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (12)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (13)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (14)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (15)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (16)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (17)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (18)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (19)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (20)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (21)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (22)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (23)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (24)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (25)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (26)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (27)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (28)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (29)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (30)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (31)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (32)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (33)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (34)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (35)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (36)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (37)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (38)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (39)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (40)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (41)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (42)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (43)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (44)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (45)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (46)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (47)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (48)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (49)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (50)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (51)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (52)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (53)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (54)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (55)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (56)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (57)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (58)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (59)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (60)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (61)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 
+@c00200
+-IBuf
+@2
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_valid_q[0:15]
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_head_q[0:15]
+@4008
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[0].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[1].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[2].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[3].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[4].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[5].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[6].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[7].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[8].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[9].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[10].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[11].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[12].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[13].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[14].q[0:109]
+^>1 ../gtkwave/gtkf-ibuf.py
+cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[15].q[0:109]
+@1401200
+-IBuf
+@4002
+[color] 4
+^>2 ../gtkwave/gtkf-ppc.py
+cocotb_icarus.c0.iu_rv_iu6_t0_i0_instr[0:31]
+[color] 4
+^>2 ../gtkwave/gtkf-ppc.py
+cocotb_icarus.c0.iu_rv_iu6_t0_i1_instr[0:31]
+@4008
+[color] 4
+^>3 ../gtkwave/gtkf-valid.py
+#{iu6_i0_itag_dispatched} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_dispatched_d cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] 
+[color] 4
+^>3 ../gtkwave/gtkf-valid.py
+#{iu6_i1_itag_dispatched} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_dispatched_d cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] 
+[color] 4
+^>3 ../gtkwave/gtkf-valid.py
+#{iu6_i0_itag_dispatched} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_dispatched_q cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] 
+[color] 4
+^>3 ../gtkwave/gtkf-valid.py
+#{iu6_i1_itag_dispatched} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_dispatched_q cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{rv0_fx0_ex0_s1} cocotb_icarus.c0.rv_fx0_ex0_s1_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{rv0_fx0_ex0_s2} cocotb_icarus.c0.rv_fx0_ex0_s2_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{rv0_fx0_ex0_s3} cocotb_icarus.c0.rv_fx0_ex0_s3_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{rv0_fx1_ex0_s1} cocotb_icarus.c0.rv_fx1_ex0_s1_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{rv0_fx1_ex0_s2} cocotb_icarus.c0.rv_fx1_ex0_s2_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{rv0_fx1_ex0_s3} cocotb_icarus.c0.rv_fx1_ex0_s3_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{rv0_fx0_ex0_s1} cocotb_icarus.c0.rv_fx0_ex0_s1_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{rv0_fx0_ex0_s2} cocotb_icarus.c0.rv_fx0_ex0_s2_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{rv0_fx0_ex0_s3} cocotb_icarus.c0.rv_fx0_ex0_s3_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{rv0_fx1_ex0_s1} cocotb_icarus.c0.rv_fx1_ex0_s1_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{rv0_fx1_ex0_s2} cocotb_icarus.c0.rv_fx1_ex0_s2_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{rv0_fx1_ex0_s3} cocotb_icarus.c0.rv_fx1_ex0_s3_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{fx0_ex0} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex0_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{fx1_ex0} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex0_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{fx0_ex1} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex1_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{fx1_ex1} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex1_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{fx0_ex2} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex2_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{fx1_ex2} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex2_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{fx0_ex3} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex3_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{fx1_ex3} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex3_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{fx0_ex4} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex4_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{fx1_ex4} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex4_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{fx0_ex5} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex5_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{fx1_ex5} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex5_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{br_ex0_bta} cocotb_icarus.c0.xu0.xu0.br.ex0_bta_val_q (0)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (1)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (2)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (3)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (4)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (5)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (6)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (7)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (8)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (9)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (10)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (11)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (12)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (13)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (14)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (15)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (16)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (17)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (18)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (19)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{br_ex1_bta} cocotb_icarus.c0.xu0.xu0.br.ex1_bta_val_q (0)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (1)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (2)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (3)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (4)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (5)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (6)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (7)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (8)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (9)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (10)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (11)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (12)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (13)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (14)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (15)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (16)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (17)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (18)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (19)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{br_ex2_bta} cocotb_icarus.c0.xu0.xu0.br.ex2_bta_val_q (0)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (1)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (2)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (3)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (4)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (5)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (6)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (7)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (8)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (9)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (10)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (11)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (12)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (13)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (14)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (15)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (16)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (17)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (18)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (19)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 
+[color] 5
+^>3 ../gtkwave/gtkf-valid.py
+#{br_ex3_bta} cocotb_icarus.c0.xu0.xu0.br.ex3_bta_val_q (0)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (1)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (2)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (3)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (4)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (5)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (6)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (7)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (8)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (9)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (10)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (11)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (12)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (13)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (14)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (15)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (16)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (17)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (18)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (19)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 
+[color] 4
+^>3 ../gtkwave/gtkf-valid.py
+#{cp2 i0_completed_itag} cocotb_icarus.c0.iu_lq_i0_completed (0)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (1)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (2)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (3)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (4)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (5)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (6)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] 
+[color] 4
+^>3 ../gtkwave/gtkf-valid.py
+#{cp2 i1_completed_itag} cocotb_icarus.c0.iu_lq_i1_completed (0)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (1)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (2)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (3)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (4)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (5)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (6)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] 
+[color] 4
+^>3 ../gtkwave/gtkf-valid.py
+#{cp2 i0_completed_ifar} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp2_i0_complete_q (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (6)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (7)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (8)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (9)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (10)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (11)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (12)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (13)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (14)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (15)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (16)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (17)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (18)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (19)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 
+[color] 4
+^>3 ../gtkwave/gtkf-valid.py
+#{cp2 i1_completed_ifar} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp2_i1_complete_q (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (6)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (7)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (8)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (9)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (10)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (11)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (12)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (13)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (14)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (15)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (16)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (17)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (18)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (19)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 
+[color] 4
+^>3 ../gtkwave/gtkf-valid.py
+#{cp2 i0_completed_itag/ifar} cocotb_icarus.c0.iu_lq_i0_completed cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (1)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (2)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (3)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (4)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (5)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (6)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (6)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (7)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (8)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (9)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (10)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (11)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (12)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (13)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (14)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (15)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (16)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (17)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (18)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (19)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 
+[color] 4
+^>3 ../gtkwave/gtkf-valid.py
+#{cp2 i1_completed_itag/ifar} cocotb_icarus.c0.iu_lq_i1_completed cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (1)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (2)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (3)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (4)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (5)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (6)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (6)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (7)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (8)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (9)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (10)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (11)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (12)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (13)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (14)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (15)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (16)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (17)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (18)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (19)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 
+@1000200
+-Pipe
+@800200
+-t0 SPR
+@4008
+^>4 ../gtkwave/gtkf-64R.py
+cocotb_icarus.c0.xu0.spr.threads.thread[0].xu_spr_tspr.srr0_do[0:64]
+^>4 ../gtkwave/gtkf-64R.py
+cocotb_icarus.c0.xu0.spr.threads.thread[0].xu_spr_tspr.srr1_do[0:64]
+@1000200
+-t0 SPR
+@10000008
+^<1 ../gtkwave/gtkf-a2l2.py
+#{A2L2 Trans (Req)} cocotb_icarus.ac_an_req cocotb_icarus.ac_an_req_endian (0)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (1)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (2)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (3)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (4)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (0)cocotb_icarus.ac_an_req_ld_xfr_len[0:2] (1)cocotb_icarus.ac_an_req_ld_xfr_len[0:2] (2)cocotb_icarus.ac_an_req_ld_xfr_len[0:2] cocotb_icarus.ac_an_req_pwr_token (0)cocotb_icarus.ac_an_req_ra[22:63] (1)cocotb_icarus.ac_an_req_ra[22:63] (2)cocotb_icarus.ac_an_req_ra[22:63] (3)cocotb_icarus.ac_an_req_ra[22:63] (4)cocotb_icarus.ac_an_req_ra[22:63] (5)cocotb_icarus.ac_an_req_ra[22:63] (6)cocotb_icarus.ac_an_req_ra[22:63] (7)cocotb_icarus.ac_an_req_ra[22:63] (8)cocotb_icarus.ac_an_req_ra[22:63] (9)cocotb_icarus.ac_an_req_ra[22:63] (10)cocotb_icarus.ac_an_req_ra[22:63] (11)cocotb_icarus.ac_an_req_ra[22:63] (12)cocotb_icarus.ac_an_req_ra[22:63] (13)cocotb_icarus.ac_an_req_ra[22:63] (14)cocotb_icarus.ac_an_req_ra[22:63] (15)cocotb_icarus.ac_an_req_ra[22:63] (16)cocotb_icarus.ac_an_req_ra[22:63] (17)cocotb_icarus.ac_an_req_ra[22:63] (18)cocotb_icarus.ac_an_req_ra[22:63] (19)cocotb_icarus.ac_an_req_ra[22:63] (20)cocotb_icarus.ac_an_req_ra[22:63] (21)cocotb_icarus.ac_an_req_ra[22:63] (22)cocotb_icarus.ac_an_req_ra[22:63] (23)cocotb_icarus.ac_an_req_ra[22:63] (24)cocotb_icarus.ac_an_req_ra[22:63] (25)cocotb_icarus.ac_an_req_ra[22:63] (26)cocotb_icarus.ac_an_req_ra[22:63] (27)cocotb_icarus.ac_an_req_ra[22:63] (28)cocotb_icarus.ac_an_req_ra[22:63] (29)cocotb_icarus.ac_an_req_ra[22:63] (30)cocotb_icarus.ac_an_req_ra[22:63] (31)cocotb_icarus.ac_an_req_ra[22:63] (32)cocotb_icarus.ac_an_req_ra[22:63] (33)cocotb_icarus.ac_an_req_ra[22:63] (34)cocotb_icarus.ac_an_req_ra[22:63] (35)cocotb_icarus.ac_an_req_ra[22:63] (36)cocotb_icarus.ac_an_req_ra[22:63] (37)cocotb_icarus.ac_an_req_ra[22:63] (38)cocotb_icarus.ac_an_req_ra[22:63] (39)cocotb_icarus.ac_an_req_ra[22:63] (40)cocotb_icarus.ac_an_req_ra[22:63] (41)cocotb_icarus.ac_an_req_ra[22:63] (0)cocotb_icarus.ac_an_req_ttype[0:5] (1)cocotb_icarus.ac_an_req_ttype[0:5] (2)cocotb_icarus.ac_an_req_ttype[0:5] (3)cocotb_icarus.ac_an_req_ttype[0:5] (4)cocotb_icarus.ac_an_req_ttype[0:5] (5)cocotb_icarus.ac_an_req_ttype[0:5] cocotb_icarus.ac_an_req_wimg_w cocotb_icarus.ac_an_req_wimg_i cocotb_icarus.ac_an_req_wimg_m cocotb_icarus.ac_an_req_wimg_g 
+[*] Test pyvcd
+[sst_expanded] 1
+[size] 3000 1500
+[treeopen] cocotb_icarus.
+[signals_width] 600
+[pattern_trace] 1

dev/sim/coco/results.xml

@@ -0,0 +1,8 @@
+<testsuites name="results">
+  <testsuite name="all" package="all">
+    <property name="random_seed" value="1654605675" />
+    <testcase name="tb" classname="tb" file="/home/wtf/projects/a2o-opf/dev/sim/coco/tb.py" lineno="232" time="163.92313623428345" sim_time_ns="8177.000001" ratio_time="49.88313540629925">
+      <failure />
+    </testcase>
+  </testsuite>
+</testsuites>

dev/sim/coco/tb.cpp

@@ -0,0 +1,250 @@
+// simple verilator top
+/*
+doesn't build on 4.106 (at least)
+*/
+
+#define TRACING
+
+#include <cstddef>
+#include <iostream>
+#include <iomanip>
+
+#include "verilated.h"
+#include "Vc.h"
+
+#ifdef TRACING
+#include "verilated_vcd_c.h"
+VerilatedVcdC *t;
+#else
+unsigned int t = 0;
+#endif
+
+/*
+#include "uart/uartsim.h"
+*/
+
+Vc* m;
+
+vluint64_t main_time = 0;     // in units of timeprecision used in verilog or --timescale-override
+// what is it?  it changed to 941621251 after calling loadmem()
+
+double sc_time_stamp() {      // $time in verilog
+   return main_time;
+}
+
+const int resetCycle = 10;
+const int threadRunCycle = 200;
+const int runCycles = 1000;
+const int hbCycles = 500;
+const int threads = 1;  // needs a more realistic a2l2 data return to work in smt
+
+/*
+
+ 143              	# -------------------------------------------------------------------------------------------------
+ 144              	# enable smt2 and branch in different locs (driver returns b +64 if doesnt hit actual ops)
+ 145              	# 32b mode until msr[32]=1
+ 146
+ 147 0344 480000BC 	.align 8
+ 147      60000000
+ 147      60000000
+ 147      60000000
+ 147      60000000
+ 148              	boot_start:
+ 149
+ 150 0400 38200003 	      li        r1,0x3
+ 151 0404 7C366BA6 	      mtspr     tens,r1          # 62:63 = tid 1:0 enabled
+ 152 0408 7C3E6AA6 	      mfspr     r1,tir           # who am i?
+ *** appears to need an isync here!  cr is not correct w/o it (old r1?)
+ 153 040c 2C010000 	      cmpwi     r1,0x00
+ 154 0410 38202000 	      li        r1,0x2000         # change to use 660 so stay in page 0
+ 155 0414 41820008 	      beq       t0
+ 156              	t1:
+ 157 0418 5421103A 	      slwi      r1,r1,2          # change to addi so stay in page 0
+ 158              	t0:
+ 160 041c 7C2903A6 	      mtctr     r1
+ 161 0420 4E800420 	      bctr                       # off to neverneverland
+
+
+ 162 041c 7C2FCBA6 	      mtspr      tar,r1
+ 163 0420 4E800460 	      bctar      0x14,0,0
+
+ 4C00012C 	      isync
+
+
+*/
+
+int mem[1024];      // 4B*1K
+
+void loadmem(void) {
+   int adr;
+   mem[0x0000/4] = 0x48000400;
+   adr = 0x400/4;
+
+   mem[adr++] = threads == 1 ? 0x38200001 : 0x38200003;
+   mem[adr++] = 0x7C366BA6;
+   mem[adr++] = 0x7C366BA6;
+   mem[adr++] = 0x7C3E6AA6;
+   mem[adr++] = 0x4C00012C;
+   mem[adr++] = 0x2C010000;
+   mem[adr++] = 0x38200660;
+   mem[adr++] = 0x41820008;
+   mem[adr++] = 0x38210100;
+   mem[adr++] = 0x7C2903A6;
+   mem[adr++] = 0x4E800420;
+
+}
+
+// nclk = (clk,reset,clk2x,clk4x,-,-)
+
+int main(int argc, char **argv) {
+   using namespace std;
+
+   loadmem();
+
+   cout << setfill('0');
+
+   Verilated::commandArgs(argc, argv);
+   m = new Vc;
+
+#ifdef TRACING
+      Verilated::traceEverOn(true);
+      t = new VerilatedVcdC;
+      m->trace(t, 99);
+      t->open("wtf.vcd");
+      cout << "Tracing enabled." << endl;
+#endif
+
+   bool resetDone = false;
+   unsigned int threadStop = 0x3;
+
+   unsigned int tick = 0;
+   unsigned int cycle = 1;
+   unsigned int readPending = 0;
+   unsigned int readAddr = 0;
+   unsigned int readTag = 0;
+   unsigned int readTID = 0;
+   unsigned int countReads = 0;
+
+   m->nclk = 0x3C;   // run 2x,4x = 1x
+   cout << setw(8) << cycle << "Resetting..." << endl;
+
+   m->an_ac_pm_thread_stop = threadStop;
+   cout << setw(8) << cycle << "Thread stop=" << threadStop << endl;
+
+   // can skip 4x with new gpr array
+   // 1x=4/4 2x=2/2 4x=1/1
+   //   1 1 1    7
+   //   1 1 0    6
+   //   1 0 1    5
+   //   1 0 0    4
+   //   0 1 1    3
+   //   0 1 0    2
+   //   0 0 1    1
+   //   0 0 0    0
+   // (insert reset)
+   //const int clocks[8] = {11, 0, 11, 0, 11, 0, 11, 0}; // 2x,4x == 1x
+   const int clocks[8] = {11, 10, 9, 8, 3, 2, 1, 0};     // 1x, 2x, 4x
+   const int ticks1x = 8;
+
+   while (!Verilated::gotFinish()) {
+
+      if (!resetDone && (cycle > resetCycle)) {
+         m->nclk &= 0x2F;
+         cout << setw(8) << cycle << "Releasing reset." << endl;
+         resetDone = true;
+      }
+
+      if (threadStop && (cycle > threadRunCycle)) {
+         threadStop = 0x0;
+         m->an_ac_pm_thread_stop = threadStop;
+         cout << setw(8) << cycle << "Thread stop=" << threadStop << endl;
+      }
+
+      m->nclk = (m->nclk & 0x10) | (clocks[tick % 8] << 2);
+      tick++;
+      m->eval();
+
+      // bus is 1x clock
+      if ((tick % ticks1x) == 0) {
+
+         if (readPending == cycle) { // i=1
+
+            m->an_ac_reld_data_vld = 1;
+            m->an_ac_reld_core_tag = readTag;
+            m->an_ac_reld_qw = 0;
+            m->an_ac_reld_crit_qw = 1;
+
+            if (readAddr == 0xFFFFFFF0) {
+
+               m->an_ac_reld_data[3]= 0x00000000;     // 0
+               m->an_ac_reld_data[2]= 0x00000000;     // 4
+               m->an_ac_reld_data[1]= 0x00000000;     // 8
+               m->an_ac_reld_data[0]= 0x48000002;     // C
+
+            } else if (readAddr < 0x0500) {
+
+               m->an_ac_reld_data[3]= mem[readAddr/4+0];
+               m->an_ac_reld_data[2]= mem[readAddr/4+1];
+               m->an_ac_reld_data[1]= mem[readAddr/4+2];
+               m->an_ac_reld_data[0]= mem[readAddr/4+3];
+
+            } else {
+
+               m->an_ac_reld_data[3]= 0x48000040;
+               m->an_ac_reld_data[2]= 0x00000000;
+               m->an_ac_reld_data[1]= 0x00000000;
+               m->an_ac_reld_data[0]= 0x00000000;
+
+            }
+            readPending = 0;
+            countReads++;
+            cout << setw(8) << cycle << " an_ac_rsp: data="<< hex << uppercase << setw(8) << m->an_ac_reld_data[3]
+               << hex << uppercase << setw(8) << m->an_ac_reld_data[2]
+               << hex << uppercase << setw(8) << m->an_ac_reld_data[1]
+               << hex << uppercase << setw(8) << m->an_ac_reld_data[0]
+               << dec << nouppercase << endl;
+         } else {
+            m->an_ac_reld_data_vld = 0;
+         }
+
+         m->an_ac_req_ld_pop = 0;
+         if (!readPending && m->ac_an_req) {
+            readAddr = m->ac_an_req_ra;
+            readTag = m->ac_an_req_ld_core_tag;
+            readTID = m->ac_an_req_thread;
+            readPending = cycle + 3;
+            cout << setw(8) << cycle << " ac_an_req: T" << readTID << " ra=" << hex << uppercase <<  setw(8) << readAddr << dec << nouppercase << endl;
+            m->an_ac_req_ld_pop = 1;
+         }
+
+      }
+
+      // finish clock stuff
+      if ((tick % ticks1x) == 0) {
+         cycle++;
+         if ((cycle % hbCycles) == 0) {
+            cout << setw(8) << cycle << " ...tick..." << endl;
+         }
+      }
+      #ifdef TRACING
+      t->dump(tick);
+      t->flush();
+      #endif
+
+      // check for fails
+
+      // hit limit
+      if (cycle > runCycles) {
+         break;
+      }
+
+   }
+
+#ifdef TRACING
+   t->close();
+#endif
+   m->final();
+
+   exit(EXIT_SUCCESS);
+
+}

dev/sim/coco/tb.py

@@ -0,0 +1,307 @@
+# a2o test tb
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import Timer
+from cocotb.triggers import FallingEdge
+from cocotb.handle import Force
+from cocotb.handle import Release
+
+import itertools
+from dotmap import DotMap
+
+from OPEnv import *
+from A2L2 import *
+
+# ------------------------------------------------------------------------------------------------
+# Tasks
+
+# get rid of z on anything that will be sampled here
+# is there a func to get all inputs?
+async def init(dut, sim):
+   """Initialize inputs. """
+
+   dut.nclk.value = 0
+   dut.scan_in.value = 0
+   dut.an_ac_scan_type_dc.value = 0x0
+   dut.an_ac_chipid_dc.value = 0x0
+   dut.an_ac_coreid.value = 0x0
+   dut.an_ac_scom_sat_id.value = 0x0
+
+   dut.an_ac_lbist_ary_wrt_thru_dc.value = 0
+   dut.an_ac_gsd_test_enable_dc.value = 0
+   dut.an_ac_gsd_test_acmode_dc.value = 0
+   dut.an_ac_ccflush_dc.value = 0
+   dut.an_ac_ccenable_dc.value = 0
+   dut.an_ac_lbist_en_dc.value = 0
+   dut.an_ac_lbist_ip_dc.value = 0
+   dut.an_ac_lbist_ac_mode_dc.value = 0
+   dut.an_ac_scan_diag_dc.value = 0
+   dut.an_ac_scan_dis_dc_b.value = 0
+
+   dut.an_ac_rtim_sl_thold_8.value = 0
+   dut.an_ac_func_sl_thold_8.value = 0
+   dut.an_ac_func_nsl_thold_8.value = 0
+   dut.an_ac_ary_nsl_thold_8.value = 0
+   dut.an_ac_sg_8.value = 0
+   dut.an_ac_fce_8.value = 0
+   dut.an_ac_abst_scan_in.value = 0
+
+   dut.an_ac_checkstop.value = 0
+
+   dut.an_ac_reset_1_complete.value = 0
+   dut.an_ac_reset_2_complete.value = 0
+   dut.an_ac_reset_3_complete.value = 0
+   dut.an_ac_reset_wd_complete.value = 0
+
+   dut.an_ac_pm_fetch_halt.value = 0
+   dut.an_ac_debug_stop.value = 0
+
+   dut.an_ac_tb_update_enable.value = 1
+   dut.an_ac_tb_update_pulse.value = 0 # tb clock if xucr0[tcs]=1 (must be <1/2 proc clk; tb pulse is 2x this clock)
+
+   # why is coco turning [0] into non-vector??? or is that gpi/vpi/icarus/???
+   if sim.threads == 1:
+      dut.an_ac_pm_thread_stop.value = 0x1
+      dut.an_ac_external_mchk.value = 0
+      dut.an_ac_sleep_en.value = 0
+      dut.an_ac_ext_interrupt.value = 0
+      dut.an_ac_crit_interrupt.value = 0
+      dut.an_ac_perf_interrupt.value = 0
+      dut.an_ac_hang_pulse.value = 0
+      dut.an_ac_uncond_dbg_event.value = 0
+   else:
+      for i in range(sim.threads):
+         dut.an_ac_pm_thread_stop[i].value = 0x1
+         dut.an_ac_external_mchk[i].value = 0
+         dut.an_ac_sleep_en[i].value = 0
+         dut.an_ac_ext_interrupt[i].value = 0
+         dut.an_ac_crit_interrupt[i].value = 0
+         dut.an_ac_perf_interrupt[i].value = 0
+         dut.an_ac_hang_pulse[i].value = 0
+         dut.an_ac_uncond_dbg_event[i].value = 0
+
+   await Timer(9, units='ns')
+
+async def config(dut, sim):
+   """Configure core, etc. """
+
+   #wtf make A2 module to do core-specific stuff
+   # A2L2 load/store credits
+   creditsLd = dut.c0.lq0.lsq.arb.load_cred_cnt_d           # 8 max
+   creditsLdMax = dut.c0.lq0.lsq.arb.ld_cred_max            # hdw check
+   creditsSt = dut.c0.lq0.lsq.arb.store_cred_cnt_d          # 32 max
+   creditsStMax = dut.c0.lq0.lsq.arb.st_cred_max            # hdw check
+   creditsLdStSingle = dut.c0.lq0.lsq.arb.spr_xucr0_cred_d.value   # 1 total credit
+   #wtf this affects A2L2 - default=1
+   #creditsLdStSingle = dut.c0.lq0.lsq.arb.spr_lsucr0_b2b_q.value   # 0=crit first, every other 1=crit first, b2b **the a2l2 spec does not say crit must be first**
+
+   await RisingEdge(dut.clk_1x)
+
+   if sim.config.core.creditsLd is not None:
+      creditsLd.value = Force(sim.config.core.creditsLd)
+      creditsLdMax.value = Force(sim.config.core.creditsLd)
+      sim.msg(f'A2L2: load credits changed from {creditsLd.value.integer} to {sim.config.core.creditsLd}.')
+      await RisingEdge(dut.clk_1x)
+      creditsLd.value = Release()
+
+   if sim.config.core.creditsSt is not None:
+      creditsSt.value = Force(sim.config.core.creditsSt)
+      creditsStMax.value = Force(sim.config.core.creditsSt)
+      sim.msg(f'A2L2: store credits changed from {creditsSt.value.integer} to {sim.config.core.creditsSt}.')
+      await RisingEdge(dut.clk_1x)
+      creditsSt.value = Release()
+
+   if sim.config.core.creditsLdStSingle:
+      creditsLdStSingle = Force(1)
+      sim.msg(f'A2L2: only one load OR store allowed when credits=1/1.')
+      await RisingEdge(dut.clk_1x)
+      creditsLdStSingle.value = Release()
+
+   await RisingEdge(dut.clk_1x)
+
+async def coreMonitor(dut, sim):
+   """Watch for core events. """
+
+   me = 'a2oMonitor'
+
+   # errors
+   creditsLdErr = dut.c0.lq0.lsq.arb.ld_cred_err_q
+   creditsStErr = dut.c0.lq0.lsq.arb.st_cred_err_q
+
+   # watches
+   iu0Comp = dut.c0.iu_lq_i0_completed
+   iu0CompIFAR = dut.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar
+   iu1Comp = dut.c0.iu_lq_i1_completed
+   iu1CompIFAR = dut.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar
+   iuCompFlushIFAR = dut.c0.cp_t0_flush_ifar
+   cp3NIA = dut.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp3_nia_q           # nia after last cycle's completions
+
+   # queue depths, etc.
+
+   errors = [
+      {'name': 'Load Credits', 'sig': creditsLdErr},
+      {'name': 'Store Credits', 'sig': creditsStErr},
+   ]
+
+   done = False
+
+   while not done:
+
+      await RisingEdge(dut.clk_1x)
+
+      for i in range(len(errors)):
+          assert errors[i]['sig'].value == 0, f'{me} Error: {errors[i]["name"]}'
+
+      comp = ''
+      if iu0Comp.value == 1:
+         comp = f'0:{int(iu0CompIFAR.value.binstr + "00", 2):06X} '
+
+      if iu1Comp.value == 1:
+         comp = f'{comp}1:{int(iu1CompIFAR.value.binstr + "00", 2):06X} '
+
+      if comp != '':
+         comp = f'{comp}{int(iuCompFlushIFAR.value.binstr + "00", 2):016X}'
+         sim.msg(f'C0: CP {comp}')
+
+
+# trilib/tri.vh:`define  NCLK_WIDTH  6   // 0  1xClk, 1  Reset, 2  2xClk, 3  4xClk,  4  Even .5xClk,  5 Odd .5xClk
+async def genReset(dut, sim):
+   """Generate reset. """
+
+   first = True
+   done = False
+
+   while not done:
+      await RisingEdge(dut.clk_1x)
+      if sim.cycle < sim.resetCycle:
+         if first:
+            dut._log.info(f'[{sim.cycle:08d}] Resetting...')
+            first = False
+         dut.nclk[1].value = 1
+      elif not done:
+         dut._log.info(f'[{sim.cycle:08d}] Releasing reset.')
+         dut.nclk[1].value = 0
+         done = True
+
+async def genClocks(dut, sim):
+   """Generate 1x, 2x, 4x clock pulses, depending on parms. """
+
+   if sim.clk2x and sim.clk4x:
+      sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
+      await cocotb.start(sim.clk1x.start())
+      sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
+      await cocotb.start(sim.clk2x.start())
+      sim.clk4x = Clock(dut.nclk[3], 2, 'ns')
+      await cocotb.start(sim.clk4x.start())
+   elif sim.clk2x:
+      sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
+      await cocotb.start(sim.clk1x.start())
+      sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
+      await cocotb.start(sim.clk2x.start())
+   else:
+      sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
+      await cocotb.start(sim.clk1x.start())
+
+
+   for cycle in range(sim.maxCycles):
+
+      sim.cycle = cycle
+
+      if cycle % sim.hbCycles == 0:
+         dut._log.info(f'[{cycle:08d}] ...tick...')
+
+      await RisingEdge(dut.clk_1x)
+
+   dut._log.info(f'[{sim.cycle:08d}] Reached max cycle.  Clocks stopped.')
+
+# ------------------------------------------------------------------------------------------------
+# Interfaces
+
+# SCOM
+async def scom(dut, sim):
+   """scom interface"""
+
+   dut.an_ac_scom_dch.value = 0
+   dut.an_ac_scom_cch.value = 0
+
+
+# ------------------------------------------------------------------------------------------------
+# Do something
+
+@cocotb.test()
+async def tb(dut):
+   """A Vulgar Display of OpenPower"""
+
+   sim = Sim(dut)
+   sim.mem = Memory(sim)
+   #sim.memFiles = ['../mem/boot_ieq1.bin.hex'] #wtf cmdline parm
+   sim.memFiles = ['../mem/boot.bin.hex'] #wtf cmdline parm
+
+   for i in range(len(sim.memFiles)):  #wtf el should be object with name, format, etc.
+      sim.mem.loadFile(sim.memFiles[i])
+   if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default:
+      sim.mem.write(sim.resetAddr, sim.resetOp)
+      sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.')
+
+#  dut.cocotb_icarus
+#  dut._log.info(sim.top.__dict__)
+#  {'_handle': <cocotb.simulator.gpi_sim_hdl at 0x55f8fa8a3aa0>,
+#   '_len': None, '_sub_handles': {}, '_invalid_sub_handles': set(), '_name': 'cocotb_icarus',
+#   '_type': 'GPI_MODULE', '_fullname': 'cocotb_icarus(GPI_MODULE)', '_path': 'cocotb_icarus.cocotb_icarus',
+#   '_log': <SimBaseLog cocotb.cocotb_icarus (INFO)>, '_def_name': 'cocotb_icarus', '_def_file': './cocotb_icarus.v',
+#   '_discovered': False
+#  }
+#  dut
+#  {'_handle': <cocotb.simulator.gpi_sim_hdl at 0x557757943540>,
+#   '_len': None, '_sub_handles': {'an_ac_pm_thread_stop': ModifiableObject(cocotb_icarus.an_ac_pm_thread_stop),
+#   'cocotb_icarus': HierarchyObject(cocotb_icarus.cocotb_icarus with definition cocotb_icarus (at ./cocotb_icarus.v))},
+#   '_invalid_sub_handles': set(), '_name': 'cocotb_icarus', '_type': 'GPI_MODULE', '_fullname': 'cocotb_icarus(GPI_MODULE)',
+#   '_path': 'cocotb_icarus', '_log': <SimBaseLog cocotb.cocotb_icarus (INFO)>, '_def_name': '', '_def_file': '',
+#   '_discovered': False
+
+   # init stuff
+   await init(dut, sim)
+
+   # start clocks,reset
+   await cocotb.start(genClocks(dut, sim))
+   await cocotb.start(genReset(dut, sim))
+
+   # start interfaces
+   await cocotb.start(scom(dut, sim))
+
+   #wtf don't have to instantiate A2L2 first?
+   #await cocotb.start(A2L2Driver(dut, sim))
+   #await cocotb.start(A2L2Checker(dut, sim))
+   #await cocotb.start(A2L2Monitor(dut, sim))
+   await cocotb.start(A2L2.driver(dut, sim))
+   await cocotb.start(A2L2.checker(dut, sim))
+   await cocotb.start(A2L2.monitor(dut, sim))
+
+   await Timer((sim.resetCycle + 5)*8, units='ns')
+   if dut.nclk[1].value != 0:
+      sim.ok = False
+      sim.fail = 'Reset active too long!'
+
+   # config stuff
+   await config(dut, sim)
+
+   # monitor stuff
+   await cocotb.start(coreMonitor(dut, sim))
+
+   # release thread(s)
+   dut.an_ac_pm_thread_stop.value = 0
+   await RisingEdge(dut.clk_1x)
+   dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')
+
+
+
+   # should await sim.done
+   await Timer((sim.maxCycles+100)*8, units='ns')
+
+   if sim.ok:
+      dut._log.info(f'[{sim.cycle:08d}] You has opulence.')
+   else:
+      dut._log.info(f'[{sim.cycle:08d}] You are worthless and weak!')
+      assert False, f'[{sim.cycle:08d}] {sim.fail}'
+

dev/sim/coco/verilog

@@ -0,0 +1 @@
+../../verilog

dev/sim/gtkwave/gtkf-64L.py

@@ -0,0 +1,32 @@
+#!/usr/bin/python3
+# gtkwave process filter
+#
+# return left 64 of binary
+
+import sys
+
+fi = sys.stdin
+fo = sys.stdout
+fe = sys.stderr
+
+def dbg(m):
+   fe.write(m + '\n')
+   fe.flush()
+
+def main():
+
+   while True:
+
+      line = fi.readline()
+      if not line:
+         return 0
+
+      try:
+         fo.write(f'{int(line[0:32],2):08X}{int(line[32:65],2):08X}\n')
+      except:
+         fo.write('\n')
+
+      fo.flush()
+
+if __name__ == '__main__':
+   sys.exit(main())

dev/sim/gtkwave/gtkf-64R.py

@@ -0,0 +1,32 @@
+#!/usr/bin/python3
+# gtkwave process filter
+#
+# return right 64 of binary
+
+import sys
+
+fi = sys.stdin
+fo = sys.stdout
+fe = sys.stderr
+
+def dbg(m):
+   fe.write(m + '\n')
+   fe.flush()
+
+def main():
+
+   while True:
+
+      line = fi.readline()
+      if not line:
+         return 0
+
+      try:
+         fo.write(f'{int(line[-65:-33],2):08X}{int(line[-33:-1],2):08X}\n')
+      except:
+         fo.write('\n')
+
+      fo.flush()
+
+if __name__ == '__main__':
+   sys.exit(main())

dev/sim/gtkwave/gtkf-a2l2.py

@@ -0,0 +1,943 @@
+#!/usr/bin/python3
+# gtkwave transaction filter
+
+# interpret a2l2 (req) interface
+# needs:
+#   track multiple outstanding and out-of-order;
+#   update to show active tag list (credits), etc.
+#
+# select the signals; F4; name it; format->binary; format->transaction filter; select the signals and create group
+
+import sys
+import tempfile
+import subprocess
+
+fi = sys.stdin
+fo = sys.stdout
+fe = sys.stderr
+
+debug = False
+
+def dbg(m):
+   if debug:
+      fe.write(m + '\n')
+      fe.flush()
+
+filterName = 'A2L2 Decode'
+transColor = 'DarkRed'
+
+colors = {
+   #'default':'DeepSkyBlue',
+   'default':'black',
+   'data':'DarkGray',
+   'bctr':'DarkOrange'
+}
+
+sigs = [None] * 30
+sigNames = {
+   'ac_an_req' : None,
+   'ac_an_req_ra[22:63]' : 'RA',
+   'ac_an_req_thread[0:2]' : 'T',
+   'ac_an_req_ttype[0:5]' : 'TT',
+   'ac_an_req_tag[0:5]' : 'Tag',
+   'ac_an_req_wimg_w' : 'W',
+   'ac_an_req_wimg_i' : 'I',
+   'ac_an_req_wimg_m' : 'M',
+   'ac_an_req_wimg_g' : 'G',
+}
+sigTypes = {
+   'RA' : ('08X',),
+   'T': ('X',),
+   'TT' : ('02X',),
+   'Tag' : ('02X',),
+   'W' : ('nz', 'X'),
+   'I' : ('nz', 'X'),
+   'M' : ('nz', 'X'),
+   'G' : ('nz', 'X'),
+}
+
+trans = []
+numTrans = 0
+
+class Sig():
+   def __init__(self, name):
+      self.name = name
+      self.values = []
+   def addValue(self, t, v):
+      self.values.append((t,v))
+
+class Trans():
+   def __init__(self):
+      self.timeReq = 0
+      self.timeDVal = 0
+      self.timeLast = 0
+      self.props = {}
+
+# the last value of each sig is in this transaction (req=1)
+def addTrans(time):
+   global numTrans
+   t = Trans()
+   t.timeReq = time
+   for i in range(len(sigs)):
+      if sigs[i] == None:
+         continue
+      t.props[sigs[i].name] = sigs[i].values[-1][1]
+   trans.append(t)
+   numTrans += 1
+
+def main():
+
+   t  = f'$name {filterName}\n'
+   t += '#0\n'
+
+   inDumpVars = False
+   startTrans = False
+   inTrans = False
+
+   while True:
+
+      l = fi.readline()
+      if not l:
+         return 0
+
+      dbg(l)
+
+      if l.startswith('#'):         # time
+         if startTrans:
+            dbg('start trans\n')
+            addTrans(varTime)
+            startTrans = False
+            inTrans = True
+         varTime = int(l[1:-1])
+      elif inDumpVars:
+         if l.startswith('$comment data_end'):
+            inDumpVars = False
+            if inTrans:
+               addTrans(varTime)
+               inTrans = False
+         elif l.startswith('$'):    # ?
+            pass
+         else:                      # value will be either 'vec num' or 'bn' (b=bit,n=num)
+            if ' ' in l:            # vector
+               v = l.split()[0]
+               if 'x' in v or 'z' in v:
+                  v = '0'           # could mark it and check later
+               elif v[0] == 'b':
+                  v = hex(int(v[1:], 2))
+               elif v[0] == 'x':
+                  v = v[1:]
+               n = int(l.split()[1])
+            else:                   # bit
+               v = l[0]
+               n = int(l[1:])
+            sigs[n-1].addValue(varTime, v)
+            dbg(f'sig {n-1} {v}\n')
+            if sigs[n-1].name == 'ac_an_req':
+               dbg(f'transig: {n-1} {v}\n')
+               if v == '1':
+                  startTrans = True
+                  dbg('about to start trans\n')
+            elif sigs[n-1].name == 'an_ac_reld_data_vld':
+               if v == '1':
+                  trans[-1].timeDVal = varTime
+                  trans[-1].timeLast = varTime
+                  inTrans = False
+      elif l.startswith('$var '):
+         tokens = l.split()      # $var wire 3 2 ac_an_req_thread[0:2] $end  3=width 2=index
+         n = int(tokens[3]) - 1
+         sigs[n] = Sig(tokens[4])
+      elif l.startswith('$dumpvars'):
+         inDumpVars = True
+      else:
+         #t += '#' + str(i) + ' ' + l + '\n'
+         pass
+
+      if l.startswith('$comment data_end'):
+         # a transaction starts every req=1 cycle
+         t = ''
+         for i in range(len(trans)):
+            t += f'#{trans[i].timeReq} ?{transColor}?'
+            for p in trans[i].props:
+               if p in sigNames and sigNames[p] is not None:
+                  n = sigNames[p]
+                  if n in sigTypes and sigTypes[n][0] == 'nz':
+                     if trans[i].props[p] == '1':
+                        t += f'{n}:{int(trans[i].props[p], 16):{sigTypes[n][1]}} '
+                  elif n in sigTypes:
+                     dbg(f'{trans[i].props[p]}\n')
+                     if n == 'T':
+                        t += f'{n}{int(trans[i].props[p], 16):{sigTypes[n][0]}} '
+                     elif n == 'TT' and trans[i].props[p] == '0x0':
+                        t += 'IFETCH '
+                     else:
+                        t += f'{n}:{int(trans[i].props[p], 16):{sigTypes[n][0]}} '
+                  else:
+                     t += f'{n}:{trans[i].props[p]} '
+            t += '\n'
+            t += f'#{trans[i].timeLast}\n'   # may need to wait till next cyc in case req on back-back?
+         t += '$finish\n'
+         fo.write(f'{t}')
+         fo.flush()
+
+
+if __name__ == '__main__':
+	sys.exit(main())
+
+'''
+rgb.c from gtkwave
+
+static struct wave_rgb_color colors[] = {
+WAVE_RGB_COLOR("alice blue", 240, 248, 255),
+WAVE_RGB_COLOR("AliceBlue", 240, 248, 255),
+WAVE_RGB_COLOR("antique white", 250, 235, 215),
+WAVE_RGB_COLOR("AntiqueWhite", 250, 235, 215),
+WAVE_RGB_COLOR("AntiqueWhite1", 255, 239, 219),
+WAVE_RGB_COLOR("AntiqueWhite2", 238, 223, 204),
+WAVE_RGB_COLOR("AntiqueWhite3", 205, 192, 176),
+WAVE_RGB_COLOR("AntiqueWhite4", 139, 131, 120),
+WAVE_RGB_COLOR("aquamarine", 127, 255, 212),
+WAVE_RGB_COLOR("aquamarine1", 127, 255, 212),
+WAVE_RGB_COLOR("aquamarine2", 118, 238, 198),
+WAVE_RGB_COLOR("aquamarine3", 102, 205, 170),
+WAVE_RGB_COLOR("aquamarine4", 69, 139, 116),
+WAVE_RGB_COLOR("azure", 240, 255, 255),
+WAVE_RGB_COLOR("azure1", 240, 255, 255),
+WAVE_RGB_COLOR("azure2", 224, 238, 238),
+WAVE_RGB_COLOR("azure3", 193, 205, 205),
+WAVE_RGB_COLOR("azure4", 131, 139, 139),
+WAVE_RGB_COLOR("beige", 245, 245, 220),
+WAVE_RGB_COLOR("bisque", 255, 228, 196),
+WAVE_RGB_COLOR("bisque1", 255, 228, 196),
+WAVE_RGB_COLOR("bisque2", 238, 213, 183),
+WAVE_RGB_COLOR("bisque3", 205, 183, 158),
+WAVE_RGB_COLOR("bisque4", 139, 125, 107),
+WAVE_RGB_COLOR("black", 0, 0, 0),
+WAVE_RGB_COLOR("blanched almond", 255, 235, 205),
+WAVE_RGB_COLOR("BlanchedAlmond", 255, 235, 205),
+WAVE_RGB_COLOR("blue", 0, 0, 255),
+WAVE_RGB_COLOR("blue violet", 138, 43, 226),
+WAVE_RGB_COLOR("blue1", 0, 0, 255),
+WAVE_RGB_COLOR("blue2", 0, 0, 238),
+WAVE_RGB_COLOR("blue3", 0, 0, 205),
+WAVE_RGB_COLOR("blue4", 0, 0, 139),
+WAVE_RGB_COLOR("BlueViolet", 138, 43, 226),
+WAVE_RGB_COLOR("brown", 165, 42, 42),
+WAVE_RGB_COLOR("brown1", 255, 64, 64),
+WAVE_RGB_COLOR("brown2", 238, 59, 59),
+WAVE_RGB_COLOR("brown3", 205, 51, 51),
+WAVE_RGB_COLOR("brown4", 139, 35, 35),
+WAVE_RGB_COLOR("burlywood", 222, 184, 135),
+WAVE_RGB_COLOR("burlywood1", 255, 211, 155),
+WAVE_RGB_COLOR("burlywood2", 238, 197, 145),
+WAVE_RGB_COLOR("burlywood3", 205, 170, 125),
+WAVE_RGB_COLOR("burlywood4", 139, 115, 85),
+WAVE_RGB_COLOR("cadet blue", 95, 158, 160),
+WAVE_RGB_COLOR("CadetBlue", 95, 158, 160),
+WAVE_RGB_COLOR("CadetBlue1", 152, 245, 255),
+WAVE_RGB_COLOR("CadetBlue2", 142, 229, 238),
+WAVE_RGB_COLOR("CadetBlue3", 122, 197, 205),
+WAVE_RGB_COLOR("CadetBlue4", 83, 134, 139),
+WAVE_RGB_COLOR("chartreuse", 127, 255, 0),
+WAVE_RGB_COLOR("chartreuse1", 127, 255, 0),
+WAVE_RGB_COLOR("chartreuse2", 118, 238, 0),
+WAVE_RGB_COLOR("chartreuse3", 102, 205, 0),
+WAVE_RGB_COLOR("chartreuse4", 69, 139, 0),
+WAVE_RGB_COLOR("chocolate", 210, 105, 30),
+WAVE_RGB_COLOR("chocolate1", 255, 127, 36),
+WAVE_RGB_COLOR("chocolate2", 238, 118, 33),
+WAVE_RGB_COLOR("chocolate3", 205, 102, 29),
+WAVE_RGB_COLOR("chocolate4", 139, 69, 19),
+WAVE_RGB_COLOR("coral", 255, 127, 80),
+WAVE_RGB_COLOR("coral1", 255, 114, 86),
+WAVE_RGB_COLOR("coral2", 238, 106, 80),
+WAVE_RGB_COLOR("coral3", 205, 91, 69),
+WAVE_RGB_COLOR("coral4", 139, 62, 47),
+WAVE_RGB_COLOR("cornflower blue", 100, 149, 237),
+WAVE_RGB_COLOR("CornflowerBlue", 100, 149, 237),
+WAVE_RGB_COLOR("cornsilk", 255, 248, 220),
+WAVE_RGB_COLOR("cornsilk1", 255, 248, 220),
+WAVE_RGB_COLOR("cornsilk2", 238, 232, 205),
+WAVE_RGB_COLOR("cornsilk3", 205, 200, 177),
+WAVE_RGB_COLOR("cornsilk4", 139, 136, 120),
+WAVE_RGB_COLOR("cyan", 0, 255, 255),
+WAVE_RGB_COLOR("cyan1", 0, 255, 255),
+WAVE_RGB_COLOR("cyan2", 0, 238, 238),
+WAVE_RGB_COLOR("cyan3", 0, 205, 205),
+WAVE_RGB_COLOR("cyan4", 0, 139, 139),
+WAVE_RGB_COLOR("dark blue", 0, 0, 139),
+WAVE_RGB_COLOR("dark cyan", 0, 139, 139),
+WAVE_RGB_COLOR("dark goldenrod", 184, 134, 11),
+WAVE_RGB_COLOR("dark gray", 169, 169, 169),
+WAVE_RGB_COLOR("dark green", 0, 100, 0),
+WAVE_RGB_COLOR("dark grey", 169, 169, 169),
+WAVE_RGB_COLOR("dark khaki", 189, 183, 107),
+WAVE_RGB_COLOR("dark magenta", 139, 0, 139),
+WAVE_RGB_COLOR("dark olive green", 85, 107, 47),
+WAVE_RGB_COLOR("dark orange", 255, 140, 0),
+WAVE_RGB_COLOR("dark orchid", 153, 50, 204),
+WAVE_RGB_COLOR("dark red", 139, 0, 0),
+WAVE_RGB_COLOR("dark salmon", 233, 150, 122),
+WAVE_RGB_COLOR("dark sea green", 143, 188, 143),
+WAVE_RGB_COLOR("dark slate blue", 72, 61, 139),
+WAVE_RGB_COLOR("dark slate gray", 47, 79, 79),
+WAVE_RGB_COLOR("dark slate grey", 47, 79, 79),
+WAVE_RGB_COLOR("dark turquoise", 0, 206, 209),
+WAVE_RGB_COLOR("dark violet", 148, 0, 211),
+WAVE_RGB_COLOR("DarkBlue", 0, 0, 139),
+WAVE_RGB_COLOR("DarkCyan", 0, 139, 139),
+WAVE_RGB_COLOR("DarkGoldenrod", 184, 134, 11),
+WAVE_RGB_COLOR("DarkGoldenrod1", 255, 185, 15),
+WAVE_RGB_COLOR("DarkGoldenrod2", 238, 173, 14),
+WAVE_RGB_COLOR("DarkGoldenrod3", 205, 149, 12),
+WAVE_RGB_COLOR("DarkGoldenrod4", 139, 101, 8),
+WAVE_RGB_COLOR("DarkGray", 169, 169, 169),
+WAVE_RGB_COLOR("DarkGreen", 0, 100, 0),
+WAVE_RGB_COLOR("DarkGrey", 169, 169, 169),
+WAVE_RGB_COLOR("DarkKhaki", 189, 183, 107),
+WAVE_RGB_COLOR("DarkMagenta", 139, 0, 139),
+WAVE_RGB_COLOR("DarkOliveGreen", 85, 107, 47),
+WAVE_RGB_COLOR("DarkOliveGreen1", 202, 255, 112),
+WAVE_RGB_COLOR("DarkOliveGreen2", 188, 238, 104),
+WAVE_RGB_COLOR("DarkOliveGreen3", 162, 205, 90),
+WAVE_RGB_COLOR("DarkOliveGreen4", 110, 139, 61),
+WAVE_RGB_COLOR("DarkOrange", 255, 140, 0),
+WAVE_RGB_COLOR("DarkOrange1", 255, 127, 0),
+WAVE_RGB_COLOR("DarkOrange2", 238, 118, 0),
+WAVE_RGB_COLOR("DarkOrange3", 205, 102, 0),
+WAVE_RGB_COLOR("DarkOrange4", 139, 69, 0),
+WAVE_RGB_COLOR("DarkOrchid", 153, 50, 204),
+WAVE_RGB_COLOR("DarkOrchid1", 191, 62, 255),
+WAVE_RGB_COLOR("DarkOrchid2", 178, 58, 238),
+WAVE_RGB_COLOR("DarkOrchid3", 154, 50, 205),
+WAVE_RGB_COLOR("DarkOrchid4", 104, 34, 139),
+WAVE_RGB_COLOR("DarkRed", 139, 0, 0),
+WAVE_RGB_COLOR("DarkSalmon", 233, 150, 122),
+WAVE_RGB_COLOR("DarkSeaGreen", 143, 188, 143),
+WAVE_RGB_COLOR("DarkSeaGreen1", 193, 255, 193),
+WAVE_RGB_COLOR("DarkSeaGreen2", 180, 238, 180),
+WAVE_RGB_COLOR("DarkSeaGreen3", 155, 205, 155),
+WAVE_RGB_COLOR("DarkSeaGreen4", 105, 139, 105),
+WAVE_RGB_COLOR("DarkSlateBlue", 72, 61, 139),
+WAVE_RGB_COLOR("DarkSlateGray", 47, 79, 79),
+WAVE_RGB_COLOR("DarkSlateGray1", 151, 255, 255),
+WAVE_RGB_COLOR("DarkSlateGray2", 141, 238, 238),
+WAVE_RGB_COLOR("DarkSlateGray3", 121, 205, 205),
+WAVE_RGB_COLOR("DarkSlateGray4", 82, 139, 139),
+WAVE_RGB_COLOR("DarkSlateGrey", 47, 79, 79),
+WAVE_RGB_COLOR("DarkTurquoise", 0, 206, 209),
+WAVE_RGB_COLOR("DarkViolet", 148, 0, 211),
+WAVE_RGB_COLOR("deep pink", 255, 20, 147),
+WAVE_RGB_COLOR("deep sky blue", 0, 191, 255),
+WAVE_RGB_COLOR("DeepPink", 255, 20, 147),
+WAVE_RGB_COLOR("DeepPink1", 255, 20, 147),
+WAVE_RGB_COLOR("DeepPink2", 238, 18, 137),
+WAVE_RGB_COLOR("DeepPink3", 205, 16, 118),
+WAVE_RGB_COLOR("DeepPink4", 139, 10, 80),
+WAVE_RGB_COLOR("DeepSkyBlue", 0, 191, 255),
+WAVE_RGB_COLOR("DeepSkyBlue1", 0, 191, 255),
+WAVE_RGB_COLOR("DeepSkyBlue2", 0, 178, 238),
+WAVE_RGB_COLOR("DeepSkyBlue3", 0, 154, 205),
+WAVE_RGB_COLOR("DeepSkyBlue4", 0, 104, 139),
+WAVE_RGB_COLOR("dim gray", 105, 105, 105),
+WAVE_RGB_COLOR("dim grey", 105, 105, 105),
+WAVE_RGB_COLOR("DimGray", 105, 105, 105),
+WAVE_RGB_COLOR("DimGrey", 105, 105, 105),
+WAVE_RGB_COLOR("dodger blue", 30, 144, 255),
+WAVE_RGB_COLOR("DodgerBlue", 30, 144, 255),
+WAVE_RGB_COLOR("DodgerBlue1", 30, 144, 255),
+WAVE_RGB_COLOR("DodgerBlue2", 28, 134, 238),
+WAVE_RGB_COLOR("DodgerBlue3", 24, 116, 205),
+WAVE_RGB_COLOR("DodgerBlue4", 16, 78, 139),
+WAVE_RGB_COLOR("firebrick", 178, 34, 34),
+WAVE_RGB_COLOR("firebrick1", 255, 48, 48),
+WAVE_RGB_COLOR("firebrick2", 238, 44, 44),
+WAVE_RGB_COLOR("firebrick3", 205, 38, 38),
+WAVE_RGB_COLOR("firebrick4", 139, 26, 26),
+WAVE_RGB_COLOR("floral white", 255, 250, 240),
+WAVE_RGB_COLOR("FloralWhite", 255, 250, 240),
+WAVE_RGB_COLOR("forest green", 34, 139, 34),
+WAVE_RGB_COLOR("ForestGreen", 34, 139, 34),
+WAVE_RGB_COLOR("gainsboro", 220, 220, 220),
+WAVE_RGB_COLOR("ghost white", 248, 248, 255),
+WAVE_RGB_COLOR("GhostWhite", 248, 248, 255),
+WAVE_RGB_COLOR("gold", 255, 215, 0),
+WAVE_RGB_COLOR("gold1", 255, 215, 0),
+WAVE_RGB_COLOR("gold2", 238, 201, 0),
+WAVE_RGB_COLOR("gold3", 205, 173, 0),
+WAVE_RGB_COLOR("gold4", 139, 117, 0),
+WAVE_RGB_COLOR("goldenrod", 218, 165, 32),
+WAVE_RGB_COLOR("goldenrod1", 255, 193, 37),
+WAVE_RGB_COLOR("goldenrod2", 238, 180, 34),
+WAVE_RGB_COLOR("goldenrod3", 205, 155, 29),
+WAVE_RGB_COLOR("goldenrod4", 139, 105, 20),
+WAVE_RGB_COLOR("gray", 190, 190, 190),
+WAVE_RGB_COLOR("gray0", 0, 0, 0),
+WAVE_RGB_COLOR("gray1", 3, 3, 3),
+WAVE_RGB_COLOR("gray10", 26, 26, 26),
+WAVE_RGB_COLOR("gray100", 255, 255, 255),
+WAVE_RGB_COLOR("gray11", 28, 28, 28),
+WAVE_RGB_COLOR("gray12", 31, 31, 31),
+WAVE_RGB_COLOR("gray13", 33, 33, 33),
+WAVE_RGB_COLOR("gray14", 36, 36, 36),
+WAVE_RGB_COLOR("gray15", 38, 38, 38),
+WAVE_RGB_COLOR("gray16", 41, 41, 41),
+WAVE_RGB_COLOR("gray17", 43, 43, 43),
+WAVE_RGB_COLOR("gray18", 46, 46, 46),
+WAVE_RGB_COLOR("gray19", 48, 48, 48),
+WAVE_RGB_COLOR("gray2", 5, 5, 5),
+WAVE_RGB_COLOR("gray20", 51, 51, 51),
+WAVE_RGB_COLOR("gray21", 54, 54, 54),
+WAVE_RGB_COLOR("gray22", 56, 56, 56),
+WAVE_RGB_COLOR("gray23", 59, 59, 59),
+WAVE_RGB_COLOR("gray24", 61, 61, 61),
+WAVE_RGB_COLOR("gray25", 64, 64, 64),
+WAVE_RGB_COLOR("gray26", 66, 66, 66),
+WAVE_RGB_COLOR("gray27", 69, 69, 69),
+WAVE_RGB_COLOR("gray28", 71, 71, 71),
+WAVE_RGB_COLOR("gray29", 74, 74, 74),
+WAVE_RGB_COLOR("gray3", 8, 8, 8),
+WAVE_RGB_COLOR("gray30", 77, 77, 77),
+WAVE_RGB_COLOR("gray31", 79, 79, 79),
+WAVE_RGB_COLOR("gray32", 82, 82, 82),
+WAVE_RGB_COLOR("gray33", 84, 84, 84),
+WAVE_RGB_COLOR("gray34", 87, 87, 87),
+WAVE_RGB_COLOR("gray35", 89, 89, 89),
+WAVE_RGB_COLOR("gray36", 92, 92, 92),
+WAVE_RGB_COLOR("gray37", 94, 94, 94),
+WAVE_RGB_COLOR("gray38", 97, 97, 97),
+WAVE_RGB_COLOR("gray39", 99, 99, 99),
+WAVE_RGB_COLOR("gray4", 10, 10, 10),
+WAVE_RGB_COLOR("gray40", 102, 102, 102),
+WAVE_RGB_COLOR("gray41", 105, 105, 105),
+WAVE_RGB_COLOR("gray42", 107, 107, 107),
+WAVE_RGB_COLOR("gray43", 110, 110, 110),
+WAVE_RGB_COLOR("gray44", 112, 112, 112),
+WAVE_RGB_COLOR("gray45", 115, 115, 115),
+WAVE_RGB_COLOR("gray46", 117, 117, 117),
+WAVE_RGB_COLOR("gray47", 120, 120, 120),
+WAVE_RGB_COLOR("gray48", 122, 122, 122),
+WAVE_RGB_COLOR("gray49", 125, 125, 125),
+WAVE_RGB_COLOR("gray5", 13, 13, 13),
+WAVE_RGB_COLOR("gray50", 127, 127, 127),
+WAVE_RGB_COLOR("gray51", 130, 130, 130),
+WAVE_RGB_COLOR("gray52", 133, 133, 133),
+WAVE_RGB_COLOR("gray53", 135, 135, 135),
+WAVE_RGB_COLOR("gray54", 138, 138, 138),
+WAVE_RGB_COLOR("gray55", 140, 140, 140),
+WAVE_RGB_COLOR("gray56", 143, 143, 143),
+WAVE_RGB_COLOR("gray57", 145, 145, 145),
+WAVE_RGB_COLOR("gray58", 148, 148, 148),
+WAVE_RGB_COLOR("gray59", 150, 150, 150),
+WAVE_RGB_COLOR("gray6", 15, 15, 15),
+WAVE_RGB_COLOR("gray60", 153, 153, 153),
+WAVE_RGB_COLOR("gray61", 156, 156, 156),
+WAVE_RGB_COLOR("gray62", 158, 158, 158),
+WAVE_RGB_COLOR("gray63", 161, 161, 161),
+WAVE_RGB_COLOR("gray64", 163, 163, 163),
+WAVE_RGB_COLOR("gray65", 166, 166, 166),
+WAVE_RGB_COLOR("gray66", 168, 168, 168),
+WAVE_RGB_COLOR("gray67", 171, 171, 171),
+WAVE_RGB_COLOR("gray68", 173, 173, 173),
+WAVE_RGB_COLOR("gray69", 176, 176, 176),
+WAVE_RGB_COLOR("gray7", 18, 18, 18),
+WAVE_RGB_COLOR("gray70", 179, 179, 179),
+WAVE_RGB_COLOR("gray71", 181, 181, 181),
+WAVE_RGB_COLOR("gray72", 184, 184, 184),
+WAVE_RGB_COLOR("gray73", 186, 186, 186),
+WAVE_RGB_COLOR("gray74", 189, 189, 189),
+WAVE_RGB_COLOR("gray75", 191, 191, 191),
+WAVE_RGB_COLOR("gray76", 194, 194, 194),
+WAVE_RGB_COLOR("gray77", 196, 196, 196),
+WAVE_RGB_COLOR("gray78", 199, 199, 199),
+WAVE_RGB_COLOR("gray79", 201, 201, 201),
+WAVE_RGB_COLOR("gray8", 20, 20, 20),
+WAVE_RGB_COLOR("gray80", 204, 204, 204),
+WAVE_RGB_COLOR("gray81", 207, 207, 207),
+WAVE_RGB_COLOR("gray82", 209, 209, 209),
+WAVE_RGB_COLOR("gray83", 212, 212, 212),
+WAVE_RGB_COLOR("gray84", 214, 214, 214),
+WAVE_RGB_COLOR("gray85", 217, 217, 217),
+WAVE_RGB_COLOR("gray86", 219, 219, 219),
+WAVE_RGB_COLOR("gray87", 222, 222, 222),
+WAVE_RGB_COLOR("gray88", 224, 224, 224),
+WAVE_RGB_COLOR("gray89", 227, 227, 227),
+WAVE_RGB_COLOR("gray9", 23, 23, 23),
+WAVE_RGB_COLOR("gray90", 229, 229, 229),
+WAVE_RGB_COLOR("gray91", 232, 232, 232),
+WAVE_RGB_COLOR("gray92", 235, 235, 235),
+WAVE_RGB_COLOR("gray93", 237, 237, 237),
+WAVE_RGB_COLOR("gray94", 240, 240, 240),
+WAVE_RGB_COLOR("gray95", 242, 242, 242),
+WAVE_RGB_COLOR("gray96", 245, 245, 245),
+WAVE_RGB_COLOR("gray97", 247, 247, 247),
+WAVE_RGB_COLOR("gray98", 250, 250, 250),
+WAVE_RGB_COLOR("gray99", 252, 252, 252),
+WAVE_RGB_COLOR("green", 0, 255, 0),
+WAVE_RGB_COLOR("green yellow", 173, 255, 47),
+WAVE_RGB_COLOR("green1", 0, 255, 0),
+WAVE_RGB_COLOR("green2", 0, 238, 0),
+WAVE_RGB_COLOR("green3", 0, 205, 0),
+WAVE_RGB_COLOR("green4", 0, 139, 0),
+WAVE_RGB_COLOR("GreenYellow", 173, 255, 47),
+WAVE_RGB_COLOR("grey", 190, 190, 190),
+WAVE_RGB_COLOR("grey0", 0, 0, 0),
+WAVE_RGB_COLOR("grey1", 3, 3, 3),
+WAVE_RGB_COLOR("grey10", 26, 26, 26),
+WAVE_RGB_COLOR("grey100", 255, 255, 255),
+WAVE_RGB_COLOR("grey11", 28, 28, 28),
+WAVE_RGB_COLOR("grey12", 31, 31, 31),
+WAVE_RGB_COLOR("grey13", 33, 33, 33),
+WAVE_RGB_COLOR("grey14", 36, 36, 36),
+WAVE_RGB_COLOR("grey15", 38, 38, 38),
+WAVE_RGB_COLOR("grey16", 41, 41, 41),
+WAVE_RGB_COLOR("grey17", 43, 43, 43),
+WAVE_RGB_COLOR("grey18", 46, 46, 46),
+WAVE_RGB_COLOR("grey19", 48, 48, 48),
+WAVE_RGB_COLOR("grey2", 5, 5, 5),
+WAVE_RGB_COLOR("grey20", 51, 51, 51),
+WAVE_RGB_COLOR("grey21", 54, 54, 54),
+WAVE_RGB_COLOR("grey22", 56, 56, 56),
+WAVE_RGB_COLOR("grey23", 59, 59, 59),
+WAVE_RGB_COLOR("grey24", 61, 61, 61),
+WAVE_RGB_COLOR("grey25", 64, 64, 64),
+WAVE_RGB_COLOR("grey26", 66, 66, 66),
+WAVE_RGB_COLOR("grey27", 69, 69, 69),
+WAVE_RGB_COLOR("grey28", 71, 71, 71),
+WAVE_RGB_COLOR("grey29", 74, 74, 74),
+WAVE_RGB_COLOR("grey3", 8, 8, 8),
+WAVE_RGB_COLOR("grey30", 77, 77, 77),
+WAVE_RGB_COLOR("grey31", 79, 79, 79),
+WAVE_RGB_COLOR("grey32", 82, 82, 82),
+WAVE_RGB_COLOR("grey33", 84, 84, 84),
+WAVE_RGB_COLOR("grey34", 87, 87, 87),
+WAVE_RGB_COLOR("grey35", 89, 89, 89),
+WAVE_RGB_COLOR("grey36", 92, 92, 92),
+WAVE_RGB_COLOR("grey37", 94, 94, 94),
+WAVE_RGB_COLOR("grey38", 97, 97, 97),
+WAVE_RGB_COLOR("grey39", 99, 99, 99),
+WAVE_RGB_COLOR("grey4", 10, 10, 10),
+WAVE_RGB_COLOR("grey40", 102, 102, 102),
+WAVE_RGB_COLOR("grey41", 105, 105, 105),
+WAVE_RGB_COLOR("grey42", 107, 107, 107),
+WAVE_RGB_COLOR("grey43", 110, 110, 110),
+WAVE_RGB_COLOR("grey44", 112, 112, 112),
+WAVE_RGB_COLOR("grey45", 115, 115, 115),
+WAVE_RGB_COLOR("grey46", 117, 117, 117),
+WAVE_RGB_COLOR("grey47", 120, 120, 120),
+WAVE_RGB_COLOR("grey48", 122, 122, 122),
+WAVE_RGB_COLOR("grey49", 125, 125, 125),
+WAVE_RGB_COLOR("grey5", 13, 13, 13),
+WAVE_RGB_COLOR("grey50", 127, 127, 127),
+WAVE_RGB_COLOR("grey51", 130, 130, 130),
+WAVE_RGB_COLOR("grey52", 133, 133, 133),
+WAVE_RGB_COLOR("grey53", 135, 135, 135),
+WAVE_RGB_COLOR("grey54", 138, 138, 138),
+WAVE_RGB_COLOR("grey55", 140, 140, 140),
+WAVE_RGB_COLOR("grey56", 143, 143, 143),
+WAVE_RGB_COLOR("grey57", 145, 145, 145),
+WAVE_RGB_COLOR("grey58", 148, 148, 148),
+WAVE_RGB_COLOR("grey59", 150, 150, 150),
+WAVE_RGB_COLOR("grey6", 15, 15, 15),
+WAVE_RGB_COLOR("grey60", 153, 153, 153),
+WAVE_RGB_COLOR("grey61", 156, 156, 156),
+WAVE_RGB_COLOR("grey62", 158, 158, 158),
+WAVE_RGB_COLOR("grey63", 161, 161, 161),
+WAVE_RGB_COLOR("grey64", 163, 163, 163),
+WAVE_RGB_COLOR("grey65", 166, 166, 166),
+WAVE_RGB_COLOR("grey66", 168, 168, 168),
+WAVE_RGB_COLOR("grey67", 171, 171, 171),
+WAVE_RGB_COLOR("grey68", 173, 173, 173),
+WAVE_RGB_COLOR("grey69", 176, 176, 176),
+WAVE_RGB_COLOR("grey7", 18, 18, 18),
+WAVE_RGB_COLOR("grey70", 179, 179, 179),
+WAVE_RGB_COLOR("grey71", 181, 181, 181),
+WAVE_RGB_COLOR("grey72", 184, 184, 184),
+WAVE_RGB_COLOR("grey73", 186, 186, 186),
+WAVE_RGB_COLOR("grey74", 189, 189, 189),
+WAVE_RGB_COLOR("grey75", 191, 191, 191),
+WAVE_RGB_COLOR("grey76", 194, 194, 194),
+WAVE_RGB_COLOR("grey77", 196, 196, 196),
+WAVE_RGB_COLOR("grey78", 199, 199, 199),
+WAVE_RGB_COLOR("grey79", 201, 201, 201),
+WAVE_RGB_COLOR("grey8", 20, 20, 20),
+WAVE_RGB_COLOR("grey80", 204, 204, 204),
+WAVE_RGB_COLOR("grey81", 207, 207, 207),
+WAVE_RGB_COLOR("grey82", 209, 209, 209),
+WAVE_RGB_COLOR("grey83", 212, 212, 212),
+WAVE_RGB_COLOR("grey84", 214, 214, 214),
+WAVE_RGB_COLOR("grey85", 217, 217, 217),
+WAVE_RGB_COLOR("grey86", 219, 219, 219),
+WAVE_RGB_COLOR("grey87", 222, 222, 222),
+WAVE_RGB_COLOR("grey88", 224, 224, 224),
+WAVE_RGB_COLOR("grey89", 227, 227, 227),
+WAVE_RGB_COLOR("grey9", 23, 23, 23),
+WAVE_RGB_COLOR("grey90", 229, 229, 229),
+WAVE_RGB_COLOR("grey91", 232, 232, 232),
+WAVE_RGB_COLOR("grey92", 235, 235, 235),
+WAVE_RGB_COLOR("grey93", 237, 237, 237),
+WAVE_RGB_COLOR("grey94", 240, 240, 240),
+WAVE_RGB_COLOR("grey95", 242, 242, 242),
+WAVE_RGB_COLOR("grey96", 245, 245, 245),
+WAVE_RGB_COLOR("grey97", 247, 247, 247),
+WAVE_RGB_COLOR("grey98", 250, 250, 250),
+WAVE_RGB_COLOR("grey99", 252, 252, 252),
+WAVE_RGB_COLOR("honeydew", 240, 255, 240),
+WAVE_RGB_COLOR("honeydew1", 240, 255, 240),
+WAVE_RGB_COLOR("honeydew2", 224, 238, 224),
+WAVE_RGB_COLOR("honeydew3", 193, 205, 193),
+WAVE_RGB_COLOR("honeydew4", 131, 139, 131),
+WAVE_RGB_COLOR("hot pink", 255, 105, 180),
+WAVE_RGB_COLOR("HotPink", 255, 105, 180),
+WAVE_RGB_COLOR("HotPink1", 255, 110, 180),
+WAVE_RGB_COLOR("HotPink2", 238, 106, 167),
+WAVE_RGB_COLOR("HotPink3", 205, 96, 144),
+WAVE_RGB_COLOR("HotPink4", 139, 58, 98),
+WAVE_RGB_COLOR("indian red", 205, 92, 92),
+WAVE_RGB_COLOR("IndianRed", 205, 92, 92),
+WAVE_RGB_COLOR("IndianRed1", 255, 106, 106),
+WAVE_RGB_COLOR("IndianRed2", 238, 99, 99),
+WAVE_RGB_COLOR("IndianRed3", 205, 85, 85),
+WAVE_RGB_COLOR("IndianRed4", 139, 58, 58),
+WAVE_RGB_COLOR("ivory", 255, 255, 240),
+WAVE_RGB_COLOR("ivory1", 255, 255, 240),
+WAVE_RGB_COLOR("ivory2", 238, 238, 224),
+WAVE_RGB_COLOR("ivory3", 205, 205, 193),
+WAVE_RGB_COLOR("ivory4", 139, 139, 131),
+WAVE_RGB_COLOR("khaki", 240, 230, 140),
+WAVE_RGB_COLOR("khaki1", 255, 246, 143),
+WAVE_RGB_COLOR("khaki2", 238, 230, 133),
+WAVE_RGB_COLOR("khaki3", 205, 198, 115),
+WAVE_RGB_COLOR("khaki4", 139, 134, 78),
+WAVE_RGB_COLOR("lavender", 230, 230, 250),
+WAVE_RGB_COLOR("lavender blush", 255, 240, 245),
+WAVE_RGB_COLOR("LavenderBlush", 255, 240, 245),
+WAVE_RGB_COLOR("LavenderBlush1", 255, 240, 245),
+WAVE_RGB_COLOR("LavenderBlush2", 238, 224, 229),
+WAVE_RGB_COLOR("LavenderBlush3", 205, 193, 197),
+WAVE_RGB_COLOR("LavenderBlush4", 139, 131, 134),
+WAVE_RGB_COLOR("lawn green", 124, 252, 0),
+WAVE_RGB_COLOR("LawnGreen", 124, 252, 0),
+WAVE_RGB_COLOR("lemon chiffon", 255, 250, 205),
+WAVE_RGB_COLOR("LemonChiffon", 255, 250, 205),
+WAVE_RGB_COLOR("LemonChiffon1", 255, 250, 205),
+WAVE_RGB_COLOR("LemonChiffon2", 238, 233, 191),
+WAVE_RGB_COLOR("LemonChiffon3", 205, 201, 165),
+WAVE_RGB_COLOR("LemonChiffon4", 139, 137, 112),
+WAVE_RGB_COLOR("light blue", 173, 216, 230),
+WAVE_RGB_COLOR("light coral", 240, 128, 128),
+WAVE_RGB_COLOR("light cyan", 224, 255, 255),
+WAVE_RGB_COLOR("light goldenrod", 238, 221, 130),
+WAVE_RGB_COLOR("light goldenrod yellow", 250, 250, 210),
+WAVE_RGB_COLOR("light gray", 211, 211, 211),
+WAVE_RGB_COLOR("light green", 144, 238, 144),
+WAVE_RGB_COLOR("light grey", 211, 211, 211),
+WAVE_RGB_COLOR("light pink", 255, 182, 193),
+WAVE_RGB_COLOR("light salmon", 255, 160, 122),
+WAVE_RGB_COLOR("light sea green", 32, 178, 170),
+WAVE_RGB_COLOR("light sky blue", 135, 206, 250),
+WAVE_RGB_COLOR("light slate blue", 132, 112, 255),
+WAVE_RGB_COLOR("light slate gray", 119, 136, 153),
+WAVE_RGB_COLOR("light slate grey", 119, 136, 153),
+WAVE_RGB_COLOR("light steel blue", 176, 196, 222),
+WAVE_RGB_COLOR("light yellow", 255, 255, 224),
+WAVE_RGB_COLOR("LightBlue", 173, 216, 230),
+WAVE_RGB_COLOR("LightBlue1", 191, 239, 255),
+WAVE_RGB_COLOR("LightBlue2", 178, 223, 238),
+WAVE_RGB_COLOR("LightBlue3", 154, 192, 205),
+WAVE_RGB_COLOR("LightBlue4", 104, 131, 139),
+WAVE_RGB_COLOR("LightCoral", 240, 128, 128),
+WAVE_RGB_COLOR("LightCyan", 224, 255, 255),
+WAVE_RGB_COLOR("LightCyan1", 224, 255, 255),
+WAVE_RGB_COLOR("LightCyan2", 209, 238, 238),
+WAVE_RGB_COLOR("LightCyan3", 180, 205, 205),
+WAVE_RGB_COLOR("LightCyan4", 122, 139, 139),
+WAVE_RGB_COLOR("LightGoldenrod", 238, 221, 130),
+WAVE_RGB_COLOR("LightGoldenrod1", 255, 236, 139),
+WAVE_RGB_COLOR("LightGoldenrod2", 238, 220, 130),
+WAVE_RGB_COLOR("LightGoldenrod3", 205, 190, 112),
+WAVE_RGB_COLOR("LightGoldenrod4", 139, 129, 76),
+WAVE_RGB_COLOR("LightGoldenrodYellow", 250, 250, 210),
+WAVE_RGB_COLOR("LightGray", 211, 211, 211),
+WAVE_RGB_COLOR("LightGreen", 144, 238, 144),
+WAVE_RGB_COLOR("LightGrey", 211, 211, 211),
+WAVE_RGB_COLOR("LightPink", 255, 182, 193),
+WAVE_RGB_COLOR("LightPink1", 255, 174, 185),
+WAVE_RGB_COLOR("LightPink2", 238, 162, 173),
+WAVE_RGB_COLOR("LightPink3", 205, 140, 149),
+WAVE_RGB_COLOR("LightPink4", 139, 95, 101),
+WAVE_RGB_COLOR("LightSalmon", 255, 160, 122),
+WAVE_RGB_COLOR("LightSalmon1", 255, 160, 122),
+WAVE_RGB_COLOR("LightSalmon2", 238, 149, 114),
+WAVE_RGB_COLOR("LightSalmon3", 205, 129, 98),
+WAVE_RGB_COLOR("LightSalmon4", 139, 87, 66),
+WAVE_RGB_COLOR("LightSeaGreen", 32, 178, 170),
+WAVE_RGB_COLOR("LightSkyBlue", 135, 206, 250),
+WAVE_RGB_COLOR("LightSkyBlue1", 176, 226, 255),
+WAVE_RGB_COLOR("LightSkyBlue2", 164, 211, 238),
+WAVE_RGB_COLOR("LightSkyBlue3", 141, 182, 205),
+WAVE_RGB_COLOR("LightSkyBlue4", 96, 123, 139),
+WAVE_RGB_COLOR("LightSlateBlue", 132, 112, 255),
+WAVE_RGB_COLOR("LightSlateGray", 119, 136, 153),
+WAVE_RGB_COLOR("LightSlateGrey", 119, 136, 153),
+WAVE_RGB_COLOR("LightSteelBlue", 176, 196, 222),
+WAVE_RGB_COLOR("LightSteelBlue1", 202, 225, 255),
+WAVE_RGB_COLOR("LightSteelBlue2", 188, 210, 238),
+WAVE_RGB_COLOR("LightSteelBlue3", 162, 181, 205),
+WAVE_RGB_COLOR("LightSteelBlue4", 110, 123, 139),
+WAVE_RGB_COLOR("LightYellow", 255, 255, 224),
+WAVE_RGB_COLOR("LightYellow1", 255, 255, 224),
+WAVE_RGB_COLOR("LightYellow2", 238, 238, 209),
+WAVE_RGB_COLOR("LightYellow3", 205, 205, 180),
+WAVE_RGB_COLOR("LightYellow4", 139, 139, 122),
+WAVE_RGB_COLOR("lime green", 50, 205, 50),
+WAVE_RGB_COLOR("LimeGreen", 50, 205, 50),
+WAVE_RGB_COLOR("linen", 250, 240, 230),
+WAVE_RGB_COLOR("magenta", 255, 0, 255),
+WAVE_RGB_COLOR("magenta1", 255, 0, 255),
+WAVE_RGB_COLOR("magenta2", 238, 0, 238),
+WAVE_RGB_COLOR("magenta3", 205, 0, 205),
+WAVE_RGB_COLOR("magenta4", 139, 0, 139),
+WAVE_RGB_COLOR("maroon", 176, 48, 96),
+WAVE_RGB_COLOR("maroon1", 255, 52, 179),
+WAVE_RGB_COLOR("maroon2", 238, 48, 167),
+WAVE_RGB_COLOR("maroon3", 205, 41, 144),
+WAVE_RGB_COLOR("maroon4", 139, 28, 98),
+WAVE_RGB_COLOR("medium aquamarine", 102, 205, 170),
+WAVE_RGB_COLOR("medium blue", 0, 0, 205),
+WAVE_RGB_COLOR("medium orchid", 186, 85, 211),
+WAVE_RGB_COLOR("medium purple", 147, 112, 219),
+WAVE_RGB_COLOR("medium sea green", 60, 179, 113),
+WAVE_RGB_COLOR("medium slate blue", 123, 104, 238),
+WAVE_RGB_COLOR("medium spring green", 0, 250, 154),
+WAVE_RGB_COLOR("medium turquoise", 72, 209, 204),
+WAVE_RGB_COLOR("medium violet red", 199, 21, 133),
+WAVE_RGB_COLOR("MediumAquamarine", 102, 205, 170),
+WAVE_RGB_COLOR("MediumBlue", 0, 0, 205),
+WAVE_RGB_COLOR("MediumOrchid", 186, 85, 211),
+WAVE_RGB_COLOR("MediumOrchid1", 224, 102, 255),
+WAVE_RGB_COLOR("MediumOrchid2", 209, 95, 238),
+WAVE_RGB_COLOR("MediumOrchid3", 180, 82, 205),
+WAVE_RGB_COLOR("MediumOrchid4", 122, 55, 139),
+WAVE_RGB_COLOR("MediumPurple", 147, 112, 219),
+WAVE_RGB_COLOR("MediumPurple1", 171, 130, 255),
+WAVE_RGB_COLOR("MediumPurple2", 159, 121, 238),
+WAVE_RGB_COLOR("MediumPurple3", 137, 104, 205),
+WAVE_RGB_COLOR("MediumPurple4", 93, 71, 139),
+WAVE_RGB_COLOR("MediumSeaGreen", 60, 179, 113),
+WAVE_RGB_COLOR("MediumSlateBlue", 123, 104, 238),
+WAVE_RGB_COLOR("MediumSpringGreen", 0, 250, 154),
+WAVE_RGB_COLOR("MediumTurquoise", 72, 209, 204),
+WAVE_RGB_COLOR("MediumVioletRed", 199, 21, 133),
+WAVE_RGB_COLOR("midnight blue", 25, 25, 112),
+WAVE_RGB_COLOR("MidnightBlue", 25, 25, 112),
+WAVE_RGB_COLOR("mint cream", 245, 255, 250),
+WAVE_RGB_COLOR("MintCream", 245, 255, 250),
+WAVE_RGB_COLOR("misty rose", 255, 228, 225),
+WAVE_RGB_COLOR("MistyRose", 255, 228, 225),
+WAVE_RGB_COLOR("MistyRose1", 255, 228, 225),
+WAVE_RGB_COLOR("MistyRose2", 238, 213, 210),
+WAVE_RGB_COLOR("MistyRose3", 205, 183, 181),
+WAVE_RGB_COLOR("MistyRose4", 139, 125, 123),
+WAVE_RGB_COLOR("moccasin", 255, 228, 181),
+WAVE_RGB_COLOR("navajo white", 255, 222, 173),
+WAVE_RGB_COLOR("NavajoWhite", 255, 222, 173),
+WAVE_RGB_COLOR("NavajoWhite1", 255, 222, 173),
+WAVE_RGB_COLOR("NavajoWhite2", 238, 207, 161),
+WAVE_RGB_COLOR("NavajoWhite3", 205, 179, 139),
+WAVE_RGB_COLOR("NavajoWhite4", 139, 121, 94),
+WAVE_RGB_COLOR("navy", 0, 0, 128),
+WAVE_RGB_COLOR("navy blue", 0, 0, 128),
+WAVE_RGB_COLOR("NavyBlue", 0, 0, 128),
+WAVE_RGB_COLOR("old lace", 253, 245, 230),
+WAVE_RGB_COLOR("OldLace", 253, 245, 230),
+WAVE_RGB_COLOR("olive drab", 107, 142, 35),
+WAVE_RGB_COLOR("OliveDrab", 107, 142, 35),
+WAVE_RGB_COLOR("OliveDrab1", 192, 255, 62),
+WAVE_RGB_COLOR("OliveDrab2", 179, 238, 58),
+WAVE_RGB_COLOR("OliveDrab3", 154, 205, 50),
+WAVE_RGB_COLOR("OliveDrab4", 105, 139, 34),
+WAVE_RGB_COLOR("orange", 255, 165, 0),
+WAVE_RGB_COLOR("orange red", 255, 69, 0),
+WAVE_RGB_COLOR("orange1", 255, 165, 0),
+WAVE_RGB_COLOR("orange2", 238, 154, 0),
+WAVE_RGB_COLOR("orange3", 205, 133, 0),
+WAVE_RGB_COLOR("orange4", 139, 90, 0),
+WAVE_RGB_COLOR("OrangeRed", 255, 69, 0),
+WAVE_RGB_COLOR("OrangeRed1", 255, 69, 0),
+WAVE_RGB_COLOR("OrangeRed2", 238, 64, 0),
+WAVE_RGB_COLOR("OrangeRed3", 205, 55, 0),
+WAVE_RGB_COLOR("OrangeRed4", 139, 37, 0),
+WAVE_RGB_COLOR("orchid", 218, 112, 214),
+WAVE_RGB_COLOR("orchid1", 255, 131, 250),
+WAVE_RGB_COLOR("orchid2", 238, 122, 233),
+WAVE_RGB_COLOR("orchid3", 205, 105, 201),
+WAVE_RGB_COLOR("orchid4", 139, 71, 137),
+WAVE_RGB_COLOR("pale goldenrod", 238, 232, 170),
+WAVE_RGB_COLOR("pale green", 152, 251, 152),
+WAVE_RGB_COLOR("pale turquoise", 175, 238, 238),
+WAVE_RGB_COLOR("pale violet red", 219, 112, 147),
+WAVE_RGB_COLOR("PaleGoldenrod", 238, 232, 170),
+WAVE_RGB_COLOR("PaleGreen", 152, 251, 152),
+WAVE_RGB_COLOR("PaleGreen1", 154, 255, 154),
+WAVE_RGB_COLOR("PaleGreen2", 144, 238, 144),
+WAVE_RGB_COLOR("PaleGreen3", 124, 205, 124),
+WAVE_RGB_COLOR("PaleGreen4", 84, 139, 84),
+WAVE_RGB_COLOR("PaleTurquoise", 175, 238, 238),
+WAVE_RGB_COLOR("PaleTurquoise1", 187, 255, 255),
+WAVE_RGB_COLOR("PaleTurquoise2", 174, 238, 238),
+WAVE_RGB_COLOR("PaleTurquoise3", 150, 205, 205),
+WAVE_RGB_COLOR("PaleTurquoise4", 102, 139, 139),
+WAVE_RGB_COLOR("PaleVioletRed", 219, 112, 147),
+WAVE_RGB_COLOR("PaleVioletRed1", 255, 130, 171),
+WAVE_RGB_COLOR("PaleVioletRed2", 238, 121, 159),
+WAVE_RGB_COLOR("PaleVioletRed3", 205, 104, 137),
+WAVE_RGB_COLOR("PaleVioletRed4", 139, 71, 93),
+WAVE_RGB_COLOR("papaya whip", 255, 239, 213),
+WAVE_RGB_COLOR("PapayaWhip", 255, 239, 213),
+WAVE_RGB_COLOR("peach puff", 255, 218, 185),
+WAVE_RGB_COLOR("PeachPuff", 255, 218, 185),
+WAVE_RGB_COLOR("PeachPuff1", 255, 218, 185),
+WAVE_RGB_COLOR("PeachPuff2", 238, 203, 173),
+WAVE_RGB_COLOR("PeachPuff3", 205, 175, 149),
+WAVE_RGB_COLOR("PeachPuff4", 139, 119, 101),
+WAVE_RGB_COLOR("peru", 205, 133, 63),
+WAVE_RGB_COLOR("pink", 255, 192, 203),
+WAVE_RGB_COLOR("pink1", 255, 181, 197),
+WAVE_RGB_COLOR("pink2", 238, 169, 184),
+WAVE_RGB_COLOR("pink3", 205, 145, 158),
+WAVE_RGB_COLOR("pink4", 139, 99, 108),
+WAVE_RGB_COLOR("plum", 221, 160, 221),
+WAVE_RGB_COLOR("plum1", 255, 187, 255),
+WAVE_RGB_COLOR("plum2", 238, 174, 238),
+WAVE_RGB_COLOR("plum3", 205, 150, 205),
+WAVE_RGB_COLOR("plum4", 139, 102, 139),
+WAVE_RGB_COLOR("powder blue", 176, 224, 230),
+WAVE_RGB_COLOR("PowderBlue", 176, 224, 230),
+WAVE_RGB_COLOR("purple", 160, 32, 240),
+WAVE_RGB_COLOR("purple1", 155, 48, 255),
+WAVE_RGB_COLOR("purple2", 145, 44, 238),
+WAVE_RGB_COLOR("purple3", 125, 38, 205),
+WAVE_RGB_COLOR("purple4", 85, 26, 139),
+WAVE_RGB_COLOR("red", 255, 0, 0),
+WAVE_RGB_COLOR("red1", 255, 0, 0),
+WAVE_RGB_COLOR("red2", 238, 0, 0),
+WAVE_RGB_COLOR("red3", 205, 0, 0),
+WAVE_RGB_COLOR("red4", 139, 0, 0),
+WAVE_RGB_COLOR("rosy brown", 188, 143, 143),
+WAVE_RGB_COLOR("RosyBrown", 188, 143, 143),
+WAVE_RGB_COLOR("RosyBrown1", 255, 193, 193),
+WAVE_RGB_COLOR("RosyBrown2", 238, 180, 180),
+WAVE_RGB_COLOR("RosyBrown3", 205, 155, 155),
+WAVE_RGB_COLOR("RosyBrown4", 139, 105, 105),
+WAVE_RGB_COLOR("royal blue", 65, 105, 225),
+WAVE_RGB_COLOR("RoyalBlue", 65, 105, 225),
+WAVE_RGB_COLOR("RoyalBlue1", 72, 118, 255),
+WAVE_RGB_COLOR("RoyalBlue2", 67, 110, 238),
+WAVE_RGB_COLOR("RoyalBlue3", 58, 95, 205),
+WAVE_RGB_COLOR("RoyalBlue4", 39, 64, 139),
+WAVE_RGB_COLOR("saddle brown", 139, 69, 19),
+WAVE_RGB_COLOR("SaddleBrown", 139, 69, 19),
+WAVE_RGB_COLOR("salmon", 250, 128, 114),
+WAVE_RGB_COLOR("salmon1", 255, 140, 105),
+WAVE_RGB_COLOR("salmon2", 238, 130, 98),
+WAVE_RGB_COLOR("salmon3", 205, 112, 84),
+WAVE_RGB_COLOR("salmon4", 139, 76, 57),
+WAVE_RGB_COLOR("sandy brown", 244, 164, 96),
+WAVE_RGB_COLOR("SandyBrown", 244, 164, 96),
+WAVE_RGB_COLOR("sea green", 46, 139, 87),
+WAVE_RGB_COLOR("SeaGreen", 46, 139, 87),
+WAVE_RGB_COLOR("SeaGreen1", 84, 255, 159),
+WAVE_RGB_COLOR("SeaGreen2", 78, 238, 148),
+WAVE_RGB_COLOR("SeaGreen3", 67, 205, 128),
+WAVE_RGB_COLOR("SeaGreen4", 46, 139, 87),
+WAVE_RGB_COLOR("seashell", 255, 245, 238),
+WAVE_RGB_COLOR("seashell1", 255, 245, 238),
+WAVE_RGB_COLOR("seashell2", 238, 229, 222),
+WAVE_RGB_COLOR("seashell3", 205, 197, 191),
+WAVE_RGB_COLOR("seashell4", 139, 134, 130),
+WAVE_RGB_COLOR("sienna", 160, 82, 45),
+WAVE_RGB_COLOR("sienna1", 255, 130, 71),
+WAVE_RGB_COLOR("sienna2", 238, 121, 66),
+WAVE_RGB_COLOR("sienna3", 205, 104, 57),
+WAVE_RGB_COLOR("sienna4", 139, 71, 38),
+WAVE_RGB_COLOR("sky blue", 135, 206, 235),
+WAVE_RGB_COLOR("SkyBlue", 135, 206, 235),
+WAVE_RGB_COLOR("SkyBlue1", 135, 206, 255),
+WAVE_RGB_COLOR("SkyBlue2", 126, 192, 238),
+WAVE_RGB_COLOR("SkyBlue3", 108, 166, 205),
+WAVE_RGB_COLOR("SkyBlue4", 74, 112, 139),
+WAVE_RGB_COLOR("slate blue", 106, 90, 205),
+WAVE_RGB_COLOR("slate gray", 112, 128, 144),
+WAVE_RGB_COLOR("slate grey", 112, 128, 144),
+WAVE_RGB_COLOR("SlateBlue", 106, 90, 205),
+WAVE_RGB_COLOR("SlateBlue1", 131, 111, 255),
+WAVE_RGB_COLOR("SlateBlue2", 122, 103, 238),
+WAVE_RGB_COLOR("SlateBlue3", 105, 89, 205),
+WAVE_RGB_COLOR("SlateBlue4", 71, 60, 139),
+WAVE_RGB_COLOR("SlateGray", 112, 128, 144),
+WAVE_RGB_COLOR("SlateGray1", 198, 226, 255),
+WAVE_RGB_COLOR("SlateGray2", 185, 211, 238),
+WAVE_RGB_COLOR("SlateGray3", 159, 182, 205),
+WAVE_RGB_COLOR("SlateGray4", 108, 123, 139),
+WAVE_RGB_COLOR("SlateGrey", 112, 128, 144),
+WAVE_RGB_COLOR("snow", 255, 250, 250),
+WAVE_RGB_COLOR("snow1", 255, 250, 250),
+WAVE_RGB_COLOR("snow2", 238, 233, 233),
+WAVE_RGB_COLOR("snow3", 205, 201, 201),
+WAVE_RGB_COLOR("snow4", 139, 137, 137),
+WAVE_RGB_COLOR("spring green", 0, 255, 127),
+WAVE_RGB_COLOR("SpringGreen", 0, 255, 127),
+WAVE_RGB_COLOR("SpringGreen1", 0, 255, 127),
+WAVE_RGB_COLOR("SpringGreen2", 0, 238, 118),
+WAVE_RGB_COLOR("SpringGreen3", 0, 205, 102),
+WAVE_RGB_COLOR("SpringGreen4", 0, 139, 69),
+WAVE_RGB_COLOR("steel blue", 70, 130, 180),
+WAVE_RGB_COLOR("SteelBlue", 70, 130, 180),
+WAVE_RGB_COLOR("SteelBlue1", 99, 184, 255),
+WAVE_RGB_COLOR("SteelBlue2", 92, 172, 238),
+WAVE_RGB_COLOR("SteelBlue3", 79, 148, 205),
+WAVE_RGB_COLOR("SteelBlue4", 54, 100, 139),
+WAVE_RGB_COLOR("tan", 210, 180, 140),
+WAVE_RGB_COLOR("tan1", 255, 165, 79),
+WAVE_RGB_COLOR("tan2", 238, 154, 73),
+WAVE_RGB_COLOR("tan3", 205, 133, 63),
+WAVE_RGB_COLOR("tan4", 139, 90, 43),
+WAVE_RGB_COLOR("thistle", 216, 191, 216),
+WAVE_RGB_COLOR("thistle1", 255, 225, 255),
+WAVE_RGB_COLOR("thistle2", 238, 210, 238),
+WAVE_RGB_COLOR("thistle3", 205, 181, 205),
+WAVE_RGB_COLOR("thistle4", 139, 123, 139),
+WAVE_RGB_COLOR("tomato", 255, 99, 71),
+WAVE_RGB_COLOR("tomato1", 255, 99, 71),
+WAVE_RGB_COLOR("tomato2", 238, 92, 66),
+WAVE_RGB_COLOR("tomato3", 205, 79, 57),
+WAVE_RGB_COLOR("tomato4", 139, 54, 38),
+WAVE_RGB_COLOR("turquoise", 64, 224, 208),
+WAVE_RGB_COLOR("turquoise1", 0, 245, 255),
+WAVE_RGB_COLOR("turquoise2", 0, 229, 238),
+WAVE_RGB_COLOR("turquoise3", 0, 197, 205),
+WAVE_RGB_COLOR("turquoise4", 0, 134, 139),
+WAVE_RGB_COLOR("violet", 238, 130, 238),
+WAVE_RGB_COLOR("violet red", 208, 32, 144),
+WAVE_RGB_COLOR("VioletRed", 208, 32, 144),
+WAVE_RGB_COLOR("VioletRed1", 255, 62, 150),
+WAVE_RGB_COLOR("VioletRed2", 238, 58, 140),
+WAVE_RGB_COLOR("VioletRed3", 205, 50, 120),
+WAVE_RGB_COLOR("VioletRed4", 139, 34, 82),
+WAVE_RGB_COLOR("wheat", 245, 222, 179),
+WAVE_RGB_COLOR("wheat1", 255, 231, 186),
+WAVE_RGB_COLOR("wheat2", 238, 216, 174),
+WAVE_RGB_COLOR("wheat3", 205, 186, 150),
+WAVE_RGB_COLOR("wheat4", 139, 126, 102),
+WAVE_RGB_COLOR("white", 255, 255, 255),
+WAVE_RGB_COLOR("white smoke", 245, 245, 245),
+WAVE_RGB_COLOR("WhiteSmoke", 245, 245, 245),
+WAVE_RGB_COLOR("yellow", 255, 255, 0),
+WAVE_RGB_COLOR("yellow green", 154, 205, 50),
+WAVE_RGB_COLOR("yellow1", 255, 255, 0),
+WAVE_RGB_COLOR("yellow2", 238, 238, 0),
+WAVE_RGB_COLOR("yellow3", 205, 205, 0),
+WAVE_RGB_COLOR("yellow4", 139, 139, 0),
+WAVE_RGB_COLOR("YellowGreen", 154, 205, 50),
+};
+'''

dev/sim/gtkwave/gtkf-gprr.py

@@ -0,0 +1,45 @@
+#!/usr/bin/python3
+# gtkwave process filter
+#
+# display gpr adr/dat (read, 1 cyc access)
+#
+# format=binary so justification and data length don't matter
+
+import sys
+
+color = ''
+
+fi = sys.stdin
+fo = sys.stdout
+fe = sys.stderr
+
+def dbg(m):
+   fe.write(m + '\n')
+   fe.flush()
+
+def main():
+
+   lastAdr = -1
+
+   while True:
+
+      line = fi.readline()
+      if not line:
+         return 0
+
+      try:
+         if lastAdr == -1:
+            fo.write(f'{color}XX:XXXXXXXXXXXXXXXX\n')
+         else:
+            fo.write(f'{color}{lastAdr:02X}:{int(line[6:70],2):016X}\n')
+         lastAdr = int(line[0:6],2)
+      except Exception as e:
+         fe.write('error!\n')
+         fe.write(str(e))
+         fe.flush()
+         fo.write('filter error!\n')
+
+      fo.flush()
+
+if __name__ == '__main__':
+   sys.exit(main())

dev/sim/gtkwave/gtkf-gprw.py

@@ -0,0 +1,43 @@
+#!/usr/bin/python3
+# gtkwave process filter
+#
+# display gpr we/adr/dat
+#
+# format=binary so justification and data length don't matter
+
+import sys
+
+#colorI = '?LightGray?'
+colorI = ''
+colorV = '?DarkBlue?'
+
+fi = sys.stdin
+fo = sys.stdout
+fe = sys.stderr
+
+def dbg(m):
+   fe.write(m + '\n')
+   fe.flush()
+
+def main():
+
+   while True:
+
+      line = fi.readline()
+      if not line:
+         return 0
+
+      try:
+         if line[0] == '0':
+            fo.write(f'{colorI}{int(line[1:7],2):02X}:{int(line[7:71],2):016X}\n')
+         else:
+            fo.write(f'{colorV}{int(line[1:7],2):02X}:{int(line[7:71],2):016X}\n')
+      except Exception as e:
+         fe.write('error!\n')
+         fe.write(str(e))
+         fo.write('filter error!\n')
+
+      fo.flush()
+
+if __name__ == '__main__':
+   sys.exit(main())

dev/sim/gtkwave/gtkf-ibuf.py

@@ -0,0 +1,37 @@
+#!/usr/bin/python3
+# gtkwave process filter
+#
+# split binary ibuf entry into op/bta/ifar
+
+import sys
+
+fi = sys.stdin
+fo = sys.stdout
+fe = sys.stderr
+
+def dbg(m):
+   fe.write(m + '\n')
+   fe.flush()
+
+# ppc 0:31, ppc+ 32:69, bta 70:89, ifar 90:109
+ibufInstrWidth = 70
+effIFARWidth = 20
+ibufIFARWidth = 20
+
+def main():
+
+   while True:
+
+      line = fi.readline()
+      if not line:
+         return 0
+
+      try:
+         fo.write(f'{int(line[0:32],2):08X} a={int(line[ibufInstrWidth+effIFARWidth:],2)<<2:08X} m={int(line[32:ibufInstrWidth],2):10X} t={int(line[ibufInstrWidth:ibufInstrWidth+effIFARWidth],2)<<2:08X}\n')
+      except:
+         fo.write('\n')
+
+      fo.flush()
+
+if __name__ == '__main__':
+   sys.exit(main())

dev/sim/gtkwave/gtkf-nop.py

@@ -0,0 +1,30 @@
+#!/usr/bin/python3
+# gtkwave process filter
+
+# does nothing
+
+import sys
+
+fi = sys.stdin
+fo = sys.stdout
+fe = sys.stderr
+
+debug = False
+
+def dbg(m):
+   if debug:
+      fe.write(m + '\n')
+      fe.flush()
+
+def main():
+
+   while True:
+
+      l = fi.readline()
+      if not l:
+         return 0
+      fo.write(f'{l}\n')
+      fo.flush()
+
+if __name__ == '__main__':
+	sys.exit(main())

dev/sim/gtkwave/gtkf-ppc.py

@@ -0,0 +1,880 @@
+#!/usr/bin/python3
+# gtkwave process filter
+
+# add:
+#   pseudo op xlate (rlwinm->shift, etc.)
+
+import sys
+import tempfile
+import subprocess
+
+fi = sys.stdin
+fo = sys.stdout
+fe = sys.stderr
+
+debug = False
+
+def dbg(m):
+   if debug:
+      fe.write(m + '\n')
+      fe.flush()
+
+colors = {
+   #'default':'DeepSkyBlue',
+   'default':'DarkGreen',
+   'data':'DarkGray',
+   'bctr':'DarkOrange',
+   'x':'red'
+}
+
+def dasm(op):
+   oo = tempfile.NamedTemporaryFile(delete=False, mode='w')
+   ai = tempfile.NamedTemporaryFile(delete=False, mode='w')
+   ai.write(f'.long 0x{op}\n')
+   ai.flush()
+   #subprocess.run(["powerpc-linux-gnu-as", "-mpower9", "-o", oo.name, ai.name])
+   subprocess.run(["powerpc-linux-gnu-as", "-ma2", "-o", oo.name, ai.name])
+   result = subprocess.run(["powerpc-linux-gnu-objdump", "-d", oo.name], capture_output=True)
+   lines = result.stdout.splitlines()
+   if len(lines) < 8:
+      return [f'0x{op}', '']
+   l = result.stdout.splitlines()[-1]
+   tokens = l.decode().split('\t')
+   op = tokens[2].split()
+   if op[0] == '.long':
+      op = [f'0x{int(op[1], 16):08X}', '']
+   else:
+      op = massage(op)
+   if len(op) > 1:
+      return [op[0], ' '.join(op[1:])]
+   else:
+      return [op[0], ' ']
+
+# beautify pseudo-ops [op operand1,operand2,...]
+def massage(op, hexify=False):
+   # li r,i             = li r,hex(i)
+   # slwi rx,ry,a       = rlwinm rx,ry,a,0,31-a
+   # mtspr n,r          = mtspr name,r
+   # mfspr r,n          = mfspr r,name
+
+   sprNames = {
+      '438': 'tens',
+      '446': 'tir',
+      '815': 'tar'
+   }
+
+   if len(op) < 2:
+      return op
+
+   ops = op[1].split(',')
+   if op[0] == 'li':
+      op = ['li', f'{ops[0]},0x{int(ops[1]):04X}']
+   elif op[0] == 'rlwinm':
+      if int(ops[3]) == 0 and int(ops[4]) == 31-int(ops[2]):
+         op = ['slwi', f'{ops[0]},{ops[1]},{ops[2]}']
+   elif op[0] == 'mfspr':
+      if ops[1] in sprNames:
+         op = ['mfspr', f'{ops[0]},{sprNames[ops[1]]}']
+   elif op[0] == 'mtspr':
+      if ops[0] in sprNames:
+         op = ['mtspr', f'{sprNames[ops[0]]},{ops[1]}']
+
+   if hexify:
+      for i in range(len(ops)):
+         try:
+            if int(ops[i]) > 10:
+               ops[i] = f'0x{int(ops[i]):X}'
+         except:
+            pass
+      op[1] = ','.join(ops)
+
+   return op
+
+def main():
+
+   while True:
+
+      l = fi.readline()
+
+      if not l:
+         return 0
+
+      if l[0] == 'x' or l[0] == 'z':
+         fo.write(f'?{colors["x"]}?X\n')
+      else:
+         t = dasm(l)
+         ins = t[0]
+         ops = t[1]
+         # could convert decimals > 10 to hex in operands
+         if ins[0:2] == '0x' and 'data' in colors:
+            color = colors['data']
+         elif ins in colors:
+            color = colors[ins]
+         else:
+            color = colors['default']
+         fo.write(f'?{color}?{ins} {ops}\n')
+
+      fo.flush()
+
+
+if __name__ == '__main__':
+	sys.exit(main())
+
+'''
+rgb.c from gtkwave
+
+static struct wave_rgb_color colors[] = {
+WAVE_RGB_COLOR("alice blue", 240, 248, 255),
+WAVE_RGB_COLOR("AliceBlue", 240, 248, 255),
+WAVE_RGB_COLOR("antique white", 250, 235, 215),
+WAVE_RGB_COLOR("AntiqueWhite", 250, 235, 215),
+WAVE_RGB_COLOR("AntiqueWhite1", 255, 239, 219),
+WAVE_RGB_COLOR("AntiqueWhite2", 238, 223, 204),
+WAVE_RGB_COLOR("AntiqueWhite3", 205, 192, 176),
+WAVE_RGB_COLOR("AntiqueWhite4", 139, 131, 120),
+WAVE_RGB_COLOR("aquamarine", 127, 255, 212),
+WAVE_RGB_COLOR("aquamarine1", 127, 255, 212),
+WAVE_RGB_COLOR("aquamarine2", 118, 238, 198),
+WAVE_RGB_COLOR("aquamarine3", 102, 205, 170),
+WAVE_RGB_COLOR("aquamarine4", 69, 139, 116),
+WAVE_RGB_COLOR("azure", 240, 255, 255),
+WAVE_RGB_COLOR("azure1", 240, 255, 255),
+WAVE_RGB_COLOR("azure2", 224, 238, 238),
+WAVE_RGB_COLOR("azure3", 193, 205, 205),
+WAVE_RGB_COLOR("azure4", 131, 139, 139),
+WAVE_RGB_COLOR("beige", 245, 245, 220),
+WAVE_RGB_COLOR("bisque", 255, 228, 196),
+WAVE_RGB_COLOR("bisque1", 255, 228, 196),
+WAVE_RGB_COLOR("bisque2", 238, 213, 183),
+WAVE_RGB_COLOR("bisque3", 205, 183, 158),
+WAVE_RGB_COLOR("bisque4", 139, 125, 107),
+WAVE_RGB_COLOR("black", 0, 0, 0),
+WAVE_RGB_COLOR("blanched almond", 255, 235, 205),
+WAVE_RGB_COLOR("BlanchedAlmond", 255, 235, 205),
+WAVE_RGB_COLOR("blue", 0, 0, 255),
+WAVE_RGB_COLOR("blue violet", 138, 43, 226),
+WAVE_RGB_COLOR("blue1", 0, 0, 255),
+WAVE_RGB_COLOR("blue2", 0, 0, 238),
+WAVE_RGB_COLOR("blue3", 0, 0, 205),
+WAVE_RGB_COLOR("blue4", 0, 0, 139),
+WAVE_RGB_COLOR("BlueViolet", 138, 43, 226),
+WAVE_RGB_COLOR("brown", 165, 42, 42),
+WAVE_RGB_COLOR("brown1", 255, 64, 64),
+WAVE_RGB_COLOR("brown2", 238, 59, 59),
+WAVE_RGB_COLOR("brown3", 205, 51, 51),
+WAVE_RGB_COLOR("brown4", 139, 35, 35),
+WAVE_RGB_COLOR("burlywood", 222, 184, 135),
+WAVE_RGB_COLOR("burlywood1", 255, 211, 155),
+WAVE_RGB_COLOR("burlywood2", 238, 197, 145),
+WAVE_RGB_COLOR("burlywood3", 205, 170, 125),
+WAVE_RGB_COLOR("burlywood4", 139, 115, 85),
+WAVE_RGB_COLOR("cadet blue", 95, 158, 160),
+WAVE_RGB_COLOR("CadetBlue", 95, 158, 160),
+WAVE_RGB_COLOR("CadetBlue1", 152, 245, 255),
+WAVE_RGB_COLOR("CadetBlue2", 142, 229, 238),
+WAVE_RGB_COLOR("CadetBlue3", 122, 197, 205),
+WAVE_RGB_COLOR("CadetBlue4", 83, 134, 139),
+WAVE_RGB_COLOR("chartreuse", 127, 255, 0),
+WAVE_RGB_COLOR("chartreuse1", 127, 255, 0),
+WAVE_RGB_COLOR("chartreuse2", 118, 238, 0),
+WAVE_RGB_COLOR("chartreuse3", 102, 205, 0),
+WAVE_RGB_COLOR("chartreuse4", 69, 139, 0),
+WAVE_RGB_COLOR("chocolate", 210, 105, 30),
+WAVE_RGB_COLOR("chocolate1", 255, 127, 36),
+WAVE_RGB_COLOR("chocolate2", 238, 118, 33),
+WAVE_RGB_COLOR("chocolate3", 205, 102, 29),
+WAVE_RGB_COLOR("chocolate4", 139, 69, 19),
+WAVE_RGB_COLOR("coral", 255, 127, 80),
+WAVE_RGB_COLOR("coral1", 255, 114, 86),
+WAVE_RGB_COLOR("coral2", 238, 106, 80),
+WAVE_RGB_COLOR("coral3", 205, 91, 69),
+WAVE_RGB_COLOR("coral4", 139, 62, 47),
+WAVE_RGB_COLOR("cornflower blue", 100, 149, 237),
+WAVE_RGB_COLOR("CornflowerBlue", 100, 149, 237),
+WAVE_RGB_COLOR("cornsilk", 255, 248, 220),
+WAVE_RGB_COLOR("cornsilk1", 255, 248, 220),
+WAVE_RGB_COLOR("cornsilk2", 238, 232, 205),
+WAVE_RGB_COLOR("cornsilk3", 205, 200, 177),
+WAVE_RGB_COLOR("cornsilk4", 139, 136, 120),
+WAVE_RGB_COLOR("cyan", 0, 255, 255),
+WAVE_RGB_COLOR("cyan1", 0, 255, 255),
+WAVE_RGB_COLOR("cyan2", 0, 238, 238),
+WAVE_RGB_COLOR("cyan3", 0, 205, 205),
+WAVE_RGB_COLOR("cyan4", 0, 139, 139),
+WAVE_RGB_COLOR("dark blue", 0, 0, 139),
+WAVE_RGB_COLOR("dark cyan", 0, 139, 139),
+WAVE_RGB_COLOR("dark goldenrod", 184, 134, 11),
+WAVE_RGB_COLOR("dark gray", 169, 169, 169),
+WAVE_RGB_COLOR("dark green", 0, 100, 0),
+WAVE_RGB_COLOR("dark grey", 169, 169, 169),
+WAVE_RGB_COLOR("dark khaki", 189, 183, 107),
+WAVE_RGB_COLOR("dark magenta", 139, 0, 139),
+WAVE_RGB_COLOR("dark olive green", 85, 107, 47),
+WAVE_RGB_COLOR("dark orange", 255, 140, 0),
+WAVE_RGB_COLOR("dark orchid", 153, 50, 204),
+WAVE_RGB_COLOR("dark red", 139, 0, 0),
+WAVE_RGB_COLOR("dark salmon", 233, 150, 122),
+WAVE_RGB_COLOR("dark sea green", 143, 188, 143),
+WAVE_RGB_COLOR("dark slate blue", 72, 61, 139),
+WAVE_RGB_COLOR("dark slate gray", 47, 79, 79),
+WAVE_RGB_COLOR("dark slate grey", 47, 79, 79),
+WAVE_RGB_COLOR("dark turquoise", 0, 206, 209),
+WAVE_RGB_COLOR("dark violet", 148, 0, 211),
+WAVE_RGB_COLOR("DarkBlue", 0, 0, 139),
+WAVE_RGB_COLOR("DarkCyan", 0, 139, 139),
+WAVE_RGB_COLOR("DarkGoldenrod", 184, 134, 11),
+WAVE_RGB_COLOR("DarkGoldenrod1", 255, 185, 15),
+WAVE_RGB_COLOR("DarkGoldenrod2", 238, 173, 14),
+WAVE_RGB_COLOR("DarkGoldenrod3", 205, 149, 12),
+WAVE_RGB_COLOR("DarkGoldenrod4", 139, 101, 8),
+WAVE_RGB_COLOR("DarkGray", 169, 169, 169),
+WAVE_RGB_COLOR("DarkGreen", 0, 100, 0),
+WAVE_RGB_COLOR("DarkGrey", 169, 169, 169),
+WAVE_RGB_COLOR("DarkKhaki", 189, 183, 107),
+WAVE_RGB_COLOR("DarkMagenta", 139, 0, 139),
+WAVE_RGB_COLOR("DarkOliveGreen", 85, 107, 47),
+WAVE_RGB_COLOR("DarkOliveGreen1", 202, 255, 112),
+WAVE_RGB_COLOR("DarkOliveGreen2", 188, 238, 104),
+WAVE_RGB_COLOR("DarkOliveGreen3", 162, 205, 90),
+WAVE_RGB_COLOR("DarkOliveGreen4", 110, 139, 61),
+WAVE_RGB_COLOR("DarkOrange", 255, 140, 0),
+WAVE_RGB_COLOR("DarkOrange1", 255, 127, 0),
+WAVE_RGB_COLOR("DarkOrange2", 238, 118, 0),
+WAVE_RGB_COLOR("DarkOrange3", 205, 102, 0),
+WAVE_RGB_COLOR("DarkOrange4", 139, 69, 0),
+WAVE_RGB_COLOR("DarkOrchid", 153, 50, 204),
+WAVE_RGB_COLOR("DarkOrchid1", 191, 62, 255),
+WAVE_RGB_COLOR("DarkOrchid2", 178, 58, 238),
+WAVE_RGB_COLOR("DarkOrchid3", 154, 50, 205),
+WAVE_RGB_COLOR("DarkOrchid4", 104, 34, 139),
+WAVE_RGB_COLOR("DarkRed", 139, 0, 0),
+WAVE_RGB_COLOR("DarkSalmon", 233, 150, 122),
+WAVE_RGB_COLOR("DarkSeaGreen", 143, 188, 143),
+WAVE_RGB_COLOR("DarkSeaGreen1", 193, 255, 193),
+WAVE_RGB_COLOR("DarkSeaGreen2", 180, 238, 180),
+WAVE_RGB_COLOR("DarkSeaGreen3", 155, 205, 155),
+WAVE_RGB_COLOR("DarkSeaGreen4", 105, 139, 105),
+WAVE_RGB_COLOR("DarkSlateBlue", 72, 61, 139),
+WAVE_RGB_COLOR("DarkSlateGray", 47, 79, 79),
+WAVE_RGB_COLOR("DarkSlateGray1", 151, 255, 255),
+WAVE_RGB_COLOR("DarkSlateGray2", 141, 238, 238),
+WAVE_RGB_COLOR("DarkSlateGray3", 121, 205, 205),
+WAVE_RGB_COLOR("DarkSlateGray4", 82, 139, 139),
+WAVE_RGB_COLOR("DarkSlateGrey", 47, 79, 79),
+WAVE_RGB_COLOR("DarkTurquoise", 0, 206, 209),
+WAVE_RGB_COLOR("DarkViolet", 148, 0, 211),
+WAVE_RGB_COLOR("deep pink", 255, 20, 147),
+WAVE_RGB_COLOR("deep sky blue", 0, 191, 255),
+WAVE_RGB_COLOR("DeepPink", 255, 20, 147),
+WAVE_RGB_COLOR("DeepPink1", 255, 20, 147),
+WAVE_RGB_COLOR("DeepPink2", 238, 18, 137),
+WAVE_RGB_COLOR("DeepPink3", 205, 16, 118),
+WAVE_RGB_COLOR("DeepPink4", 139, 10, 80),
+WAVE_RGB_COLOR("DeepSkyBlue", 0, 191, 255),
+WAVE_RGB_COLOR("DeepSkyBlue1", 0, 191, 255),
+WAVE_RGB_COLOR("DeepSkyBlue2", 0, 178, 238),
+WAVE_RGB_COLOR("DeepSkyBlue3", 0, 154, 205),
+WAVE_RGB_COLOR("DeepSkyBlue4", 0, 104, 139),
+WAVE_RGB_COLOR("dim gray", 105, 105, 105),
+WAVE_RGB_COLOR("dim grey", 105, 105, 105),
+WAVE_RGB_COLOR("DimGray", 105, 105, 105),
+WAVE_RGB_COLOR("DimGrey", 105, 105, 105),
+WAVE_RGB_COLOR("dodger blue", 30, 144, 255),
+WAVE_RGB_COLOR("DodgerBlue", 30, 144, 255),
+WAVE_RGB_COLOR("DodgerBlue1", 30, 144, 255),
+WAVE_RGB_COLOR("DodgerBlue2", 28, 134, 238),
+WAVE_RGB_COLOR("DodgerBlue3", 24, 116, 205),
+WAVE_RGB_COLOR("DodgerBlue4", 16, 78, 139),
+WAVE_RGB_COLOR("firebrick", 178, 34, 34),
+WAVE_RGB_COLOR("firebrick1", 255, 48, 48),
+WAVE_RGB_COLOR("firebrick2", 238, 44, 44),
+WAVE_RGB_COLOR("firebrick3", 205, 38, 38),
+WAVE_RGB_COLOR("firebrick4", 139, 26, 26),
+WAVE_RGB_COLOR("floral white", 255, 250, 240),
+WAVE_RGB_COLOR("FloralWhite", 255, 250, 240),
+WAVE_RGB_COLOR("forest green", 34, 139, 34),
+WAVE_RGB_COLOR("ForestGreen", 34, 139, 34),
+WAVE_RGB_COLOR("gainsboro", 220, 220, 220),
+WAVE_RGB_COLOR("ghost white", 248, 248, 255),
+WAVE_RGB_COLOR("GhostWhite", 248, 248, 255),
+WAVE_RGB_COLOR("gold", 255, 215, 0),
+WAVE_RGB_COLOR("gold1", 255, 215, 0),
+WAVE_RGB_COLOR("gold2", 238, 201, 0),
+WAVE_RGB_COLOR("gold3", 205, 173, 0),
+WAVE_RGB_COLOR("gold4", 139, 117, 0),
+WAVE_RGB_COLOR("goldenrod", 218, 165, 32),
+WAVE_RGB_COLOR("goldenrod1", 255, 193, 37),
+WAVE_RGB_COLOR("goldenrod2", 238, 180, 34),
+WAVE_RGB_COLOR("goldenrod3", 205, 155, 29),
+WAVE_RGB_COLOR("goldenrod4", 139, 105, 20),
+WAVE_RGB_COLOR("gray", 190, 190, 190),
+WAVE_RGB_COLOR("gray0", 0, 0, 0),
+WAVE_RGB_COLOR("gray1", 3, 3, 3),
+WAVE_RGB_COLOR("gray10", 26, 26, 26),
+WAVE_RGB_COLOR("gray100", 255, 255, 255),
+WAVE_RGB_COLOR("gray11", 28, 28, 28),
+WAVE_RGB_COLOR("gray12", 31, 31, 31),
+WAVE_RGB_COLOR("gray13", 33, 33, 33),
+WAVE_RGB_COLOR("gray14", 36, 36, 36),
+WAVE_RGB_COLOR("gray15", 38, 38, 38),
+WAVE_RGB_COLOR("gray16", 41, 41, 41),
+WAVE_RGB_COLOR("gray17", 43, 43, 43),
+WAVE_RGB_COLOR("gray18", 46, 46, 46),
+WAVE_RGB_COLOR("gray19", 48, 48, 48),
+WAVE_RGB_COLOR("gray2", 5, 5, 5),
+WAVE_RGB_COLOR("gray20", 51, 51, 51),
+WAVE_RGB_COLOR("gray21", 54, 54, 54),
+WAVE_RGB_COLOR("gray22", 56, 56, 56),
+WAVE_RGB_COLOR("gray23", 59, 59, 59),
+WAVE_RGB_COLOR("gray24", 61, 61, 61),
+WAVE_RGB_COLOR("gray25", 64, 64, 64),
+WAVE_RGB_COLOR("gray26", 66, 66, 66),
+WAVE_RGB_COLOR("gray27", 69, 69, 69),
+WAVE_RGB_COLOR("gray28", 71, 71, 71),
+WAVE_RGB_COLOR("gray29", 74, 74, 74),
+WAVE_RGB_COLOR("gray3", 8, 8, 8),
+WAVE_RGB_COLOR("gray30", 77, 77, 77),
+WAVE_RGB_COLOR("gray31", 79, 79, 79),
+WAVE_RGB_COLOR("gray32", 82, 82, 82),
+WAVE_RGB_COLOR("gray33", 84, 84, 84),
+WAVE_RGB_COLOR("gray34", 87, 87, 87),
+WAVE_RGB_COLOR("gray35", 89, 89, 89),
+WAVE_RGB_COLOR("gray36", 92, 92, 92),
+WAVE_RGB_COLOR("gray37", 94, 94, 94),
+WAVE_RGB_COLOR("gray38", 97, 97, 97),
+WAVE_RGB_COLOR("gray39", 99, 99, 99),
+WAVE_RGB_COLOR("gray4", 10, 10, 10),
+WAVE_RGB_COLOR("gray40", 102, 102, 102),
+WAVE_RGB_COLOR("gray41", 105, 105, 105),
+WAVE_RGB_COLOR("gray42", 107, 107, 107),
+WAVE_RGB_COLOR("gray43", 110, 110, 110),
+WAVE_RGB_COLOR("gray44", 112, 112, 112),
+WAVE_RGB_COLOR("gray45", 115, 115, 115),
+WAVE_RGB_COLOR("gray46", 117, 117, 117),
+WAVE_RGB_COLOR("gray47", 120, 120, 120),
+WAVE_RGB_COLOR("gray48", 122, 122, 122),
+WAVE_RGB_COLOR("gray49", 125, 125, 125),
+WAVE_RGB_COLOR("gray5", 13, 13, 13),
+WAVE_RGB_COLOR("gray50", 127, 127, 127),
+WAVE_RGB_COLOR("gray51", 130, 130, 130),
+WAVE_RGB_COLOR("gray52", 133, 133, 133),
+WAVE_RGB_COLOR("gray53", 135, 135, 135),
+WAVE_RGB_COLOR("gray54", 138, 138, 138),
+WAVE_RGB_COLOR("gray55", 140, 140, 140),
+WAVE_RGB_COLOR("gray56", 143, 143, 143),
+WAVE_RGB_COLOR("gray57", 145, 145, 145),
+WAVE_RGB_COLOR("gray58", 148, 148, 148),
+WAVE_RGB_COLOR("gray59", 150, 150, 150),
+WAVE_RGB_COLOR("gray6", 15, 15, 15),
+WAVE_RGB_COLOR("gray60", 153, 153, 153),
+WAVE_RGB_COLOR("gray61", 156, 156, 156),
+WAVE_RGB_COLOR("gray62", 158, 158, 158),
+WAVE_RGB_COLOR("gray63", 161, 161, 161),
+WAVE_RGB_COLOR("gray64", 163, 163, 163),
+WAVE_RGB_COLOR("gray65", 166, 166, 166),
+WAVE_RGB_COLOR("gray66", 168, 168, 168),
+WAVE_RGB_COLOR("gray67", 171, 171, 171),
+WAVE_RGB_COLOR("gray68", 173, 173, 173),
+WAVE_RGB_COLOR("gray69", 176, 176, 176),
+WAVE_RGB_COLOR("gray7", 18, 18, 18),
+WAVE_RGB_COLOR("gray70", 179, 179, 179),
+WAVE_RGB_COLOR("gray71", 181, 181, 181),
+WAVE_RGB_COLOR("gray72", 184, 184, 184),
+WAVE_RGB_COLOR("gray73", 186, 186, 186),
+WAVE_RGB_COLOR("gray74", 189, 189, 189),
+WAVE_RGB_COLOR("gray75", 191, 191, 191),
+WAVE_RGB_COLOR("gray76", 194, 194, 194),
+WAVE_RGB_COLOR("gray77", 196, 196, 196),
+WAVE_RGB_COLOR("gray78", 199, 199, 199),
+WAVE_RGB_COLOR("gray79", 201, 201, 201),
+WAVE_RGB_COLOR("gray8", 20, 20, 20),
+WAVE_RGB_COLOR("gray80", 204, 204, 204),
+WAVE_RGB_COLOR("gray81", 207, 207, 207),
+WAVE_RGB_COLOR("gray82", 209, 209, 209),
+WAVE_RGB_COLOR("gray83", 212, 212, 212),
+WAVE_RGB_COLOR("gray84", 214, 214, 214),
+WAVE_RGB_COLOR("gray85", 217, 217, 217),
+WAVE_RGB_COLOR("gray86", 219, 219, 219),
+WAVE_RGB_COLOR("gray87", 222, 222, 222),
+WAVE_RGB_COLOR("gray88", 224, 224, 224),
+WAVE_RGB_COLOR("gray89", 227, 227, 227),
+WAVE_RGB_COLOR("gray9", 23, 23, 23),
+WAVE_RGB_COLOR("gray90", 229, 229, 229),
+WAVE_RGB_COLOR("gray91", 232, 232, 232),
+WAVE_RGB_COLOR("gray92", 235, 235, 235),
+WAVE_RGB_COLOR("gray93", 237, 237, 237),
+WAVE_RGB_COLOR("gray94", 240, 240, 240),
+WAVE_RGB_COLOR("gray95", 242, 242, 242),
+WAVE_RGB_COLOR("gray96", 245, 245, 245),
+WAVE_RGB_COLOR("gray97", 247, 247, 247),
+WAVE_RGB_COLOR("gray98", 250, 250, 250),
+WAVE_RGB_COLOR("gray99", 252, 252, 252),
+WAVE_RGB_COLOR("green", 0, 255, 0),
+WAVE_RGB_COLOR("green yellow", 173, 255, 47),
+WAVE_RGB_COLOR("green1", 0, 255, 0),
+WAVE_RGB_COLOR("green2", 0, 238, 0),
+WAVE_RGB_COLOR("green3", 0, 205, 0),
+WAVE_RGB_COLOR("green4", 0, 139, 0),
+WAVE_RGB_COLOR("GreenYellow", 173, 255, 47),
+WAVE_RGB_COLOR("grey", 190, 190, 190),
+WAVE_RGB_COLOR("grey0", 0, 0, 0),
+WAVE_RGB_COLOR("grey1", 3, 3, 3),
+WAVE_RGB_COLOR("grey10", 26, 26, 26),
+WAVE_RGB_COLOR("grey100", 255, 255, 255),
+WAVE_RGB_COLOR("grey11", 28, 28, 28),
+WAVE_RGB_COLOR("grey12", 31, 31, 31),
+WAVE_RGB_COLOR("grey13", 33, 33, 33),
+WAVE_RGB_COLOR("grey14", 36, 36, 36),
+WAVE_RGB_COLOR("grey15", 38, 38, 38),
+WAVE_RGB_COLOR("grey16", 41, 41, 41),
+WAVE_RGB_COLOR("grey17", 43, 43, 43),
+WAVE_RGB_COLOR("grey18", 46, 46, 46),
+WAVE_RGB_COLOR("grey19", 48, 48, 48),
+WAVE_RGB_COLOR("grey2", 5, 5, 5),
+WAVE_RGB_COLOR("grey20", 51, 51, 51),
+WAVE_RGB_COLOR("grey21", 54, 54, 54),
+WAVE_RGB_COLOR("grey22", 56, 56, 56),
+WAVE_RGB_COLOR("grey23", 59, 59, 59),
+WAVE_RGB_COLOR("grey24", 61, 61, 61),
+WAVE_RGB_COLOR("grey25", 64, 64, 64),
+WAVE_RGB_COLOR("grey26", 66, 66, 66),
+WAVE_RGB_COLOR("grey27", 69, 69, 69),
+WAVE_RGB_COLOR("grey28", 71, 71, 71),
+WAVE_RGB_COLOR("grey29", 74, 74, 74),
+WAVE_RGB_COLOR("grey3", 8, 8, 8),
+WAVE_RGB_COLOR("grey30", 77, 77, 77),
+WAVE_RGB_COLOR("grey31", 79, 79, 79),
+WAVE_RGB_COLOR("grey32", 82, 82, 82),
+WAVE_RGB_COLOR("grey33", 84, 84, 84),
+WAVE_RGB_COLOR("grey34", 87, 87, 87),
+WAVE_RGB_COLOR("grey35", 89, 89, 89),
+WAVE_RGB_COLOR("grey36", 92, 92, 92),
+WAVE_RGB_COLOR("grey37", 94, 94, 94),
+WAVE_RGB_COLOR("grey38", 97, 97, 97),
+WAVE_RGB_COLOR("grey39", 99, 99, 99),
+WAVE_RGB_COLOR("grey4", 10, 10, 10),
+WAVE_RGB_COLOR("grey40", 102, 102, 102),
+WAVE_RGB_COLOR("grey41", 105, 105, 105),
+WAVE_RGB_COLOR("grey42", 107, 107, 107),
+WAVE_RGB_COLOR("grey43", 110, 110, 110),
+WAVE_RGB_COLOR("grey44", 112, 112, 112),
+WAVE_RGB_COLOR("grey45", 115, 115, 115),
+WAVE_RGB_COLOR("grey46", 117, 117, 117),
+WAVE_RGB_COLOR("grey47", 120, 120, 120),
+WAVE_RGB_COLOR("grey48", 122, 122, 122),
+WAVE_RGB_COLOR("grey49", 125, 125, 125),
+WAVE_RGB_COLOR("grey5", 13, 13, 13),
+WAVE_RGB_COLOR("grey50", 127, 127, 127),
+WAVE_RGB_COLOR("grey51", 130, 130, 130),
+WAVE_RGB_COLOR("grey52", 133, 133, 133),
+WAVE_RGB_COLOR("grey53", 135, 135, 135),
+WAVE_RGB_COLOR("grey54", 138, 138, 138),
+WAVE_RGB_COLOR("grey55", 140, 140, 140),
+WAVE_RGB_COLOR("grey56", 143, 143, 143),
+WAVE_RGB_COLOR("grey57", 145, 145, 145),
+WAVE_RGB_COLOR("grey58", 148, 148, 148),
+WAVE_RGB_COLOR("grey59", 150, 150, 150),
+WAVE_RGB_COLOR("grey6", 15, 15, 15),
+WAVE_RGB_COLOR("grey60", 153, 153, 153),
+WAVE_RGB_COLOR("grey61", 156, 156, 156),
+WAVE_RGB_COLOR("grey62", 158, 158, 158),
+WAVE_RGB_COLOR("grey63", 161, 161, 161),
+WAVE_RGB_COLOR("grey64", 163, 163, 163),
+WAVE_RGB_COLOR("grey65", 166, 166, 166),
+WAVE_RGB_COLOR("grey66", 168, 168, 168),
+WAVE_RGB_COLOR("grey67", 171, 171, 171),
+WAVE_RGB_COLOR("grey68", 173, 173, 173),
+WAVE_RGB_COLOR("grey69", 176, 176, 176),
+WAVE_RGB_COLOR("grey7", 18, 18, 18),
+WAVE_RGB_COLOR("grey70", 179, 179, 179),
+WAVE_RGB_COLOR("grey71", 181, 181, 181),
+WAVE_RGB_COLOR("grey72", 184, 184, 184),
+WAVE_RGB_COLOR("grey73", 186, 186, 186),
+WAVE_RGB_COLOR("grey74", 189, 189, 189),
+WAVE_RGB_COLOR("grey75", 191, 191, 191),
+WAVE_RGB_COLOR("grey76", 194, 194, 194),
+WAVE_RGB_COLOR("grey77", 196, 196, 196),
+WAVE_RGB_COLOR("grey78", 199, 199, 199),
+WAVE_RGB_COLOR("grey79", 201, 201, 201),
+WAVE_RGB_COLOR("grey8", 20, 20, 20),
+WAVE_RGB_COLOR("grey80", 204, 204, 204),
+WAVE_RGB_COLOR("grey81", 207, 207, 207),
+WAVE_RGB_COLOR("grey82", 209, 209, 209),
+WAVE_RGB_COLOR("grey83", 212, 212, 212),
+WAVE_RGB_COLOR("grey84", 214, 214, 214),
+WAVE_RGB_COLOR("grey85", 217, 217, 217),
+WAVE_RGB_COLOR("grey86", 219, 219, 219),
+WAVE_RGB_COLOR("grey87", 222, 222, 222),
+WAVE_RGB_COLOR("grey88", 224, 224, 224),
+WAVE_RGB_COLOR("grey89", 227, 227, 227),
+WAVE_RGB_COLOR("grey9", 23, 23, 23),
+WAVE_RGB_COLOR("grey90", 229, 229, 229),
+WAVE_RGB_COLOR("grey91", 232, 232, 232),
+WAVE_RGB_COLOR("grey92", 235, 235, 235),
+WAVE_RGB_COLOR("grey93", 237, 237, 237),
+WAVE_RGB_COLOR("grey94", 240, 240, 240),
+WAVE_RGB_COLOR("grey95", 242, 242, 242),
+WAVE_RGB_COLOR("grey96", 245, 245, 245),
+WAVE_RGB_COLOR("grey97", 247, 247, 247),
+WAVE_RGB_COLOR("grey98", 250, 250, 250),
+WAVE_RGB_COLOR("grey99", 252, 252, 252),
+WAVE_RGB_COLOR("honeydew", 240, 255, 240),
+WAVE_RGB_COLOR("honeydew1", 240, 255, 240),
+WAVE_RGB_COLOR("honeydew2", 224, 238, 224),
+WAVE_RGB_COLOR("honeydew3", 193, 205, 193),
+WAVE_RGB_COLOR("honeydew4", 131, 139, 131),
+WAVE_RGB_COLOR("hot pink", 255, 105, 180),
+WAVE_RGB_COLOR("HotPink", 255, 105, 180),
+WAVE_RGB_COLOR("HotPink1", 255, 110, 180),
+WAVE_RGB_COLOR("HotPink2", 238, 106, 167),
+WAVE_RGB_COLOR("HotPink3", 205, 96, 144),
+WAVE_RGB_COLOR("HotPink4", 139, 58, 98),
+WAVE_RGB_COLOR("indian red", 205, 92, 92),
+WAVE_RGB_COLOR("IndianRed", 205, 92, 92),
+WAVE_RGB_COLOR("IndianRed1", 255, 106, 106),
+WAVE_RGB_COLOR("IndianRed2", 238, 99, 99),
+WAVE_RGB_COLOR("IndianRed3", 205, 85, 85),
+WAVE_RGB_COLOR("IndianRed4", 139, 58, 58),
+WAVE_RGB_COLOR("ivory", 255, 255, 240),
+WAVE_RGB_COLOR("ivory1", 255, 255, 240),
+WAVE_RGB_COLOR("ivory2", 238, 238, 224),
+WAVE_RGB_COLOR("ivory3", 205, 205, 193),
+WAVE_RGB_COLOR("ivory4", 139, 139, 131),
+WAVE_RGB_COLOR("khaki", 240, 230, 140),
+WAVE_RGB_COLOR("khaki1", 255, 246, 143),
+WAVE_RGB_COLOR("khaki2", 238, 230, 133),
+WAVE_RGB_COLOR("khaki3", 205, 198, 115),
+WAVE_RGB_COLOR("khaki4", 139, 134, 78),
+WAVE_RGB_COLOR("lavender", 230, 230, 250),
+WAVE_RGB_COLOR("lavender blush", 255, 240, 245),
+WAVE_RGB_COLOR("LavenderBlush", 255, 240, 245),
+WAVE_RGB_COLOR("LavenderBlush1", 255, 240, 245),
+WAVE_RGB_COLOR("LavenderBlush2", 238, 224, 229),
+WAVE_RGB_COLOR("LavenderBlush3", 205, 193, 197),
+WAVE_RGB_COLOR("LavenderBlush4", 139, 131, 134),
+WAVE_RGB_COLOR("lawn green", 124, 252, 0),
+WAVE_RGB_COLOR("LawnGreen", 124, 252, 0),
+WAVE_RGB_COLOR("lemon chiffon", 255, 250, 205),
+WAVE_RGB_COLOR("LemonChiffon", 255, 250, 205),
+WAVE_RGB_COLOR("LemonChiffon1", 255, 250, 205),
+WAVE_RGB_COLOR("LemonChiffon2", 238, 233, 191),
+WAVE_RGB_COLOR("LemonChiffon3", 205, 201, 165),
+WAVE_RGB_COLOR("LemonChiffon4", 139, 137, 112),
+WAVE_RGB_COLOR("light blue", 173, 216, 230),
+WAVE_RGB_COLOR("light coral", 240, 128, 128),
+WAVE_RGB_COLOR("light cyan", 224, 255, 255),
+WAVE_RGB_COLOR("light goldenrod", 238, 221, 130),
+WAVE_RGB_COLOR("light goldenrod yellow", 250, 250, 210),
+WAVE_RGB_COLOR("light gray", 211, 211, 211),
+WAVE_RGB_COLOR("light green", 144, 238, 144),
+WAVE_RGB_COLOR("light grey", 211, 211, 211),
+WAVE_RGB_COLOR("light pink", 255, 182, 193),
+WAVE_RGB_COLOR("light salmon", 255, 160, 122),
+WAVE_RGB_COLOR("light sea green", 32, 178, 170),
+WAVE_RGB_COLOR("light sky blue", 135, 206, 250),
+WAVE_RGB_COLOR("light slate blue", 132, 112, 255),
+WAVE_RGB_COLOR("light slate gray", 119, 136, 153),
+WAVE_RGB_COLOR("light slate grey", 119, 136, 153),
+WAVE_RGB_COLOR("light steel blue", 176, 196, 222),
+WAVE_RGB_COLOR("light yellow", 255, 255, 224),
+WAVE_RGB_COLOR("LightBlue", 173, 216, 230),
+WAVE_RGB_COLOR("LightBlue1", 191, 239, 255),
+WAVE_RGB_COLOR("LightBlue2", 178, 223, 238),
+WAVE_RGB_COLOR("LightBlue3", 154, 192, 205),
+WAVE_RGB_COLOR("LightBlue4", 104, 131, 139),
+WAVE_RGB_COLOR("LightCoral", 240, 128, 128),
+WAVE_RGB_COLOR("LightCyan", 224, 255, 255),
+WAVE_RGB_COLOR("LightCyan1", 224, 255, 255),
+WAVE_RGB_COLOR("LightCyan2", 209, 238, 238),
+WAVE_RGB_COLOR("LightCyan3", 180, 205, 205),
+WAVE_RGB_COLOR("LightCyan4", 122, 139, 139),
+WAVE_RGB_COLOR("LightGoldenrod", 238, 221, 130),
+WAVE_RGB_COLOR("LightGoldenrod1", 255, 236, 139),
+WAVE_RGB_COLOR("LightGoldenrod2", 238, 220, 130),
+WAVE_RGB_COLOR("LightGoldenrod3", 205, 190, 112),
+WAVE_RGB_COLOR("LightGoldenrod4", 139, 129, 76),
+WAVE_RGB_COLOR("LightGoldenrodYellow", 250, 250, 210),
+WAVE_RGB_COLOR("LightGray", 211, 211, 211),
+WAVE_RGB_COLOR("LightGreen", 144, 238, 144),
+WAVE_RGB_COLOR("LightGrey", 211, 211, 211),
+WAVE_RGB_COLOR("LightPink", 255, 182, 193),
+WAVE_RGB_COLOR("LightPink1", 255, 174, 185),
+WAVE_RGB_COLOR("LightPink2", 238, 162, 173),
+WAVE_RGB_COLOR("LightPink3", 205, 140, 149),
+WAVE_RGB_COLOR("LightPink4", 139, 95, 101),
+WAVE_RGB_COLOR("LightSalmon", 255, 160, 122),
+WAVE_RGB_COLOR("LightSalmon1", 255, 160, 122),
+WAVE_RGB_COLOR("LightSalmon2", 238, 149, 114),
+WAVE_RGB_COLOR("LightSalmon3", 205, 129, 98),
+WAVE_RGB_COLOR("LightSalmon4", 139, 87, 66),
+WAVE_RGB_COLOR("LightSeaGreen", 32, 178, 170),
+WAVE_RGB_COLOR("LightSkyBlue", 135, 206, 250),
+WAVE_RGB_COLOR("LightSkyBlue1", 176, 226, 255),
+WAVE_RGB_COLOR("LightSkyBlue2", 164, 211, 238),
+WAVE_RGB_COLOR("LightSkyBlue3", 141, 182, 205),
+WAVE_RGB_COLOR("LightSkyBlue4", 96, 123, 139),
+WAVE_RGB_COLOR("LightSlateBlue", 132, 112, 255),
+WAVE_RGB_COLOR("LightSlateGray", 119, 136, 153),
+WAVE_RGB_COLOR("LightSlateGrey", 119, 136, 153),
+WAVE_RGB_COLOR("LightSteelBlue", 176, 196, 222),
+WAVE_RGB_COLOR("LightSteelBlue1", 202, 225, 255),
+WAVE_RGB_COLOR("LightSteelBlue2", 188, 210, 238),
+WAVE_RGB_COLOR("LightSteelBlue3", 162, 181, 205),
+WAVE_RGB_COLOR("LightSteelBlue4", 110, 123, 139),
+WAVE_RGB_COLOR("LightYellow", 255, 255, 224),
+WAVE_RGB_COLOR("LightYellow1", 255, 255, 224),
+WAVE_RGB_COLOR("LightYellow2", 238, 238, 209),
+WAVE_RGB_COLOR("LightYellow3", 205, 205, 180),
+WAVE_RGB_COLOR("LightYellow4", 139, 139, 122),
+WAVE_RGB_COLOR("lime green", 50, 205, 50),
+WAVE_RGB_COLOR("LimeGreen", 50, 205, 50),
+WAVE_RGB_COLOR("linen", 250, 240, 230),
+WAVE_RGB_COLOR("magenta", 255, 0, 255),
+WAVE_RGB_COLOR("magenta1", 255, 0, 255),
+WAVE_RGB_COLOR("magenta2", 238, 0, 238),
+WAVE_RGB_COLOR("magenta3", 205, 0, 205),
+WAVE_RGB_COLOR("magenta4", 139, 0, 139),
+WAVE_RGB_COLOR("maroon", 176, 48, 96),
+WAVE_RGB_COLOR("maroon1", 255, 52, 179),
+WAVE_RGB_COLOR("maroon2", 238, 48, 167),
+WAVE_RGB_COLOR("maroon3", 205, 41, 144),
+WAVE_RGB_COLOR("maroon4", 139, 28, 98),
+WAVE_RGB_COLOR("medium aquamarine", 102, 205, 170),
+WAVE_RGB_COLOR("medium blue", 0, 0, 205),
+WAVE_RGB_COLOR("medium orchid", 186, 85, 211),
+WAVE_RGB_COLOR("medium purple", 147, 112, 219),
+WAVE_RGB_COLOR("medium sea green", 60, 179, 113),
+WAVE_RGB_COLOR("medium slate blue", 123, 104, 238),
+WAVE_RGB_COLOR("medium spring green", 0, 250, 154),
+WAVE_RGB_COLOR("medium turquoise", 72, 209, 204),
+WAVE_RGB_COLOR("medium violet red", 199, 21, 133),
+WAVE_RGB_COLOR("MediumAquamarine", 102, 205, 170),
+WAVE_RGB_COLOR("MediumBlue", 0, 0, 205),
+WAVE_RGB_COLOR("MediumOrchid", 186, 85, 211),
+WAVE_RGB_COLOR("MediumOrchid1", 224, 102, 255),
+WAVE_RGB_COLOR("MediumOrchid2", 209, 95, 238),
+WAVE_RGB_COLOR("MediumOrchid3", 180, 82, 205),
+WAVE_RGB_COLOR("MediumOrchid4", 122, 55, 139),
+WAVE_RGB_COLOR("MediumPurple", 147, 112, 219),
+WAVE_RGB_COLOR("MediumPurple1", 171, 130, 255),
+WAVE_RGB_COLOR("MediumPurple2", 159, 121, 238),
+WAVE_RGB_COLOR("MediumPurple3", 137, 104, 205),
+WAVE_RGB_COLOR("MediumPurple4", 93, 71, 139),
+WAVE_RGB_COLOR("MediumSeaGreen", 60, 179, 113),
+WAVE_RGB_COLOR("MediumSlateBlue", 123, 104, 238),
+WAVE_RGB_COLOR("MediumSpringGreen", 0, 250, 154),
+WAVE_RGB_COLOR("MediumTurquoise", 72, 209, 204),
+WAVE_RGB_COLOR("MediumVioletRed", 199, 21, 133),
+WAVE_RGB_COLOR("midnight blue", 25, 25, 112),
+WAVE_RGB_COLOR("MidnightBlue", 25, 25, 112),
+WAVE_RGB_COLOR("mint cream", 245, 255, 250),
+WAVE_RGB_COLOR("MintCream", 245, 255, 250),
+WAVE_RGB_COLOR("misty rose", 255, 228, 225),
+WAVE_RGB_COLOR("MistyRose", 255, 228, 225),
+WAVE_RGB_COLOR("MistyRose1", 255, 228, 225),
+WAVE_RGB_COLOR("MistyRose2", 238, 213, 210),
+WAVE_RGB_COLOR("MistyRose3", 205, 183, 181),
+WAVE_RGB_COLOR("MistyRose4", 139, 125, 123),
+WAVE_RGB_COLOR("moccasin", 255, 228, 181),
+WAVE_RGB_COLOR("navajo white", 255, 222, 173),
+WAVE_RGB_COLOR("NavajoWhite", 255, 222, 173),
+WAVE_RGB_COLOR("NavajoWhite1", 255, 222, 173),
+WAVE_RGB_COLOR("NavajoWhite2", 238, 207, 161),
+WAVE_RGB_COLOR("NavajoWhite3", 205, 179, 139),
+WAVE_RGB_COLOR("NavajoWhite4", 139, 121, 94),
+WAVE_RGB_COLOR("navy", 0, 0, 128),
+WAVE_RGB_COLOR("navy blue", 0, 0, 128),
+WAVE_RGB_COLOR("NavyBlue", 0, 0, 128),
+WAVE_RGB_COLOR("old lace", 253, 245, 230),
+WAVE_RGB_COLOR("OldLace", 253, 245, 230),
+WAVE_RGB_COLOR("olive drab", 107, 142, 35),
+WAVE_RGB_COLOR("OliveDrab", 107, 142, 35),
+WAVE_RGB_COLOR("OliveDrab1", 192, 255, 62),
+WAVE_RGB_COLOR("OliveDrab2", 179, 238, 58),
+WAVE_RGB_COLOR("OliveDrab3", 154, 205, 50),
+WAVE_RGB_COLOR("OliveDrab4", 105, 139, 34),
+WAVE_RGB_COLOR("orange", 255, 165, 0),
+WAVE_RGB_COLOR("orange red", 255, 69, 0),
+WAVE_RGB_COLOR("orange1", 255, 165, 0),
+WAVE_RGB_COLOR("orange2", 238, 154, 0),
+WAVE_RGB_COLOR("orange3", 205, 133, 0),
+WAVE_RGB_COLOR("orange4", 139, 90, 0),
+WAVE_RGB_COLOR("OrangeRed", 255, 69, 0),
+WAVE_RGB_COLOR("OrangeRed1", 255, 69, 0),
+WAVE_RGB_COLOR("OrangeRed2", 238, 64, 0),
+WAVE_RGB_COLOR("OrangeRed3", 205, 55, 0),
+WAVE_RGB_COLOR("OrangeRed4", 139, 37, 0),
+WAVE_RGB_COLOR("orchid", 218, 112, 214),
+WAVE_RGB_COLOR("orchid1", 255, 131, 250),
+WAVE_RGB_COLOR("orchid2", 238, 122, 233),
+WAVE_RGB_COLOR("orchid3", 205, 105, 201),
+WAVE_RGB_COLOR("orchid4", 139, 71, 137),
+WAVE_RGB_COLOR("pale goldenrod", 238, 232, 170),
+WAVE_RGB_COLOR("pale green", 152, 251, 152),
+WAVE_RGB_COLOR("pale turquoise", 175, 238, 238),
+WAVE_RGB_COLOR("pale violet red", 219, 112, 147),
+WAVE_RGB_COLOR("PaleGoldenrod", 238, 232, 170),
+WAVE_RGB_COLOR("PaleGreen", 152, 251, 152),
+WAVE_RGB_COLOR("PaleGreen1", 154, 255, 154),
+WAVE_RGB_COLOR("PaleGreen2", 144, 238, 144),
+WAVE_RGB_COLOR("PaleGreen3", 124, 205, 124),
+WAVE_RGB_COLOR("PaleGreen4", 84, 139, 84),
+WAVE_RGB_COLOR("PaleTurquoise", 175, 238, 238),
+WAVE_RGB_COLOR("PaleTurquoise1", 187, 255, 255),
+WAVE_RGB_COLOR("PaleTurquoise2", 174, 238, 238),
+WAVE_RGB_COLOR("PaleTurquoise3", 150, 205, 205),
+WAVE_RGB_COLOR("PaleTurquoise4", 102, 139, 139),
+WAVE_RGB_COLOR("PaleVioletRed", 219, 112, 147),
+WAVE_RGB_COLOR("PaleVioletRed1", 255, 130, 171),
+WAVE_RGB_COLOR("PaleVioletRed2", 238, 121, 159),
+WAVE_RGB_COLOR("PaleVioletRed3", 205, 104, 137),
+WAVE_RGB_COLOR("PaleVioletRed4", 139, 71, 93),
+WAVE_RGB_COLOR("papaya whip", 255, 239, 213),
+WAVE_RGB_COLOR("PapayaWhip", 255, 239, 213),
+WAVE_RGB_COLOR("peach puff", 255, 218, 185),
+WAVE_RGB_COLOR("PeachPuff", 255, 218, 185),
+WAVE_RGB_COLOR("PeachPuff1", 255, 218, 185),
+WAVE_RGB_COLOR("PeachPuff2", 238, 203, 173),
+WAVE_RGB_COLOR("PeachPuff3", 205, 175, 149),
+WAVE_RGB_COLOR("PeachPuff4", 139, 119, 101),
+WAVE_RGB_COLOR("peru", 205, 133, 63),
+WAVE_RGB_COLOR("pink", 255, 192, 203),
+WAVE_RGB_COLOR("pink1", 255, 181, 197),
+WAVE_RGB_COLOR("pink2", 238, 169, 184),
+WAVE_RGB_COLOR("pink3", 205, 145, 158),
+WAVE_RGB_COLOR("pink4", 139, 99, 108),
+WAVE_RGB_COLOR("plum", 221, 160, 221),
+WAVE_RGB_COLOR("plum1", 255, 187, 255),
+WAVE_RGB_COLOR("plum2", 238, 174, 238),
+WAVE_RGB_COLOR("plum3", 205, 150, 205),
+WAVE_RGB_COLOR("plum4", 139, 102, 139),
+WAVE_RGB_COLOR("powder blue", 176, 224, 230),
+WAVE_RGB_COLOR("PowderBlue", 176, 224, 230),
+WAVE_RGB_COLOR("purple", 160, 32, 240),
+WAVE_RGB_COLOR("purple1", 155, 48, 255),
+WAVE_RGB_COLOR("purple2", 145, 44, 238),
+WAVE_RGB_COLOR("purple3", 125, 38, 205),
+WAVE_RGB_COLOR("purple4", 85, 26, 139),
+WAVE_RGB_COLOR("red", 255, 0, 0),
+WAVE_RGB_COLOR("red1", 255, 0, 0),
+WAVE_RGB_COLOR("red2", 238, 0, 0),
+WAVE_RGB_COLOR("red3", 205, 0, 0),
+WAVE_RGB_COLOR("red4", 139, 0, 0),
+WAVE_RGB_COLOR("rosy brown", 188, 143, 143),
+WAVE_RGB_COLOR("RosyBrown", 188, 143, 143),
+WAVE_RGB_COLOR("RosyBrown1", 255, 193, 193),
+WAVE_RGB_COLOR("RosyBrown2", 238, 180, 180),
+WAVE_RGB_COLOR("RosyBrown3", 205, 155, 155),
+WAVE_RGB_COLOR("RosyBrown4", 139, 105, 105),
+WAVE_RGB_COLOR("royal blue", 65, 105, 225),
+WAVE_RGB_COLOR("RoyalBlue", 65, 105, 225),
+WAVE_RGB_COLOR("RoyalBlue1", 72, 118, 255),
+WAVE_RGB_COLOR("RoyalBlue2", 67, 110, 238),
+WAVE_RGB_COLOR("RoyalBlue3", 58, 95, 205),
+WAVE_RGB_COLOR("RoyalBlue4", 39, 64, 139),
+WAVE_RGB_COLOR("saddle brown", 139, 69, 19),
+WAVE_RGB_COLOR("SaddleBrown", 139, 69, 19),
+WAVE_RGB_COLOR("salmon", 250, 128, 114),
+WAVE_RGB_COLOR("salmon1", 255, 140, 105),
+WAVE_RGB_COLOR("salmon2", 238, 130, 98),
+WAVE_RGB_COLOR("salmon3", 205, 112, 84),
+WAVE_RGB_COLOR("salmon4", 139, 76, 57),
+WAVE_RGB_COLOR("sandy brown", 244, 164, 96),
+WAVE_RGB_COLOR("SandyBrown", 244, 164, 96),
+WAVE_RGB_COLOR("sea green", 46, 139, 87),
+WAVE_RGB_COLOR("SeaGreen", 46, 139, 87),
+WAVE_RGB_COLOR("SeaGreen1", 84, 255, 159),
+WAVE_RGB_COLOR("SeaGreen2", 78, 238, 148),
+WAVE_RGB_COLOR("SeaGreen3", 67, 205, 128),
+WAVE_RGB_COLOR("SeaGreen4", 46, 139, 87),
+WAVE_RGB_COLOR("seashell", 255, 245, 238),
+WAVE_RGB_COLOR("seashell1", 255, 245, 238),
+WAVE_RGB_COLOR("seashell2", 238, 229, 222),
+WAVE_RGB_COLOR("seashell3", 205, 197, 191),
+WAVE_RGB_COLOR("seashell4", 139, 134, 130),
+WAVE_RGB_COLOR("sienna", 160, 82, 45),
+WAVE_RGB_COLOR("sienna1", 255, 130, 71),
+WAVE_RGB_COLOR("sienna2", 238, 121, 66),
+WAVE_RGB_COLOR("sienna3", 205, 104, 57),
+WAVE_RGB_COLOR("sienna4", 139, 71, 38),
+WAVE_RGB_COLOR("sky blue", 135, 206, 235),
+WAVE_RGB_COLOR("SkyBlue", 135, 206, 235),
+WAVE_RGB_COLOR("SkyBlue1", 135, 206, 255),
+WAVE_RGB_COLOR("SkyBlue2", 126, 192, 238),
+WAVE_RGB_COLOR("SkyBlue3", 108, 166, 205),
+WAVE_RGB_COLOR("SkyBlue4", 74, 112, 139),
+WAVE_RGB_COLOR("slate blue", 106, 90, 205),
+WAVE_RGB_COLOR("slate gray", 112, 128, 144),
+WAVE_RGB_COLOR("slate grey", 112, 128, 144),
+WAVE_RGB_COLOR("SlateBlue", 106, 90, 205),
+WAVE_RGB_COLOR("SlateBlue1", 131, 111, 255),
+WAVE_RGB_COLOR("SlateBlue2", 122, 103, 238),
+WAVE_RGB_COLOR("SlateBlue3", 105, 89, 205),
+WAVE_RGB_COLOR("SlateBlue4", 71, 60, 139),
+WAVE_RGB_COLOR("SlateGray", 112, 128, 144),
+WAVE_RGB_COLOR("SlateGray1", 198, 226, 255),
+WAVE_RGB_COLOR("SlateGray2", 185, 211, 238),
+WAVE_RGB_COLOR("SlateGray3", 159, 182, 205),
+WAVE_RGB_COLOR("SlateGray4", 108, 123, 139),
+WAVE_RGB_COLOR("SlateGrey", 112, 128, 144),
+WAVE_RGB_COLOR("snow", 255, 250, 250),
+WAVE_RGB_COLOR("snow1", 255, 250, 250),
+WAVE_RGB_COLOR("snow2", 238, 233, 233),
+WAVE_RGB_COLOR("snow3", 205, 201, 201),
+WAVE_RGB_COLOR("snow4", 139, 137, 137),
+WAVE_RGB_COLOR("spring green", 0, 255, 127),
+WAVE_RGB_COLOR("SpringGreen", 0, 255, 127),
+WAVE_RGB_COLOR("SpringGreen1", 0, 255, 127),
+WAVE_RGB_COLOR("SpringGreen2", 0, 238, 118),
+WAVE_RGB_COLOR("SpringGreen3", 0, 205, 102),
+WAVE_RGB_COLOR("SpringGreen4", 0, 139, 69),
+WAVE_RGB_COLOR("steel blue", 70, 130, 180),
+WAVE_RGB_COLOR("SteelBlue", 70, 130, 180),
+WAVE_RGB_COLOR("SteelBlue1", 99, 184, 255),
+WAVE_RGB_COLOR("SteelBlue2", 92, 172, 238),
+WAVE_RGB_COLOR("SteelBlue3", 79, 148, 205),
+WAVE_RGB_COLOR("SteelBlue4", 54, 100, 139),
+WAVE_RGB_COLOR("tan", 210, 180, 140),
+WAVE_RGB_COLOR("tan1", 255, 165, 79),
+WAVE_RGB_COLOR("tan2", 238, 154, 73),
+WAVE_RGB_COLOR("tan3", 205, 133, 63),
+WAVE_RGB_COLOR("tan4", 139, 90, 43),
+WAVE_RGB_COLOR("thistle", 216, 191, 216),
+WAVE_RGB_COLOR("thistle1", 255, 225, 255),
+WAVE_RGB_COLOR("thistle2", 238, 210, 238),
+WAVE_RGB_COLOR("thistle3", 205, 181, 205),
+WAVE_RGB_COLOR("thistle4", 139, 123, 139),
+WAVE_RGB_COLOR("tomato", 255, 99, 71),
+WAVE_RGB_COLOR("tomato1", 255, 99, 71),
+WAVE_RGB_COLOR("tomato2", 238, 92, 66),
+WAVE_RGB_COLOR("tomato3", 205, 79, 57),
+WAVE_RGB_COLOR("tomato4", 139, 54, 38),
+WAVE_RGB_COLOR("turquoise", 64, 224, 208),
+WAVE_RGB_COLOR("turquoise1", 0, 245, 255),
+WAVE_RGB_COLOR("turquoise2", 0, 229, 238),
+WAVE_RGB_COLOR("turquoise3", 0, 197, 205),
+WAVE_RGB_COLOR("turquoise4", 0, 134, 139),
+WAVE_RGB_COLOR("violet", 238, 130, 238),
+WAVE_RGB_COLOR("violet red", 208, 32, 144),
+WAVE_RGB_COLOR("VioletRed", 208, 32, 144),
+WAVE_RGB_COLOR("VioletRed1", 255, 62, 150),
+WAVE_RGB_COLOR("VioletRed2", 238, 58, 140),
+WAVE_RGB_COLOR("VioletRed3", 205, 50, 120),
+WAVE_RGB_COLOR("VioletRed4", 139, 34, 82),
+WAVE_RGB_COLOR("wheat", 245, 222, 179),
+WAVE_RGB_COLOR("wheat1", 255, 231, 186),
+WAVE_RGB_COLOR("wheat2", 238, 216, 174),
+WAVE_RGB_COLOR("wheat3", 205, 186, 150),
+WAVE_RGB_COLOR("wheat4", 139, 126, 102),
+WAVE_RGB_COLOR("white", 255, 255, 255),
+WAVE_RGB_COLOR("white smoke", 245, 245, 245),
+WAVE_RGB_COLOR("WhiteSmoke", 245, 245, 245),
+WAVE_RGB_COLOR("yellow", 255, 255, 0),
+WAVE_RGB_COLOR("yellow green", 154, 205, 50),
+WAVE_RGB_COLOR("yellow1", 255, 255, 0),
+WAVE_RGB_COLOR("yellow2", 238, 238, 0),
+WAVE_RGB_COLOR("yellow3", 205, 205, 0),
+WAVE_RGB_COLOR("yellow4", 139, 139, 0),
+WAVE_RGB_COLOR("YellowGreen", 154, 205, 50),
+};
+'''

dev/sim/gtkwave/gtkf-valid.py

@@ -0,0 +1,56 @@
+#!/usr/bin/python3
+# gtkwave process filter
+#
+# display valid+anything else (inc. just valid)
+#
+# format=binary so justification and data length don't matter
+# valid is on left
+
+import sys
+
+colorI = ''
+colorV = '?DarkBlue?'
+colorX = '?red?'
+
+fi = sys.stdin
+fo = sys.stdout
+fe = sys.stderr
+
+debug = False
+
+def dbg(m):
+   if debug:
+      fe.write(m + '\n')
+      fe.flush()
+
+def main():
+
+   while True:
+
+      line = fi.readline()
+      if not line:
+         return 0
+
+      try:
+         if line[0] == 'x' or line[0] == 'z':
+            fo.write(f'{colorX}{line[0]}\n')
+         elif line[0] == '0':
+            if len(line) > 2:
+               fo.write(f'{colorI}{int(line[1:],2):02X}\n')
+            else:
+               fo.write(f'{colorI}\n')
+         else:
+            if len(line) > 2:
+               fo.write(f'{colorV}{int(line[1:],2):02X}\n')
+            else:
+               fo.write(f'{colorV}\n')
+
+      except Exception as e:
+         fe.write('error!\n')
+         fe.write(str(e))
+         fo.write('filter error!\n')
+
+      fo.flush()
+
+if __name__ == '__main__':
+   sys.exit(main())

dev/sim/gtkwave/gtkw.tcl

@@ -0,0 +1,33 @@
+# init for a2o
+
+# install acts on highlighted traces; filter=0 uninstalls
+
+#set which_f [gtkwave::setCurrentTranslateFile ./gtkf-alias.py]
+#puts "$which_f"
+#gtkwave::installFileFilter $which_f
+
+#set which_f [gtkwave::setCurrentTranslateProc ./gtkf-ppc.py]
+#puts "$which_f"
+#gtkwave::installProcFilter $which_f
+
+set sigs [gtkwave::getDisplayedSignals]
+puts "$sigs"
+
+# cant figure out how to unhighlight all; somehow it is remembering after reinvoke
+# unhighlight all
+foreach sig $sigs {
+   puts "$sig off"
+   gtkwave::setTraceHighlightFromNameMatch $sig off
+}
+
+# highlight bus
+set h [list {A2L2_AC_AN}]  ;# combined - does it work?
+set n [gtkwave::highlightSignalsFromList $h]
+
+if {$h > 0} {
+   set f [gtkwave::setCurrentTranslateTransProc ./gtkf-a2l2.py]
+   gtkwave::installTransFilter $f
+} else {
+   puts "Didn't apply trans filter to [lindex $h 0]"
+}
+

dev/sim/gtkwave/gtkwave.ini

@@ -0,0 +1,2 @@
+color_value white
+force_toolbars on

dev/sim/mem/boot.bin.hex

@@ -0,0 +1,982 @@
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dev/sim/mem/boot_normal.bin.hex

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dev/sim/readme.md

@@ -0,0 +1,127 @@
+# Simulation
+
+Building with cocotb, verilator, icarus...
+
+```
+cd coco
+```
+
+## cocotb + Icarus
+
+* A2L2 python interface partially implemented
+* original boot code makes it to jump to (missing) test
+* makegtkw creates netlist
+
+```
+make -f Makefile.icarus run
+...
+  7353.00ns INFO     [00000919] C0: CP 0:00056C 000000000000056C
+  7369.00ns INFO     [00000921] C0: CP 0:000570 0000000000000570
+  7377.00ns INFO     [00000922] RELD tag=08 48000000480000FC6000000060000000 1of4 crit
+  7385.00ns INFO     [00000923] RELD tag=08 60000000600000006000000060000000 2of4
+  7393.00ns INFO     [00000924] RELD tag=08 60000000600000006000000060000000 3of4
+  7401.00ns INFO     [00000925] RELD tag=08 60000000600000006000000060000000 4of4
+  7433.00ns INFO     [00000929] T0 IFETCH 00000640 tag=09 len=6 WIMG:0 reld data:935
+  7481.00ns INFO     [00000935] RELD tag=09 60000000600000006000000060000000 1of4 crit
+  7481.00ns INFO     [00000935] C0: CP 0:000574 0000000000000574
+  7489.00ns INFO     [00000936] RELD tag=09 60000000600000006000000060000000 2of4
+  7497.00ns INFO     [00000937] RELD tag=09 60000000600000006000000060000000 3of4
+  7505.00ns INFO     [00000938] RELD tag=09 60000000600000006000000060000000 4of4
+  7593.00ns INFO     [00000949] C0: CP 0:000578 1:00057C 0000000000000578
+  7697.00ns INFO     [00000962] C0: CP 0:000580 0000000000000580
+  7793.00ns INFO     [00000974] C0: CP 0:000584 0000000000000584
+  7801.00ns INFO     [00000975] T0 IFETCH 00000700 tag=08 len=6 WIMG:0 reld data:981
+  7849.00ns INFO     [00000981] RELD tag=08 48000000480000FC6000000060000000 1of4 crit
+  7857.00ns INFO     [00000982] RELD tag=08 60000000600000006000000060000000 2of4
+  7857.00ns INFO     [00000982] C0: CP 0:000588 1:00058C 0000000000000588
+  7865.00ns INFO     [00000983] RELD tag=08 60000000600000006000000060000000 3of4
+  7873.00ns INFO     [00000984] RELD tag=08 60000000600000006000000060000000 4of4
+  7905.00ns INFO     [00000988] T0 IFETCH 00000740 tag=09 len=6 WIMG:0 reld data:994
+  7953.00ns INFO     [00000994] RELD tag=09 60000000600000006000000060000000 1of4 crit
+  7961.00ns INFO     [00000995] RELD tag=09 60000000600000006000000060000000 2of4
+  7969.00ns INFO     [00000996] RELD tag=09 60000000600000006000000060000000 3of4
+  7977.00ns INFO     [00000997] RELD tag=09 60000000600000006000000060000000 4of4
+  8001.00ns INFO     [00001000] ...tick...
+  8009.00ns INFO     [00001001] T0 IFETCH 100004B0 tag=08 len=6 LE WIMG:0 reld data:1007
+  8057.00ns INFO     [00001007] RELD tag=08 00000000000000000000000000000000 1of4
+  8065.00ns INFO     [00001008] RELD tag=08 00000000000000000000000000000000 2of4
+  8073.00ns INFO     [00001009] RELD tag=08 00000000000000000000000000000000 3of4
+  8081.00ns INFO     [00001010] RELD tag=08 00000000000000000000000000000000 4of4 crit
+  8113.00ns INFO     [00001014] T0 IFETCH 100004C0 tag=09 len=6 LE WIMG:0 reld data:1020
+  8161.00ns INFO     [00001020] RELD tag=09 00000000000000000000000000000000 1of4 crit
+  8169.00ns INFO     [00001021] RELD tag=09 00000000000000000000000000000000 2of4
+  8177.00ns INFO     [00001022] RELD tag=09 00000000000000000000000000000000 3of4
+  8185.00ns INFO     [00001023] RELD tag=09 00000000000000000000000000000000 4of4
+  8257.00ns INFO     [00001032] T0 IFETCH 000000E0 tag=08 len=6 WIMG:0 reld data:1038
+  8257.00ns INFO     Test stopped by this forked coroutine
+  8257.00ns INFO     tb failed
+                     Traceback (most recent call last):
+                       File "/home/wtf/projects/a2o-opf/dev/sim/coco/A2L2.py", line 405, in A2L2Monitor
+                         assert False, (f'{me}: Bad IFetch @={ra:08X}')  #wtf want this to end back in main code for summary
+                     AssertionError: A2L2 Monitor: Bad IFetch @=000000E0
+  8257.00ns INFO     **************************************************************************************
+                     ** TEST                          STATUS  SIM TIME (ns)  REAL TIME (s)  RATIO (ns/s) **
+                     **************************************************************************************
+                     ** tb.tb                          FAIL        8257.00         154.07         53.59  **
+                     **************************************************************************************
+                     ** TESTS=0 PASS=0 FAIL=1 SKIP=0               8257.00         154.09         53.58  **
+                     **************************************************************************************
+
+
+```
+
+## Verilator (can't build with coco so far)
+
+
+* build and run a few hardcoded ops
+
+```
+verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1  -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims c.v tb.cpp
+make -C obj_dir -f Vc.mk Vc
+obj_dir/Vc
+Tracing enabled.
+00000001Resetting...
+00000001Thread stop=3
+00000011Releasing reset.
+00000201Thread stop=0
+00000213 ac_an_req: T0 ra=FFFFFFF0
+00000216 an_ac_rsp: data=00000000000000000000000048000002
+00000236 ac_an_req: T0 ra=00000000
+00000239 an_ac_rsp: data=48000400000000000000000000000000
+00000251 ac_an_req: T0 ra=00000400
+00000254 an_ac_rsp: data=382000017C366BA67C366BA67C3E6AA6
+00000263 ac_an_req: T0 ra=00000410
+00000266 an_ac_rsp: data=4C00012C2C0100003820066041820008
+00000275 ac_an_req: T0 ra=00000420
+00000278 an_ac_rsp: data=382101007C2903A64E80042000000000
+00000287 ac_an_req: T0 ra=00000430
+00000290 an_ac_rsp: data=00000000000000000000000000000000
+00000299 ac_an_req: T0 ra=00000440
+00000302 an_ac_rsp: data=00000000000000000000000000000000
+00000311 ac_an_req: T0 ra=00000450
+00000314 an_ac_rsp: data=00000000000000000000000000000000
+00000319 ac_an_req: T0 ra=00000410
+00000322 an_ac_rsp: data=4C00012C2C0100003820066041820008
+00000331 ac_an_req: T0 ra=00000420
+00000334 an_ac_rsp: data=382101007C2903A64E80042000000000
+00000344 ac_an_req: T0 ra=00000420
+00000347 an_ac_rsp: data=382101007C2903A64E80042000000000
+00000356 ac_an_req: T0 ra=00000430
+00000359 an_ac_rsp: data=00000000000000000000000000000000
+00000369 ac_an_req: T0 ra=00000660
+00000372 an_ac_rsp: data=48000040000000000000000000000000
+00000384 ac_an_req: T0 ra=000006A0
+00000387 an_ac_rsp: data=48000040000000000000000000000000
+00000399 ac_an_req: T0 ra=000006E0
+00000402 an_ac_rsp: data=48000040000000000000000000000000
+00000414 ac_an_req: T0 ra=00000720
+00000417 an_ac_rsp: data=48000040000000000000000000000000
+00000429 ac_an_req: T0 ra=00000760
+00000432 an_ac_rsp: data=48000040000000000000000000000000
+00000444 ac_an_req: T0 ra=000007A0
+00000447 an_ac_rsp: data=48000040000000000000000000000000
+00000459 ac_an_req: T0 ra=000007E0
+00000462 an_ac_rsp: data=48000040000000000000000000000000
+00000474 ac_an_req: T0 ra=00000820
+...
+```

dev/src/asm/boot.bin.hex

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dev/src/asm/boot.d

@@ -0,0 +1,3 @@
+
+boot:     file format elf32-powerpc
+

dev/src/asm/boot.lst

@@ -0,0 +1,913 @@
+   1              	# © IBM Corp. 2020
+   2              	# Licensed under and subject to the terms of the CC-BY 4.0
+   3              	# license (https://creativecommons.org/licenses/by/4.0/legalcode).
+   4              	# Additional rights, including the right to physically implement a softcore
+   5              	# that is compliant with the required sections of the Power ISA
+   6              	# Specification, will be available at no cost via the OpenPOWER Foundation.
+   7              	# This README will be updated with additional information when OpenPOWER's
+   8              	# license is available.
+   9              	
+  10              	# boot kernel
+  11              	#  set up translations
+  12              	#  set up timer facilities
+  13              	#  set up threads
+  14              	#  call user code
+  15              	#  process user rc
+  16              	
+  17              	# todo:
+  18              	# 1. skip_printf_init flag should be threaded
+  19              	
+  20              	.include "defines.s"
+   1              	# © IBM Corp. 2020
+   2              	# Licensed under and subject to the terms of the CC-BY 4.0
+   3              	# license (https://creativecommons.org/licenses/by/4.0/legalcode). 
+   4              	# Additional rights, including the right to physically implement a softcore 
+   5              	# that is compliant with the required sections of the Power ISA 
+   6              	# Specification, will be available at no cost via the OpenPOWER Foundation. 
+   7              	# This README will be updated with additional information when OpenPOWER's 
+   8              	# license is available.
+   9              	
+  10              	#-----------------------------------------
+  11              	# Defines
+  12              	#-----------------------------------------
+  13              	
+  14              	# Regs
+  15              	
+  16              	.set    r0,  0
+  17              	.set    r1,  1
+  18              	.set    r2,  2
+  19              	.set    r3,  3
+  20              	.set    r4,  4
+  21              	.set    r5,  5
+  22              	.set    r6,  6
+  23              	.set    r7,  7
+  24              	.set    r8,  8
+  25              	.set    r9,  9
+  26              	.set    r10,10
+  27              	.set    r11,11
+  28              	.set    r12,12
+  29              	.set    r13,13
+  30              	.set    r14,14
+  31              	.set    r15,15
+  32              	.set    r16,16
+  33              	.set    r17,17
+  34              	.set    r18,18
+  35              	.set    r19,19
+  36              	.set    r20,20
+  37              	.set    r21,21
+  38              	.set    r22,22
+  39              	.set    r23,23
+  40              	.set    r24,24
+  41              	.set    r25,25
+  42              	.set    r26,26
+  43              	.set    r27,27
+  44              	.set    r28,28
+  45              	.set    r29,29
+  46              	.set    r30,30
+  47              	.set    r31,31
+  48              	
+  49              	.set    f0,  0
+  50              	.set    f1,  1
+  51              	.set    f2,  2
+  52              	.set    f3,  3
+  53              	.set    f4,  4
+  54              	.set    f5,  5
+  55              	.set    f6,  6
+  56              	.set    f7,  7
+  57              	.set    f8,  8
+  58              	.set    f9,  9
+  59              	.set    f10,10
+  60              	.set    f11,11
+  61              	.set    f12,12
+  62              	.set    f13,13
+  63              	.set    f14,14
+  64              	.set    f15,15
+  65              	.set    f16,16
+  66              	.set    f17,17
+  67              	.set    f18,18
+  68              	.set    f19,19
+  69              	.set    f20,20
+  70              	.set    f21,21
+  71              	.set    f22,22
+  72              	.set    f23,23
+  73              	.set    f24,24
+  74              	.set    f25,25
+  75              	.set    f26,26
+  76              	.set    f27,27
+  77              	.set    f28,28
+  78              	.set    f29,29
+  79              	.set    f30,30
+  80              	.set    f31,31
+  81              	
+  82              	.set    cr0, 0
+  83              	.set    cr1, 1
+  84              	.set    cr2, 2
+  85              	.set    cr3, 3
+  86              	.set    cr4, 4
+  87              	.set    cr5, 5
+  88              	.set    cr6, 6
+  89              	.set    cr7, 7
+  90              	
+  91              	# SPR numbers
+  92              	
+  93              	.set    srr0, 26
+  94              	.set    srr1, 27
+  95              	.set    epcr, 307
+  96              	.set    tar, 815
+  97              	
+  98              	.set    dbsr, 304
+  99              	.set    dbcr0, 308
+ 100              	.set    dbcr1, 309
+ 101              	.set    dbcr2, 310
+ 102              	.set    dbcr3, 848
+ 103              	
+ 104              	.set    ivpr, 63
+ 105              	
+ 106              	.set    iucr0, 1011
+ 107              	.set    iucr1, 883
+ 108              	.set    iucr2, 884
+ 109              	
+ 110              	.set    iudbg0, 888
+ 111              	.set    iudbg1, 889
+ 112              	.set    iudbg2, 890
+ 113              	.set    iulfsr, 891
+ 114              	.set    iullcr, 892
+ 115              	
+ 116              	.set    mmucr0, 1020
+ 117              	.set    mmucr1, 1021
+ 118              	.set    mmucr2, 1022
+ 119              	.set    mmucr3, 1023
+ 120              	
+ 121              	.set    tb, 268
+ 122              	.set    tbl, 284
+ 123              	.set    tbh, 285
+ 124              	
+ 125              	.set    dec, 22
+ 126              	.set    udec, 550
+ 127              	.set    tsr, 336
+ 128              	.set    tcr, 340
+ 129              	
+ 130              	.set    xucr0, 1014
+ 131              	.set    xucr1, 851
+ 132              	.set    xucr2, 1016
+ 133              	.set    xucr3, 852
+ 134              	.set    xucr4, 853
+ 135              	
+ 136              	.set    tens, 438
+ 137              	.set    tenc, 439
+ 138              	.set    tensr, 437
+ 139              	
+ 140              	.set    pid, 48
+ 141              	.set    pir, 286
+ 142              	.set    pvr, 287
+ 143              	.set    tir, 446
+ 144              	
+  21              	
+  22              	.section .text
+  23              	start:
+  24              	
+  25              	int_000:
+  26 0000 48000400 	      b         boot_start
+  27              	
+  28              	# critical input
+  29 0004 4800001C 	.align 5
+  29      60000000 
+  29      60000000 
+  29      60000000 
+  29      60000000 
+  30              	int_020:
+  31 0020 48000000 	      b         .
+  32              	
+  33              	# debug
+  34 0024 4800001C 	.align 5
+  34      60000000 
+  34      60000000 
+  34      60000000 
+  34      60000000 
+  35              	int_040:
+  36 0040 48000000 	      b         .
+  37              	
+  38              	# dsi
+  39 0044 4800001C 	.align 5
+  39      60000000 
+  39      60000000 
+  39      60000000 
+  39      60000000 
+  40              	int_060:
+  41 0060 48000000 	      b         .
+  42              	
+  43              	# isi
+  44 0064 4800001C 	.align 5
+  44      60000000 
+  44      60000000 
+  44      60000000 
+  44      60000000 
+  45              	int_080:
+  46 0080 48000000 	      b         .
+  47              	
+  48              	# external
+  49 0084 4800001C 	.align 5
+  49      60000000 
+  49      60000000 
+  49      60000000 
+  49      60000000 
+  50              	int_0A0:
+  51 00a0 48000000 	      b         .