- __LPC Peripheral__ : This is an LPC peripheral that implements LPC IO and FW cycles so that it can boot a host like a POWER9. This peripheral would typically sit inside a BMC SoC.
- __LPC Peripheral__ : This is an LPC peripheral that implements LPC IO and FW cycles so that it can boot a host like a POWER9. This peripheral would typically sit inside a BMC SoC.
- __AC922 Interposer DC-SCM v1.0__ : The purpose of this design is to enable the AC922 to accept a DC-SCM v1.0 hardware management module. This enables AC922 as a development platform for DC-SCM development and test.
- __A2O Core__ : The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue
- __Microwatt__ : A tiny Open POWER ISA softcore written in VHDL 2008
https://git.openpower.foundation/cores/a2o
https://git.openpower.foundation/cores/microwatt
https://github.com/antonblanchard/microwatt
https://gitlab.com/openpowerfoundation/microwatt
- __A2O Core__ : The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue
https://git.openpower.foundation/cores/a2o
https://github.com/OpenPOWERFoundation/a2p
- __A2I Core__ : The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
- __A2I Core__ : The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
https://git.openpower.foundation/cores/a2i
https://git.openpower.foundation/cores/a2i
- A2P Core :
- __A2P Core__ : An experimental small core based on VexRiscv, written in Scala
