microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Paul Mackerras 9646fe28b0 Do sign-extension instructions in writeback instead of execute1 This makes the exts[bhw] instructions do the sign extension in the writeback stage using the sign-extension logic there instead of having unique sign extension logic in execute1. This requires passing the data length and sign extend flag from decode2 down through execute1 and execute2 and into writeback. As a side bonus we reduce the number of values in insn_type_t by two. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		5 years ago
fpga	Fix clk_gen_bypass	5 years ago
hello_world	…
media	Add title image	5 years ago
scripts	…
sim-unisim	…
tests	…
.gitignore	Update gitignore for new test bench build files	5 years ago
.travis.yml	…
LICENSE	…
Makefile	writeback: Do data formatting and condition recording in writeback	5 years ago
README.md	Add logo to README.md	5 years ago
cache_ram.vhdl	icache: Set associative icache	5 years ago
common.vhdl	Do sign-extension instructions in writeback instead of execute1	5 years ago
control.vhdl	Add CR hazard detection	5 years ago
core.vhdl	divider: Return 0 for invalid and overflow cases, like P9 does	5 years ago
core_debug.vhdl	fetch/icache: Fit icache in BRAM	5 years ago
core_tb.vhdl	…
countzero.vhdl	countzero: Reorganize to have fewer levels of logic and fewer LUTs	5 years ago
countzero_tb.vhdl	countzero: Add a testbench	5 years ago
cr_file.vhdl	…
cr_hazard.vhdl	Add CR hazard detection	5 years ago
crhelpers.vhdl	…
decode1.vhdl	Do sign-extension instructions in writeback instead of execute1	5 years ago
decode2.vhdl	Do sign-extension instructions in writeback instead of execute1	5 years ago
decode_types.vhdl	Do sign-extension instructions in writeback instead of execute1	5 years ago
divider.vhdl	writeback: Do data formatting and condition recording in writeback	5 years ago
divider_tb.vhdl	writeback: Do data formatting and condition recording in writeback	5 years ago
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	…
execute1.vhdl	Do sign-extension instructions in writeback instead of execute1	5 years ago
execute2.vhdl	Do sign-extension instructions in writeback instead of execute1	5 years ago
fetch1.vhdl	fetch/icache: Fit icache in BRAM	5 years ago
fetch2.vhdl	fetch2: Remove blank line	5 years ago
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
gpr_hazard.vhdl	Add GPR hazard detection	5 years ago
helpers.vhdl	…
icache.vhdl	icache: Set associative icache	5 years ago
icache_tb.vhdl	icache: Use narrower block RAMs	5 years ago
insn_helpers.vhdl	…
loadstore1.vhdl	…
loadstore2.vhdl	writeback: Do data formatting and condition recording in writeback	5 years ago
logical.vhdl	Consolidate logical instructions	5 years ago
microwatt.core	Add CR hazard detection	5 years ago
multiply.vhdl	writeback: Do data formatting and condition recording in writeback	5 years ago
multiply_tb.vhdl	writeback: Do data formatting and condition recording in writeback	5 years ago
plru.vhdl	icache: Set associative icache	5 years ago
plru_tb.vhdl	plru: Add a simple PLRU module	5 years ago
ppc_fx_insns.vhdl	…
register_file.vhdl	Fix register file size (there are 32 gprs).	5 years ago
rotator.vhdl	…
rotator_tb.vhdl	…
sim_console.vhdl	…
sim_console_c.c	…
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	…
sim_uart.vhdl	…
simple_ram_behavioural.vhdl	…
simple_ram_behavioural_helpers.vhdl	…
simple_ram_behavioural_helpers_c.c	…
simple_ram_behavioural_tb.bin	…
simple_ram_behavioural_tb.vhdl	…
soc.vhdl	Tighten UART address	5 years ago
wishbone_arbiter.vhdl	…
wishbone_debug_master.vhdl	…
wishbone_types.vhdl	…
writeback.vhdl	Do sign-extension instructions in writeback instead of execute1	5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com

git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):

fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)