microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Benjamin Herrenschmidt 48f260761b writeback: Slightly improve timing The CR update currently depends on the complete data formatting mux chain. This makes it source its inputs from a bit earlier in the chian, thus improving timing a bit Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
fpga	fpga/bram: Generate stall signal	5 years ago
hello_world	…
media	…
scripts	icache_tb: Improve test and include test file	5 years ago
sim-unisim	…
tests	…
.gitignore	…
.travis.yml	…
LICENSE	…
Makefile	dcache: Add testbench	5 years ago
README.md	Minor tweaks to README.md	5 years ago
cache_ram.vhdl	dcache: Introduce an extra cycle latency to make timing	5 years ago
common.vhdl	dcache: Add a dcache	5 years ago
control.vhdl	Add CR hazard detection	5 years ago
core.vhdl	Merge pull request #113 from mikey/exec-sim-remove	5 years ago
core_debug.vhdl	…
core_tb.vhdl	…
countzero.vhdl	countzero: Reorganize to have fewer levels of logic and fewer LUTs	5 years ago
countzero_tb.vhdl	countzero: Add a testbench	5 years ago
cr_file.vhdl	…
cr_hazard.vhdl	Add CR hazard detection	5 years ago
crhelpers.vhdl	crhelpers: Constraint "crnum" integer	5 years ago
dcache.vhdl	dcache: Add wishbone pipelining support	5 years ago
dcache_tb.vhdl	dcache: Add testbench	5 years ago
decode1.vhdl	insn: Simplistic implementation of icbi	5 years ago
decode2.vhdl	Do sign-extension instructions in writeback instead of execute1	5 years ago
decode_types.vhdl	Merge pull request #105 from paulusmack/writeback	5 years ago
divider.vhdl	writeback: Do data formatting and condition recording in writeback	5 years ago
divider_tb.vhdl	writeback: Do data formatting and condition recording in writeback	5 years ago
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	…
execute1.vhdl	Merge pull request #113 from mikey/exec-sim-remove	5 years ago
fetch1.vhdl	…
fetch2.vhdl	…
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
gpr_hazard.vhdl	Add GPR hazard detection	5 years ago
helpers.vhdl	…
icache.vhdl	icache: Add wishbone pipelining support	5 years ago
icache_tb.vhdl	icache_tb: Initialize stop_mark	5 years ago
icache_test.bin	icache_tb: Improve test and include test file	5 years ago
insn_helpers.vhdl	…
loadstore1.vhdl	dcache: Add a dcache	5 years ago
logical.vhdl	…
microwatt.core	dcache: Add a dcache	5 years ago
multiply.vhdl	writeback: Do data formatting and condition recording in writeback	5 years ago
multiply_tb.vhdl	writeback: Do data formatting and condition recording in writeback	5 years ago
plru.vhdl	plru: Improve sensitivity list	5 years ago
plru_tb.vhdl	…
ppc_fx_insns.vhdl	…
register_file.vhdl	…
rotator.vhdl	…
rotator_tb.vhdl	…
sim_console.vhdl	…
sim_console_c.c	…
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	…
sim_uart.vhdl	…
simple_ram_behavioural.vhdl	simple_ram: Turn on pipelining	5 years ago
simple_ram_behavioural_helpers.vhdl	…
simple_ram_behavioural_helpers_c.c	…
simple_ram_behavioural_tb.bin	…
simple_ram_behavioural_tb.vhdl	Make it possible to change wishbone address size	5 years ago
soc.vhdl	intercon: Generate stall signals for non-pipelined slaves	5 years ago
wishbone_arbiter.vhdl	wb_arbiter: Forward stall signals	5 years ago
wishbone_debug_master.vhdl	wb_debug: Add wishbone pipelining support	5 years ago
wishbone_types.vhdl	wishbone: Add stall signal	5 years ago
writeback.vhdl	writeback: Slightly improve timing	5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com

git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)