Merge pull request #353 from tianrui-wei/master

fix: fix icache_tb not finishing correctly
Merge pull request #373 from antonblanchard/icache-insn-u-state
77 changed files with 41931 additions and 43904 deletions
--- a/.github/workflows/test.yml
+++ b/.github/workflows/test.yml
@ -72,7 +72,7 @@ jobs:
      fail-fast: false
      max-parallel: 2
      matrix:
-        task: [ ECP5-EVN, ORANGE-CRAB ]
+        task: [ ECP5-EVN, ORANGE-CRAB, ORANGE-CRAB-0.21 ]
    runs-on: ubuntu-latest
    env:
      DOCKER: 1
--- a/75
+++ b/75
@ -6,13 +6,17 @@ VERILATOR_FLAGS=-O3 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
 # It takes forever to build with optimisation, so disable by default
 #VERILATOR_CFLAGS=-O3

-GHDLSYNTH ?= ghdl.so
+# some yosys builds have ghdl plugin built in, otherwise need "-m ghdl"
+GHDLSYNTH ?= $(shell ($(YOSYS) -H | grep -q ghdl) || echo -m ghdl)
 YOSYS     ?= yosys
 NEXTPNR   ?= nextpnr-ecp5
 ECPPACK   ?= ecppack
+ECPPROG   ?= ecpprog
 OPENOCD   ?= openocd
 VUNITRUN  ?= python3 ./run.py
 VERILATOR ?= verilator
+DFUUTIL   ?= dfu-util
+DFUSUFFIX ?= dfu-suffix

 # We need a version of GHDL built with either the LLVM or gcc backend.
 # Fedora provides this, but other distros may not. Another option is to use
@ -35,7 +39,7 @@ PWD = $(shell pwd)
 DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
 GHDL      = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
 CC        = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
-GHDLSYNTH = ghdl
+GHDLSYNTH = -m ghdl
 YOSYS     = $(DOCKERBIN) $(DOCKERARGS) hdlc/ghdl:yosys yosys
 NEXTPNR   = $(DOCKERBIN) $(DOCKERARGS) hdlc/nextpnr:ecp5 nextpnr-ecp5
 ECPPACK   = $(DOCKERBIN) $(DOCKERARGS) hdlc/prjtrellis ecppack
@ -56,7 +60,7 @@ core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
 	decode1.vhdl helpers.vhdl insn_helpers.vhdl \
 	control.vhdl decode2.vhdl register_file.vhdl \
 	cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
-	logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
+	logical.vhdl countbits.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
 	loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
 	core.vhdl fpu.vhdl pmu.vhdl

@ -148,13 +152,18 @@ RAM_INIT_FILE ?=hello_world/hello_world.hex
 #MEMORY_SIZE=393216
 #RAM_INIT_FILE=micropython/firmware.hex

-FPGA_TARGET ?= ORANGE-CRAB
+FPGA_TARGET ?= ORANGE-CRAB-0.21

 # FIXME: icache RAMs aren't being inferrenced as block RAMs on ECP5
 # with yosys, so make it smaller for now as a workaround.
 ICACHE_NUM_LINES=4

-# OrangeCrab with ECP85
+clkgen=fpga/clk_gen_ecp5.vhd
+toplevel=fpga/top-generic.vhdl
+dmi_dtm=dmi_dtm_dummy.vhdl
+LITEDRAM_GHDL_ARG=
+
+# OrangeCrab with ECP85 (original v0.0 with UM5G-85 chip)
 ifeq ($(FPGA_TARGET), ORANGE-CRAB)
 RESET_LOW=true
 CLK_INPUT=48000000
@ -164,6 +173,26 @@ PACKAGE=CSFBGA285
 NEXTPNR_FLAGS=--um5g-85k --freq 48
 OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
+ECP_FLASH_OFFSET=0x80000
+endif
+
+# OrangeCrab with ECP85 (v0.21)
+ifeq ($(FPGA_TARGET), ORANGE-CRAB-0.21)
+RESET_LOW=true
+CLK_INPUT=48000000
+CLK_FREQUENCY=48000000
+LPF=constraints/orange-crab-0.2.lpf
+PACKAGE=CSFBGA285
+NEXTPNR_FLAGS=--85k --speed 8 --freq 48 --timing-allow-fail --ignore-loops
+OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
+OPENOCD_DEVICE_CONFIG=openocd/LFE5U-85F.cfg
+DFU_VENDOR=1209
+DFU_PRODUCT=5af0
+ECP_FLASH_OFFSET=0x80000
+toplevel=fpga/top-orangecrab0.2.vhdl
+litedram_target=orangecrab-85-0.2
+soc_extra_v += litesdcard/generated/lattice/litesdcard_core.v
+dmi_dtm=dmi_dtm_ecp5.vhdl
 endif

 # ECP5-EVN
@ -178,12 +207,17 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 endif

+ifneq ($(litedram_target),)
+soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \
+	litedram/generated/$(litedram_target)/litedram-initmem.vhdl
+soc_extra_v += litedram/generated/$(litedram_target)/litedram_core.v
+LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=true
+endif
+
 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
-	-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES)
+	-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES) \
+	$(LITEDRAM_GHDL_ARG)

-clkgen=fpga/clk_gen_ecp5.vhd
-toplevel=fpga/top-generic.vhdl
-dmi_dtm=dmi_dtm_dummy.vhdl

 ifeq ($(FPGA_TARGET), verilator)
 RESET_LOW=true
@ -196,13 +230,13 @@ fpga_files = fpga/soc_reset.vhdl \
 	fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
 	nonrandom.vhdl

-synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
+synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)

 microwatt.json: $(synth_files) $(RAM_INIT_FILE)
-	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -abc9 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)" $(uart_files)
+	$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)"

 microwatt.v: $(synth_files) $(RAM_INIT_FILE)
-	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
+	$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"

 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
 	$(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ -top-module toplevel
@ -213,13 +247,28 @@ microwatt_out.config: microwatt.json $(LPF)
 	mv -f $@.tmp $@

 microwatt.bit: microwatt_out.config
-	$(ECPPACK) --svf microwatt.svf $< $@
+	$(ECPPACK) --compress --freq 38.8 --svf microwatt.svf $< $@

 microwatt.svf: microwatt.bit

 prog: microwatt.svf
 	$(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"

+microwatt.dfu: microwatt.bit
+	cp $< $@.tmp
+	$(DFUSUFFIX) -v $(DFU_VENDOR) -p $(DFU_PRODUCT) -a $@.tmp
+	mv $@.tmp $@
+
+dfuprog: microwatt.dfu
+	$(DFUUTIL) -a 0 -D $<
+
+ecpprog: microwatt.bit
+	$(ECPPROG) -S $<
+
+ecpflash: microwatt.bit
+	test -n "$(ECP_FLASH_OFFSET)" || (echo Error: No ECP_FLASH_OFFSET defined for target; exit 1)
+	$(ECPPROG) -o $(ECP_FLASH_OFFSET) $<
+
 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
 tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))

--- a/README.md
+++ b/README.md
@ -103,14 +103,8 @@ sudo dnf install fusesoc

 ```
 fusesoc init
-```
-
- Create a working directory and point FuseSoC at microwatt:
-
-```
-mkdir microwatt-fusesoc
-cd microwatt-fusesoc
-fusesoc library add microwatt /path/to/microwatt/
+fusesoc fetch uart16550
+fusesoc library add microwatt /path/to/microwatt
 ```

 - Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
@ -128,6 +122,68 @@ You should then be able to see output via the serial port of the board (/dev/tty
 fusesoc run --target=nexys_video microwatt
 ```

+## Linux on Microwatt
+
+Mainline Linux supports Microwatt as of v5.14. The Arty A7 is the best tested
+platform, but it's also been tested on the OrangeCrab and ButterStick.
+
+1. Use buildroot to create a userspace
+
+   A small change is required to glibc in order to support the VMX/AltiVec-less
+   Microwatt, as float128 support is mandiatory and for this in GCC requires
+   VSX/AltiVec. This change is included in Joel's buildroot fork, along with a
+   defconfig:
+   ```
+   git clone -b microwatt https://github.com/shenki/buildroot
+   cd buildroot
+   make ppc64le_microwatt_defconfig
+   make
+   ```
+
+   The output is `output/images/rootfs.cpio`.
+
+2. Build the Linux kernel
+   ```
+   git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
+   cd linux
+   make ARCH=powerpc microwatt_defconfig
+   make ARCH=powerpc CROSS_COMPILE=powerpc64le-linux-gnu- \
+     CONFIG_INITRAMFS_SOURCE=/buildroot/output/images/rootfs.cpio -j`nproc`
+   ```
+
+   The output is `arch/powerpc/boot/dtbImage.microwatt.elf`.
+
+3. Build gateware using FuseSoC
+
+   First configure FuseSoC as above.
+   ```
+   fusesoc run --build --target=arty_a7-100 microwatt --no_bram --memory_size=0
+   ```
+
+   The output is `build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit`.
+
+4. Program the flash
+
+   This operation will overwrite the contents of your flash.
+
+   For the Arty A7 A100, set `FLASH_ADDRESS` to `0x400000` and pass `-f a100`.
+
+   For the Arty A7 A35, set `FLASH_ADDRESS` to `0x300000` and pass `-f a35`.
+   ```
+   microwatt/openocd/flash-arty -f a100 build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit
+   microwatt/openocd/flash-arty -f a100 dtbImage.microwatt.elf -t bin -a $FLASH_ADDRESS
+   ```
+
+5. Connect to the second USB TTY device exposed by the FPGA
+
+   ```
+   minicom -D /dev/ttyUSB1
+   ```
+
+   The gateware has firmware that will look at `FLASH_ADDRESS` and attempt to
+   parse an ELF there, loading it to the address specified in the ELF header
+   and jumping to it.
+
 ## Testing

 - A simple test suite containing random execution test cases and a couple of
@ -139,8 +195,5 @@ make -j$(nproc) check

 ## Issues

-This is functional, but very simple. We still have quite a lot to do:
-
- There are a few instructions still to be implemented
- Need to add caches and bypassing (in progress)
- Need to add supervisor state (in progress)
+- There are a few instructions still to be implemented:
+  - Vector/VMX/VSX
--- a/common.vhdl
+++ b/common.vhdl
@ -156,6 +156,12 @@ package common is
    constant FPSCR_NI     : integer := 63 - 61;
    constant FPSCR_RN     : integer := 63 - 63;

+    -- Real addresses
+    -- REAL_ADDR_BITS is the number of real address bits that we store
+    constant REAL_ADDR_BITS : positive := 56;
+    subtype real_addr_t is std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
+    function addr_to_real(addr: std_ulogic_vector(63 downto 0)) return real_addr_t;
+
    -- Used for tracking instruction completion and pending register writes
    constant TAG_COUNT : positive := 4;
    constant TAG_NUMBER_BITS : natural := log2(TAG_COUNT);
@ -194,7 +200,6 @@ package common is
        priv_mode : std_ulogic;
        big_endian : std_ulogic;
 	stop_mark: std_ulogic;
-        sequential: std_ulogic;
        predicted : std_ulogic;
        pred_ntaken : std_ulogic;
 	nia: std_ulogic_vector(63 downto 0);
@ -779,4 +784,9 @@ package body common is
    begin
        return tag1.valid = '1' and tag2.valid = '1' and tag1.tag = tag2.tag;
    end;
+
+    function addr_to_real(addr: std_ulogic_vector(63 downto 0)) return real_addr_t is
+    begin
+        return addr(real_addr_t'range);
+    end;
 end common;
--- a/constraints/orange-crab-0.2.lpf
+++ b/constraints/orange-crab-0.2.lpf
@ -0,0 +1,225 @@
+LOCATE COMP "ext_clk" SITE "A9";
+IOBUF PORT "ext_clk" IO_TYPE=LVCMOS33;
+
+// LOCATE COMP "ext_rst_n" SITE "J2"; // io_13
+// IOBUF PORT "ext_rst_n" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+// user_button as reset
+LOCATE COMP "ext_rst_n" SITE "J17";
+IOBUF PORT "ext_rst_n" IO_TYPE=SSTL135_I;
+
+LOCATE COMP "usb_d_p" SITE "N1";
+LOCATE COMP "usb_d_n" SITE "M2";
+LOCATE COMP "usb_pullup" SITE "N2";
+
+IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33;
+IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33;
+IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33;
+
+LOCATE COMP "led0_g" SITE "M3";
+LOCATE COMP "led0_r" SITE "K4";
+LOCATE COMP "led0_b" SITE "J3";
+
+IOBUF PORT "led0_g" IO_TYPE=LVCMOS33;
+IOBUF PORT "led0_g" IO_TYPE=LVCMOS33;
+IOBUF PORT "led0_b" IO_TYPE=LVCMOS33;
+
+// discontinuous gpio numbers, match orangecrab litex platform
+LOCATE COMP "pin_gpio_0" SITE "N17"; // tx
+LOCATE COMP "pin_gpio_1" SITE "M18"; // rx
+LOCATE COMP "pin_gpio_2" SITE "C10"; // sda
+LOCATE COMP "pin_gpio_3" SITE "C9"; // scl
+//
+LOCATE COMP "pin_gpio_5" SITE "B10"; // io_5
+LOCATE COMP "pin_gpio_6" SITE "B9"; // ...
+//
+LOCATE COMP "pin_gpio_9" SITE "C8"; //
+LOCATE COMP "pin_gpio_10" SITE "B8"; //
+LOCATE COMP "pin_gpio_11" SITE "A8"; //
+LOCATE COMP "pin_gpio_12" SITE "H2"; //
+LOCATE COMP "pin_gpio_13" SITE "J2"; // io_13
+LOCATE COMP "pin_gpio_14" SITE "N15"; // miso
+LOCATE COMP "pin_gpio_15" SITE "R17"; // sck
+LOCATE COMP "pin_gpio_16" SITE "N16"; // mosi
+
+LOCATE COMP "pin_io_a0" SITE "L4";
+LOCATE COMP "pin_io_a1" SITE "N3";
+LOCATE COMP "pin_io_a2" SITE "N4";
+LOCATE COMP "pin_io_a3" SITE "H4";
+LOCATE COMP "pin_io_a4" SITE "G4";
+LOCATE COMP "pin_io_a5" SITE "T17";
+
+IOBUF PORT "pin_gpio_0" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_1" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_2" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_3" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_5" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_6" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_9" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_10" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_11" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_12" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_13" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_14" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_15" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_gpio_16" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_io_a0" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_io_a1" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_io_a2" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_io_a3" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_io_a4" IO_TYPE=LVCMOS33;
+IOBUF PORT "pin_io_a5" IO_TYPE=LVCMOS33;
+
+LOCATE COMP "ddram_a[0]"  SITE "C4";
+LOCATE COMP "ddram_a[1]"  SITE "D2";
+LOCATE COMP "ddram_a[2]"  SITE "D3";
+LOCATE COMP "ddram_a[3]"  SITE "A3";
+LOCATE COMP "ddram_a[4]"  SITE "A4";
+LOCATE COMP "ddram_a[5]"  SITE "D4";
+LOCATE COMP "ddram_a[6]"  SITE "C3";
+LOCATE COMP "ddram_a[7]"  SITE "B2";
+LOCATE COMP "ddram_a[8]"  SITE "B1";
+LOCATE COMP "ddram_a[9]"  SITE "D1";
+LOCATE COMP "ddram_a[10]" SITE "A7";
+LOCATE COMP "ddram_a[11]" SITE "C2";
+LOCATE COMP "ddram_a[12]" SITE "B6";
+LOCATE COMP "ddram_a[13]" SITE "C1";
+LOCATE COMP "ddram_a[14]" SITE "A2";
+LOCATE COMP "ddram_a[15]" SITE "C7";
+IOBUF PORT "ddram_a[0]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[1]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[2]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[3]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[4]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[5]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[6]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[7]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[8]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[9]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+
+LOCATE COMP "ddram_ba[0]" SITE "D6";
+LOCATE COMP "ddram_ba[1]" SITE "B7";
+LOCATE COMP "ddram_ba[2]" SITE "A6";
+LOCATE COMP "ddram_cas_n" SITE "D13";
+LOCATE COMP "ddram_cs_n"  SITE "A12";
+LOCATE COMP "ddram_dm[0]" SITE "D16";
+LOCATE COMP "ddram_dm[1]" SITE "G16";
+LOCATE COMP "ddram_ras_n" SITE "C12";
+LOCATE COMP "ddram_we_n"  SITE "B12";
+IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_cs_n"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_we_n"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
+
+// from litex platform, termination disabled to reduce heat
+LOCATE COMP "ddram_dq[0]"  SITE "C17";
+LOCATE COMP "ddram_dq[1]"  SITE "D15";
+LOCATE COMP "ddram_dq[2]"  SITE "B17";
+LOCATE COMP "ddram_dq[3]"  SITE "C16";
+LOCATE COMP "ddram_dq[4]"  SITE "A15";
+LOCATE COMP "ddram_dq[5]"  SITE "B13";
+LOCATE COMP "ddram_dq[6]"  SITE "A17";
+LOCATE COMP "ddram_dq[7]"  SITE "A13";
+LOCATE COMP "ddram_dq[8]"  SITE "F17";
+LOCATE COMP "ddram_dq[9]"  SITE "F16";
+LOCATE COMP "ddram_dq[10]" SITE "G15";
+LOCATE COMP "ddram_dq[11]" SITE "F15";
+LOCATE COMP "ddram_dq[12]" SITE "J16";
+LOCATE COMP "ddram_dq[13]" SITE "C18";
+LOCATE COMP "ddram_dq[14]" SITE "H16";
+LOCATE COMP "ddram_dq[15]" SITE "F18";
+IOBUF PORT "ddram_dq[0]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[1]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[2]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[3]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[4]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[5]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[6]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[7]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[8]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[9]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
+
+LOCATE COMP "ddram_dqs_n[0]" SITE "A16";
+LOCATE COMP "ddram_dqs_n[1]" SITE "H17";
+LOCATE COMP "ddram_dqs_p[0]" SITE "B15";
+LOCATE COMP "ddram_dqs_p[1]" SITE "G18";
+IOBUF PORT "ddram_dqs_n[0]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
+IOBUF PORT "ddram_dqs_n[1]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
+IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
+IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
+
+LOCATE COMP "ddram_clk_p" SITE "J18";
+LOCATE COMP "ddram_clk_n" SITE "K18";
+IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I SLEWRATE=FAST;
+IOBUF PORT "ddram_clk_n" IO_TYPE=SSTL135D_I SLEWRATE=FAST;
+
+LOCATE COMP "ddram_cke"     SITE "D18";
+LOCATE COMP "ddram_odt"     SITE "C13";
+LOCATE COMP "ddram_reset_n" SITE "L18";
+IOBUF PORT "ddram_cke"     IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_odt"     IO_TYPE=SSTL135_I SLEWRATE=FAST;
+IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
+
+LOCATE COMP "ddram_vccio[0]" SITE "K16";
+LOCATE COMP "ddram_vccio[1]" SITE "D17";
+LOCATE COMP "ddram_vccio[2]" SITE "K15";
+LOCATE COMP "ddram_vccio[3]" SITE "K17";
+LOCATE COMP "ddram_vccio[4]" SITE "B18";
+LOCATE COMP "ddram_vccio[5]" SITE "C6";
+LOCATE COMP "ddram_gnd[0]"   SITE "L15";
+LOCATE COMP "ddram_gnd[1]"   SITE "L16";
+IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
+IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
+IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
+IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
+IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
+IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
+IOBUF PORT "ddram_gnd[0]"   IO_TYPE=SSTL135_II SLEWRATE=FAST;
+IOBUF PORT "ddram_gnd[1]"   IO_TYPE=SSTL135_II SLEWRATE=FAST;
+
+// We use USRMCLK instead for clk
+// LOCATE COMP "spi_flash_clk" SITE "U16";
+// IOBUF PORT "spi_flash_clk" IO_TYPE=LVCMOS33;
+LOCATE COMP "spi_flash_cs_n" SITE "U17";
+IOBUF PORT "spi_flash_cs_n" IO_TYPE=LVCMOS33;
+LOCATE COMP "spi_flash_mosi" SITE "U18";
+IOBUF PORT "spi_flash_mosi" IO_TYPE=LVCMOS33;
+LOCATE COMP "spi_flash_miso" SITE "T18";
+IOBUF PORT "spi_flash_miso" IO_TYPE=LVCMOS33;
+LOCATE COMP "spi_flash_wp_n" SITE "R18";
+IOBUF PORT "spi_flash_wp_n" IO_TYPE=LVCMOS33;
+LOCATE COMP "spi_flash_hold_n" SITE "N18";
+IOBUF PORT "spi_flash_hold_n" IO_TYPE=LVCMOS33;
+
+LOCATE COMP "sdcard_data[0]" SITE "J1";
+LOCATE COMP "sdcard_data[1]" SITE "K3";
+LOCATE COMP "sdcard_data[2]" SITE "L3";
+LOCATE COMP "sdcard_data[3]" SITE "M1";
+LOCATE COMP "sdcard_cmd" SITE "K2";
+LOCATE COMP "sdcard_clk" SITE "K1";
+LOCATE COMP "sdcard_cd" SITE "L1";
+
+IOBUF PORT "sdcard_data[0]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
+IOBUF PORT "sdcard_data[1]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
+IOBUF PORT "sdcard_data[2]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
+IOBUF PORT "sdcard_data[3]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
+IOBUF PORT "sdcard_cmd" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
+IOBUF PORT "sdcard_clk" IO_TYPE=LVCMOS33 SLEWRATE=FAST;
+IOBUF PORT "sdcard_cd" IO_TYPE=LVCMOS33;
--- a/control.vhdl
+++ b/control.vhdl
@ -64,8 +64,8 @@ architecture rtl of control is

    signal r_int, rin_int : reg_internal_type := reg_internal_init;

-    signal gpr_write_valid : std_ulogic := '0';
-    signal cr_write_valid  : std_ulogic := '0';
+    signal gpr_write_valid : std_ulogic;
+    signal cr_write_valid  : std_ulogic;

    type tag_register is record
        wr_gpr : std_ulogic;
@ -245,6 +245,8 @@ begin
        end if;

        if rst = '1' then
+            gpr_write_valid <= '0';
+            cr_write_valid <= '0';
            v_int := reg_internal_init;
            valid_tmp := '0';
        end if;
--- a/core.vhdl
+++ b/core.vhdl
@ -117,21 +117,20 @@ architecture behave of core is
    signal complete: instr_tag_t;
    signal terminate: std_ulogic;
    signal core_rst: std_ulogic;
-    signal icache_inv: std_ulogic;
    signal do_interrupt: std_ulogic;

    -- Delayed/Latched resets and alt_reset
-    signal rst_fetch1  : std_ulogic := '1';
-    signal rst_fetch2  : std_ulogic := '1';
-    signal rst_icache  : std_ulogic := '1';
-    signal rst_dcache  : std_ulogic := '1';
-    signal rst_dec1    : std_ulogic := '1';
-    signal rst_dec2    : std_ulogic := '1';
-    signal rst_ex1     : std_ulogic := '1';
-    signal rst_fpu     : std_ulogic := '1';
-    signal rst_ls1     : std_ulogic := '1';
-    signal rst_wback   : std_ulogic := '1';
-    signal rst_dbg     : std_ulogic := '1';
+    signal rst_fetch1  : std_ulogic;
+    signal rst_fetch2  : std_ulogic;
+    signal rst_icache  : std_ulogic;
+    signal rst_dcache  : std_ulogic;
+    signal rst_dec1    : std_ulogic;
+    signal rst_dec2    : std_ulogic;
+    signal rst_ex1     : std_ulogic;
+    signal rst_fpu     : std_ulogic;
+    signal rst_ls1     : std_ulogic;
+    signal rst_wback   : std_ulogic;
+    signal rst_dbg     : std_ulogic;
    signal alt_reset_d : std_ulogic;

    signal sim_cr_dump: std_ulogic;
--- a/core_debug.vhdl
+++ b/core_debug.vhdl
@ -154,6 +154,7 @@ begin
                stopping <= '0';
                terminated <= '0';
                log_trigger_delay <= 0;
+                gspr_index <= (others => '0');
            else
                if do_log_trigger = '1' or log_trigger_delay /= 0 then
                    if log_trigger_delay = 255 then
--- a/core_dram_tb.vhdl
+++ b/core_dram_tb.vhdl
@ -121,6 +121,7 @@ begin
            DRAM_ABITS => 24,
            DRAM_ALINES => 1,
            DRAM_DLINES => 16,
+            DRAM_CKLINES => 1,
            DRAM_PORT_WIDTH => 128,
            PAYLOAD_FILE => DRAM_INIT_FILE,
            PAYLOAD_SIZE => ROM_SIZE
--- a/countbits.vhdl
+++ b/countbits.vhdl
@ -0,0 +1,136 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.helpers.all;
+
+entity bit_counter is
+    port (
+        clk         : in std_logic;
+        rs          : in std_ulogic_vector(63 downto 0);
+        count_right : in std_ulogic;
+        do_popcnt   : in std_ulogic;
+        is_32bit    : in std_ulogic;
+        datalen     : in std_ulogic_vector(3 downto 0);
+        result      : out std_ulogic_vector(63 downto 0)
+        );
+end entity bit_counter;
+
+architecture behaviour of bit_counter is
+    -- signals for count-leading/trailing-zeroes
+    signal inp : std_ulogic_vector(63 downto 0);
+    signal inp_r : std_ulogic_vector(63 downto 0);
+    signal sum : std_ulogic_vector(64 downto 0);
+    signal sum_r : std_ulogic_vector(64 downto 0);
+    signal onehot : std_ulogic_vector(63 downto 0);
+    signal edge : std_ulogic_vector(63 downto 0);
+    signal bitnum : std_ulogic_vector(5 downto 0);
+    signal cntz : std_ulogic_vector(63 downto 0);
+
+    -- signals for popcnt
+    signal dlen_r   : std_ulogic_vector(3 downto 0);
+    signal pcnt_r   : std_ulogic;
+    subtype twobit is unsigned(1 downto 0);
+    type twobit32 is array(0 to 31) of twobit;
+    signal pc2      : twobit32;
+    subtype threebit is unsigned(2 downto 0);
+    type threebit16 is array(0 to 15) of threebit;
+    signal pc4      : threebit16;
+    subtype fourbit is unsigned(3 downto 0);
+    type fourbit8 is array(0 to 7) of fourbit;
+    signal pc8      : fourbit8;
+    signal pc8_r    : fourbit8;
+    subtype sixbit is unsigned(5 downto 0);
+    type sixbit2 is array(0 to 1) of sixbit;
+    signal pc32     : sixbit2;
+    signal popcnt   : std_ulogic_vector(63 downto 0);
+
+begin
+    countzero_r: process(clk)
+    begin
+        if rising_edge(clk) then
+            inp_r <= inp;
+            sum_r <= sum;
+        end if;
+    end process;
+
+    countzero: process(all)
+        variable bitnum_e, bitnum_o : std_ulogic_vector(5 downto 0);
+    begin
+        if is_32bit = '0' then
+            if count_right = '0' then
+                inp <= bit_reverse(rs);
+            else
+                inp <= rs;
+            end if;
+        else
+            inp(63 downto 32) <= x"FFFFFFFF";
+            if count_right = '0' then
+                inp(31 downto 0) <= bit_reverse(rs(31 downto 0));
+            else
+                inp(31 downto 0) <= rs(31 downto 0);
+            end if;
+        end if;
+
+        sum <= std_ulogic_vector(unsigned('0' & not inp) + 1);
+
+        -- The following occurs after a clock edge
+        edge <= sum_r(63 downto 0) or inp_r;
+        bitnum_e := edgelocation(edge, 6);
+        onehot <= sum_r(63 downto 0) and inp_r;
+        bitnum_o := bit_number(onehot);
+        bitnum(5 downto 2) <= bitnum_e(5 downto 2);
+        bitnum(1 downto 0) <= bitnum_o(1 downto 0);
+
+        cntz <= 57x"0" & sum_r(64) & bitnum;
+    end process;
+
+    popcnt_r: process(clk)
+    begin
+        if rising_edge(clk) then
+            for i in 0 to 7 loop
+                pc8_r(i) <= pc8(i);
+            end loop;
+            dlen_r <= datalen;
+            pcnt_r <= do_popcnt;
+        end if;
+    end process;
+
+    popcnt_a: process(all)
+    begin
+        for i in 0 to 31 loop
+            pc2(i) <= unsigned("0" & rs(i * 2 downto i * 2)) + unsigned("0" & rs(i * 2 + 1 downto i * 2 + 1));
+        end loop;
+        for i in 0 to 15 loop
+            pc4(i) <= ('0' & pc2(i * 2)) + ('0' & pc2(i * 2 + 1));
+        end loop;
+        for i in 0 to 7 loop
+            pc8(i) <= ('0' & pc4(i * 2)) + ('0' & pc4(i * 2 + 1));
+        end loop;
+
+        -- after a clock edge
+        for i in 0 to 1 loop
+            pc32(i) <= ("00" & pc8_r(i * 4)) + ("00" & pc8_r(i * 4 + 1)) +
+                       ("00" & pc8_r(i * 4 + 2)) + ("00" & pc8_r(i * 4 + 3));
+        end loop;
+        
+        popcnt <= (others => '0');
+        if dlen_r(3 downto 2) = "00" then
+            -- popcntb
+            for i in 0 to 7 loop
+                popcnt(i * 8 + 3 downto i * 8) <= std_ulogic_vector(pc8_r(i));
+            end loop;
+        elsif dlen_r(3) = '0' then
+            -- popcntw
+            for i in 0 to 1 loop
+                popcnt(i * 32 + 5 downto i * 32) <= std_ulogic_vector(pc32(i));
+            end loop;
+        else
+            popcnt(6 downto 0) <= std_ulogic_vector(('0' & pc32(0)) + ('0' & pc32(1)));
+        end if;
+    end process;
+
+    result <= cntz when pcnt_r = '0' else popcnt;
+
+end behaviour;
--- a/countbits_tb.vhdl
+++ b/countbits_tb.vhdl
@ -11,11 +11,11 @@ use work.common.all;
 library osvvm;
 use osvvm.RandomPkg.all;

-entity countzero_tb is
+entity countbits_tb is
    generic (runner_cfg : string := runner_cfg_default);
-end countzero_tb;
+end countbits_tb;

-architecture behave of countzero_tb is
+architecture behave of countbits_tb is
    constant clk_period: time := 10 ns;
    signal rs: std_ulogic_vector(63 downto 0);
    signal is_32bit, count_right: std_ulogic := '0';
@ -23,13 +23,15 @@ architecture behave of countzero_tb is
    signal clk: std_ulogic;

 begin
-    zerocounter_0: entity work.zero_counter
+    bitcounter_0: entity work.bit_counter
        port map (
            clk => clk,
            rs => rs,
            result => res,
            count_right => count_right,
-            is_32bit => is_32bit
+            is_32bit => is_32bit,
+            do_popcnt => '0',
+            datalen => "0000"
        );

    clk_process: process
--- a/countzero.vhdl
+++ b/countzero.vhdl
@ -1,60 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.helpers.all;
-
-entity zero_counter is
-    port (
-        clk         : in std_logic;
-        rs          : in std_ulogic_vector(63 downto 0);
-        count_right : in std_ulogic;
-        is_32bit    : in std_ulogic;
-        result      : out std_ulogic_vector(63 downto 0)
-        );
-end entity zero_counter;
-
-architecture behaviour of zero_counter is
-    signal inp : std_ulogic_vector(63 downto 0);
-    signal sum : std_ulogic_vector(64 downto 0);
-    signal msb_r : std_ulogic;
-    signal onehot : std_ulogic_vector(63 downto 0);
-    signal onehot_r : std_ulogic_vector(63 downto 0);
-    signal bitnum : std_ulogic_vector(5 downto 0);
-
-begin
-    countzero_r: process(clk)
-    begin
-        if rising_edge(clk) then
-            msb_r <= sum(64);
-            onehot_r <= onehot;
-        end if;
-    end process;
-
-    countzero: process(all)
-    begin
-        if is_32bit = '0' then
-            if count_right = '0' then
-                inp <= bit_reverse(rs);
-            else
-                inp <= rs;
-            end if;
-        else
-            inp(63 downto 32) <= x"FFFFFFFF";
-            if count_right = '0' then
-                inp(31 downto 0) <= bit_reverse(rs(31 downto 0));
-            else
-                inp(31 downto 0) <= rs(31 downto 0);
-            end if;
-        end if;
-
-        sum <= std_ulogic_vector(unsigned('0' & not inp) + 1);
-        onehot <= sum(63 downto 0) and inp;
-
-        -- The following occurs after a clock edge
-        bitnum <= bit_number(onehot_r);
-
-        result <= x"00000000000000" & "0" & msb_r & bitnum;
-    end process;
-end behaviour;
--- a/dcache.vhdl
+++ b/dcache.vhdl
@ -67,8 +67,6 @@ architecture rtl of dcache is

    -- Bit fields counts in the address

-    -- REAL_ADDR_BITS is the number of real address bits that we store
-    constant REAL_ADDR_BITS : positive := 56;
    -- ROW_BITS is the number of bits to select a row 
    constant ROW_BITS      : natural := log2(BRAM_ROWS);
    -- ROW_LINEBITS is the number of bits to select a row within a line
@ -289,7 +287,7 @@ architecture rtl of dcache is
        op        : op_t;
        valid     : std_ulogic;
        dcbz      : std_ulogic;
-        real_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
+        real_addr : real_addr_t;
        data      : std_ulogic_vector(63 downto 0);
        byte_sel  : std_ulogic_vector(7 downto 0);
        hit_way   : way_t;
@ -412,7 +410,7 @@ architecture rtl of dcache is
    signal tlb_hit : std_ulogic;
    signal tlb_hit_way : tlb_way_t;
    signal pte : tlb_pte_t;
-    signal ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
+    signal ra : real_addr_t;
    signal valid_ra : std_ulogic;
    signal perm_attr : perm_attr_t;
    signal rc_ok : std_ulogic;
@ -454,7 +452,7 @@ architecture rtl of dcache is
    end;

    -- Returns whether this is the last row of a line
-    function is_last_row_addr(addr: wishbone_addr_type; last: row_in_line_t) return boolean is
+    function is_last_row_wb_addr(addr: wishbone_addr_type; last: row_in_line_t) return boolean is
    begin
 	return unsigned(addr(LINE_OFF_BITS - ROW_OFF_BITS - 1 downto 0)) = last;
    end;
@ -466,7 +464,7 @@ architecture rtl of dcache is
    end;

    -- Return the address of the next row in the current cache line
-    function next_row_addr(addr: wishbone_addr_type) return std_ulogic_vector is
+    function next_row_wb_addr(addr: wishbone_addr_type) return std_ulogic_vector is
 	variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
 	variable result  : wishbone_addr_type;
    begin
@ -803,11 +801,10 @@ begin

    -- Cache tag RAM second read port, for snooping
    cache_tag_read_2 : process(clk)
-        variable addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
+        variable addr : real_addr_t;
    begin
        if rising_edge(clk) then
-            addr := (others => '0');
-            addr(snoop_in.adr'left + ROW_OFF_BITS downto ROW_OFF_BITS) := snoop_in.adr;
+            addr := addr_to_real(wb_to_addr(snoop_in.adr));
            snoop_tag_set <= cache_tags(get_index(addr));
            snoop_wrtag <= get_tag(addr);
            snoop_index <= get_index(addr);
@ -830,7 +827,7 @@ begin
        variable s_hit       : std_ulogic;
        variable s_tag       : cache_tag_t;
        variable s_pte       : tlb_pte_t;
-        variable s_ra        : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
+        variable s_ra        : real_addr_t;
        variable hit_set     : std_ulogic_vector(TLB_NUM_WAYS - 1 downto 0);
        variable hit_way_set : hit_way_set_t;
        variable rel_matches : std_ulogic_vector(TLB_NUM_WAYS - 1 downto 0);
@ -1124,7 +1121,6 @@ begin
    rams: for i in 0 to NUM_WAYS-1 generate
 	signal do_read  : std_ulogic;
 	signal rd_addr  : std_ulogic_vector(ROW_BITS-1 downto 0);
-	signal do_write : std_ulogic;
 	signal wr_addr  : std_ulogic_vector(ROW_BITS-1 downto 0);
 	signal wr_data  : std_ulogic_vector(wishbone_data_bits-1 downto 0);
 	signal wr_sel   : std_ulogic_vector(ROW_SIZE-1 downto 0);
@ -1383,7 +1379,7 @@ begin
 		-- Main state machine
 		case r1.state is
                when IDLE =>
-                    r1.wb.adr <= req.real_addr(r1.wb.adr'left + ROW_OFF_BITS downto ROW_OFF_BITS);
+                    r1.wb.adr <= addr_to_wb(req.real_addr);
                    r1.wb.sel <= req.byte_sel;
                    r1.wb.dat <= req.data;
                    r1.dcbz <= req.dcbz;
@ -1471,12 +1467,12 @@ begin
 		    -- If we are still sending requests, was one accepted ?
                    if wishbone_in.stall = '0' and r1.wb.stb = '1' then
 			-- That was the last word ? We are done sending. Clear stb.
-			if is_last_row_addr(r1.wb.adr, r1.end_row_ix) then
+			if is_last_row_wb_addr(r1.wb.adr, r1.end_row_ix) then
 			    r1.wb.stb <= '0';
 			end if;

 			-- Calculate the next row address
-			r1.wb.adr <= next_row_addr(r1.wb.adr);
+			r1.wb.adr <= next_row_wb_addr(r1.wb.adr);
 		    end if;

 		    -- Incoming acks processing
--- a/decode2.vhdl
+++ b/decode2.vhdl
@ -215,7 +215,6 @@ architecture behaviour of decode2 is
        OP_AND      => "001",           -- logical_result
        OP_OR       => "001",
        OP_XOR      => "001",
-        OP_POPCNT   => "001",
        OP_PRTY     => "001",
        OP_CMPB     => "001",
        OP_EXTS     => "001",
@ -234,7 +233,8 @@ architecture behaviour of decode2 is
        OP_DIV      => "011",
        OP_DIVE     => "011",
        OP_MOD      => "011",
-        OP_CNTZ     => "100",           -- countzero_result
+        OP_CNTZ     => "100",           -- countbits_result
+        OP_POPCNT   => "100",
        OP_MFSPR    => "101",           -- spr_result
        OP_B        => "110",           -- next_nia
        OP_BC       => "110",
--- a/divider.vhdl
+++ b/divider.vhdl
@ -42,6 +42,8 @@ begin
                quot <= (others => '0');
                running <= '0';
                count <= "0000000";
+                is_32bit <= '0';
+                overflow <= '0';
            elsif d_in.valid = '1' then
                if d_in.is_extended = '1'  then
                    dend <= '0' & d_in.dividend & x"0000000000000000";
--- a/dmi_dtm_ecp5.vhdl
+++ b/dmi_dtm_ecp5.vhdl
@ -0,0 +1,298 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.math_real.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity dmi_dtm is
+    generic(ABITS : INTEGER:=8;
+            DBITS : INTEGER:=64);
+
+    port(sys_clk   : in std_ulogic;
+         sys_reset : in std_ulogic;
+         dmi_addr  : out std_ulogic_vector(ABITS - 1 downto 0);
+         dmi_din   : in std_ulogic_vector(DBITS - 1 downto 0);
+         dmi_dout  : out std_ulogic_vector(DBITS - 1 downto 0);
+         dmi_req   : out std_ulogic;
+         dmi_wr    : out std_ulogic;
+         dmi_ack   : in std_ulogic
+--         dmi_err : in std_ulogic TODO: Add error response
+         );
+end entity dmi_dtm;
+
+architecture behaviour of dmi_dtm is
+    -- Signals coming out of the JTAGG block
+    signal jtag_reset_n : std_ulogic;
+    signal tdi        : std_ulogic;
+    signal tdo        : std_ulogic;
+    signal tck        : std_ulogic;
+    signal jce1       : std_ulogic;
+    signal jshift     : std_ulogic;
+    signal update     : std_ulogic;
+
+    -- signals to match dmi_dtb_xilinx
+    signal jtag_reset : std_ulogic;
+    signal capture    : std_ulogic;
+    signal jtag_clk   : std_ulogic;
+    signal sel        : std_ulogic;
+    signal shift      : std_ulogic;
+
+    -- delays
+    signal jce1_d     : std_ulogic;
+    constant TCK_DELAY : INTEGER := 8;
+    signal tck_d : std_ulogic_vector(TCK_DELAY+1 downto 1);
+
+    -- ** JTAG clock domain **
+
+    -- Shift register
+    signal shiftr : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
+
+    -- Latched request
+    signal request : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
+
+    -- A request is present
+    signal jtag_req : std_ulogic;
+
+    -- Synchronizer for jtag_rsp (sys clk -> jtag_clk)
+    signal dmi_ack_0 : std_ulogic;
+    signal dmi_ack_1 : std_ulogic;
+
+    -- ** sys clock domain **
+
+    -- Synchronizer for jtag_req (jtag clk -> sys clk)
+    signal jtag_req_0 : std_ulogic;
+    signal jtag_req_1 : std_ulogic;
+
+    -- ** combination signals
+    signal jtag_bsy : std_ulogic;
+    signal op_valid : std_ulogic;
+    signal rsp_op   : std_ulogic_vector(1 downto 0);
+
+    -- ** Constants **
+    constant DMI_REQ_NOP : std_ulogic_vector(1 downto 0) := "00";
+    constant DMI_REQ_RD  : std_ulogic_vector(1 downto 0) := "01";
+    constant DMI_REQ_WR  : std_ulogic_vector(1 downto 0) := "10";
+    constant DMI_RSP_OK  : std_ulogic_vector(1 downto 0) := "00";
+    constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11";
+
+    attribute ASYNC_REG : string;
+    attribute ASYNC_REG of jtag_req_0: signal is "TRUE";
+    attribute ASYNC_REG of jtag_req_1: signal is "TRUE";
+    attribute ASYNC_REG of dmi_ack_0: signal is "TRUE";
+    attribute ASYNC_REG of dmi_ack_1: signal is "TRUE";
+
+    -- ECP5 JTAGG
+    component JTAGG is
+        generic (
+            ER1 : string := "ENABLED";
+            ER2 : string := "ENABLED"
+        );
+        port(
+            JTDO1 : in std_ulogic;
+            JTDO2 : in std_ulogic;
+            JTDI : out std_ulogic;
+            JTCK : out std_ulogic;
+            JRTI1 : out std_ulogic;
+            JRTI2 : out std_ulogic;
+            JSHIFT : out std_ulogic;
+            JUPDATE : out std_ulogic;
+            JRSTN : out std_ulogic;
+            JCE1 : out std_ulogic;
+            JCE2 : out std_ulogic
+        );
+    end component;
+
+    component LUT4 is
+        generic (
+            INIT : std_logic_vector
+        );
+        port(
+          A : in STD_ULOGIC;
+          B : in STD_ULOGIC;
+          C : in STD_ULOGIC;
+          D : in STD_ULOGIC;
+          Z : out STD_ULOGIC
+        );
+    end component;
+
+begin
+
+    jtag: JTAGG
+        generic map(
+            ER2 => "DISABLED"
+        )
+        port map (
+            JTDO1 => tdo,
+            JTDO2 => '0',
+            JTDI => tdi,
+            JTCK => tck,
+            JRTI1 => open,
+            JRTI2 => open,
+            JSHIFT => jshift,
+            JUPDATE => update,
+            JRSTN => jtag_reset_n,
+            JCE1 => jce1,
+            JCE2 => open
+        );
+
+    -- JRTI1 looks like it could be connected to SEL, but
+    -- in practise JRTI1 is only high briefly, not for the duration
+    -- of the transmission. possibly mw_debug could be modified.
+    -- The ecp5 is probably the only jtag device anyway.
+    sel <= '1';
+
+    -- TDI needs to align with TCK, we use LUT delays here.
+    -- From https://github.com/enjoy-digital/litex/pull/1087
+    tck_d(1) <= tck;
+    del: for i in 1 to TCK_DELAY generate
+        attribute keep : boolean;
+        attribute keep of l: label is true;
+    begin
+        l: LUT4
+            generic map(
+                INIT => b"0000_0000_0000_0010"
+            )
+            port map (
+                A => tck_d(i),
+                B => '0', C => '0', D => '0',
+                Z => tck_d(i+1)
+            );
+    end generate;
+    jtag_clk <= tck_d(TCK_DELAY+1);
+
+    -- capture signal
+    jce1_sync : process(jtag_clk)
+    begin
+        if rising_edge(jtag_clk) then
+            jce1_d <= jce1;
+            capture <= jce1 and not jce1_d;
+        end if;
+    end process;
+
+    -- latch the shift signal, otherwise
+    -- we miss the last shift in
+    -- (maybe because we are delaying tck?)
+    shift_sync : process(jtag_clk)
+    begin
+        if (sys_reset = '1') then
+            shift <= '0';
+        elsif rising_edge(jtag_clk) then
+            shift <= jshift;
+        end if;
+    end process;
+
+    jtag_reset <= not jtag_reset_n;
+
+    -- dmi_req synchronization
+    dmi_req_sync : process(sys_clk)
+    begin
+        -- sys_reset is synchronous
+        if rising_edge(sys_clk) then
+            if (sys_reset = '1') then
+                jtag_req_0 <= '0';
+                jtag_req_1 <= '0';
+            else
+                jtag_req_0 <= jtag_req;
+                jtag_req_1 <= jtag_req_0;
+            end if;
+        end if;
+    end process;
+    dmi_req <= jtag_req_1;
+
+    -- dmi_ack synchronization
+    dmi_ack_sync: process(jtag_clk, jtag_reset)
+    begin
+        -- jtag_reset is async (see comments)
+        if jtag_reset = '1' then
+            dmi_ack_0 <= '0';
+            dmi_ack_1 <= '0';
+        elsif rising_edge(jtag_clk) then
+            dmi_ack_0 <= dmi_ack;
+            dmi_ack_1 <= dmi_ack_0;
+        end if;
+    end process;
+   
+    -- jtag_bsy indicates whether we can start a new request, we can when
+    -- we aren't already processing one (jtag_req) and the synchronized ack
+    -- of the previous one is 0.
+    --
+    jtag_bsy <= jtag_req or dmi_ack_1;
+
+    -- decode request type in shift register
+    with shiftr(1 downto 0) select op_valid <=
+        '1' when DMI_REQ_RD,
+        '1' when DMI_REQ_WR,
+        '0' when others;
+
+    -- encode response op
+    rsp_op <= DMI_RSP_BSY when jtag_bsy = '1' else DMI_RSP_OK;
+
+    -- Some DMI out signals are directly driven from the request register
+    dmi_addr <= request(ABITS + DBITS + 1 downto DBITS + 2);
+    dmi_dout <= request(DBITS + 1 downto 2);
+    dmi_wr   <= '1' when request(1 downto 0) = DMI_REQ_WR else '0';
+
+    -- TDO is wired to shift register bit 0
+    tdo <= shiftr(0);
+
+    -- Main state machine. Handles shift registers, request latch and
+    -- jtag_req latch. Could be split into 3 processes but it's probably
+    -- not worthwhile.
+    --
+    shifter: process(jtag_clk, jtag_reset, sys_reset)
+    begin
+        if jtag_reset = '1' or sys_reset = '1' then
+            shiftr <= (others => '0');
+            jtag_req <= '0';
+            request <= (others => '0');
+        elsif rising_edge(jtag_clk) then
+
+            -- Handle jtag "commands" when sel is 1
+            if sel = '1' then
+                -- Shift state, rotate the register
+                if shift = '1' then
+                    shiftr <= tdi & shiftr(ABITS + DBITS + 1 downto 1);
+                end if;
+
+                -- Update state (trigger)
+                --
+                -- Latch the request if we aren't already processing one and
+                -- it has a valid command opcode.
+                --
+                    if update = '1' and op_valid = '1' then
+                    if jtag_bsy = '0' then
+                        request <= shiftr;
+                        jtag_req <= '1';
+                    end if;
+                    -- Set the shift register "op" to "busy". This will prevent
+                    -- us from re-starting the command on the next update if
+                    -- the command completes before that.
+                    shiftr(1 downto 0) <= DMI_RSP_BSY;
+                end if;
+
+                -- Request completion.
+                --
+                -- Capture the response data for reads and clear request flag.
+                --
+                -- Note: We clear req (and thus dmi_req) here which relies on tck
+                -- ticking and sel set. This means we are stuck with dmi_req up if
+                -- the jtag interface stops. Slaves must be resilient to this.
+                --
+                if jtag_req = '1' and dmi_ack_1 = '1' then
+                    jtag_req <= '0';
+                    if request(1 downto 0) = DMI_REQ_RD then
+                        request(DBITS + 1 downto 2) <= dmi_din;
+                    end if;
+                end if;
+
+                -- Capture state, grab latch content with updated status
+                if capture = '1' then
+                    shiftr <= request(ABITS + DBITS + 1 downto 2) & rsp_op;
+                end if;
+
+            end if;
+        end if;
+    end process;
+end architecture behaviour;
+
--- a/dram_tb.vhdl
+++ b/dram_tb.vhdl
@ -44,6 +44,7 @@ begin
            DRAM_ABITS => 24,
            DRAM_ALINES => 1,
            DRAM_DLINES => 16,
+            DRAM_CKLINES => 1,
            DRAM_PORT_WIDTH => 128,
            PAYLOAD_FILE => DRAM_INIT_FILE,
            PAYLOAD_SIZE => DRAM_INIT_SIZE
--- a/execute1.vhdl
+++ b/execute1.vhdl
@ -99,21 +99,20 @@ architecture behaviour of execute1 is
    signal mshort_p : std_ulogic_vector(31 downto 0) := (others => '0');

    signal valid_in : std_ulogic;
-    signal ctrl: ctrl_t := (others => (others => '0'));
-    signal ctrl_tmp: ctrl_t := (others => (others => '0'));
+    signal ctrl: ctrl_t;
+    signal ctrl_tmp: ctrl_t;
    signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
    signal rot_sign_ext: std_ulogic;
    signal rotator_result: std_ulogic_vector(63 downto 0);
    signal rotator_carry: std_ulogic;
    signal logical_result: std_ulogic_vector(63 downto 0);
-    signal countzero_result: std_ulogic_vector(63 downto 0);
+    signal do_popcnt: std_ulogic;
+    signal countbits_result: std_ulogic_vector(63 downto 0);
    signal alu_result: std_ulogic_vector(63 downto 0);
    signal adder_result: std_ulogic_vector(63 downto 0);
    signal misc_result: std_ulogic_vector(63 downto 0);
    signal muldiv_result: std_ulogic_vector(63 downto 0);
    signal spr_result: std_ulogic_vector(63 downto 0);
-    signal result_mux_sel: std_ulogic_vector(2 downto 0);
-    signal sub_mux_sel: std_ulogic_vector(2 downto 0);
    signal next_nia : std_ulogic_vector(63 downto 0);
    signal current: Decode2ToExecute1Type;

@ -284,13 +283,15 @@ begin
            datalen => e_in.data_len
 	    );

-    countzero_0: entity work.zero_counter
+    countbits_0: entity work.bit_counter
 	port map (
            clk => clk,
 	    rs => c_in,
 	    count_right => e_in.insn(10),
 	    is_32bit => e_in.is_32bit,
-	    result => countzero_result
+            do_popcnt => do_popcnt,
+            datalen => e_in.data_len,
+	    result => countbits_result
 	    );

    multiply_0: entity work.multiply
@ -391,7 +392,7 @@ begin
        logical_result     when "001",
        rotator_result     when "010",
        muldiv_result      when "011",
-        countzero_result   when "100",
+        countbits_result   when "100",
        spr_result         when "101",
        next_nia           when "110",
        misc_result        when others;
@ -403,6 +404,7 @@ begin
                r <= reg_type_init;
                ctrl.tb <= (others => '0');
                ctrl.dec <= (others => '0');
+                ctrl.cfar <= (others => '0');
                ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
            else
                r <= rin;
@ -813,6 +815,8 @@ begin
 	rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
        rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';

+        do_popcnt <= '1' when e_in.insn_type = OP_POPCNT else '0';
+
        illegal := '0';
        if r.intr_pending = '1' then
            v.e.srr1 := r.e.srr1;
@ -963,7 +967,7 @@ begin
            when OP_ADDG6S =>
            when OP_CMPRB =>
            when OP_CMPEQB =>
-            when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
+            when OP_AND | OP_OR | OP_XOR | OP_PRTY | OP_CMPB | OP_EXTS |
                    OP_BPERM | OP_BCD =>

 	    when OP_B =>
@ -1025,7 +1029,7 @@ begin
                end if;
                do_trace := '0';

-            when OP_CNTZ =>
+            when OP_CNTZ | OP_POPCNT =>
                v.e.valid := '0';
                v.cntz_in_progress := '1';
                v.busy := '1';
@ -1220,7 +1224,7 @@ begin
        -- valid_in = 0.  Hence they don't happen in the same cycle as any of
        -- the cases above which depend on valid_in = 1.
        if r.cntz_in_progress = '1' then
-            -- cnt[lt]z always takes two cycles
+            -- cnt[lt]z and popcnt* always take two cycles
            v.e.valid := '1';
 	elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
 	    if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
--- a/fetch1.vhdl
+++ b/fetch1.vhdl
@ -89,9 +89,8 @@ begin
                r_int.predicted_taken <= r_next_int.predicted_taken;
                r_int.pred_not_taken <= r_next_int.pred_not_taken;
                r_int.predicted_nia <= r_next_int.predicted_nia;
-                r_int.rd_is_niap4 <= r_next.sequential;
+                r_int.rd_is_niap4 <= r_next_int.rd_is_niap4;
            end if;
-            r.sequential <= r_next.sequential and advance_nia;
            -- always send the up-to-date stop mark and req
            r.stop_mark <= stop_in;
            r.req <= not rst;
@ -145,11 +144,11 @@ begin
    begin
 	v := r;
 	v_int := r_int;
-        v.sequential := '0';
        v.predicted := '0';
        v.pred_ntaken := '0';
        v_int.predicted_taken := '0';
        v_int.pred_not_taken := '0';
+        v_int.rd_is_niap4 := '0';

 	if rst = '1' then
 	    if alt_reset_in = '1' then
@ -180,7 +179,7 @@ begin
            v.nia := r_int.predicted_nia;
            v.predicted := '1';
        else
-            v.sequential := '1';
+            v_int.rd_is_niap4 := '1';
            v.pred_ntaken := r_int.pred_not_taken;
            v.nia := std_ulogic_vector(unsigned(r.nia) + 4);
            if r_int.mode_32bit = '1' then
--- a/fpga/clk_gen_ecp5.vhd
+++ b/fpga/clk_gen_ecp5.vhd
@ -82,33 +82,42 @@ architecture bypass of clock_generator is
            CLKINTFB :   out  std_logic  );
    end component;

+    signal clkos : std_ulogic;
    signal clkop : std_logic;
    signal lock : std_logic;

-    -- PLL constants based on prjtrellis example
-    constant PLL_IN : natural :=    2000000;
-    constant PLL_OUT : natural := 600000000;
+    -- PLL constants
+    -- According to the datasheet, PLL_IN needs to be between 10 and 400 MHz
+    -- PLL_OUT needs to be between 400 and 800 MHz
+    -- PLL_IN is chosen based on 12 and 48 MHz being common values
+    -- for the reference clock.
+    constant PLL_IN : natural :=   12000000;
+    constant PLL_OUT : natural := 480000000;

    -- Configration for ECP5 PLL
    constant PLL_CLKOP_DIV : natural := PLL_OUT/CLK_OUTPUT_HZ;
-    constant PLL_CLKFB_DIV : natural := CLK_OUTPUT_HZ/PLL_IN;
+    constant PLL_CLKOS_DIV : natural := 2;
+    constant PLL_CLKFB_DIV : natural := PLL_OUT/PLL_CLKOS_DIV/PLL_IN;
    constant PLL_CLKI_DIV  : natural := CLK_INPUT_HZ/PLL_IN;

 begin
    pll_clk_out <= clkop;
-    pll_locked_out <= not lock; -- FIXME: EHXPLLL lock signal active low?!?
+    pll_locked_out <= lock;

    clkgen: EHXPLLL
        generic map(
-            CLKOP_CPHASE => 11, -- FIXME: Copied from prjtrells.
            CLKOP_DIV => PLL_CLKOP_DIV,
+            CLKOS_ENABLE => "ENABLED",
+            CLKOS_DIV => PLL_CLKOS_DIV,
            CLKFB_DIV => PLL_CLKFB_DIV,
-            CLKI_DIV  => PLL_CLKI_DIV
+            CLKI_DIV  => PLL_CLKI_DIV,
+            FEEDBK_PATH => "CLKOS"
        )
        port map (
            CLKI => ext_clk,
            CLKOP => clkop,
-            CLKFB => clkop,
+            CLKOS => clkos,
+            CLKFB => clkos,
            LOCK => lock,
            RST => pll_rst_in,
            PHASESEL1 => '0',
@ -118,8 +127,8 @@ begin
            PHASELOADREG => '0',
            STDBY => '0',
            PLLWAKESYNC => '0',
-            ENCLKOP => '0',
-            ENCLKOS => '0',
+            ENCLKOP => '1',
+            ENCLKOS => '1',
            ENCLKOS2 => '0',
            ENCLKOS3 => '0'
    );
--- a/fpga/top-acorn-cle-215.vhdl
+++ b/fpga/top-acorn-cle-215.vhdl
@ -94,6 +94,10 @@ architecture behaviour of toplevel is
    signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
    signal spi_sdat_i  : std_ulogic_vector(3 downto 0);

+    -- ddram clock signals as vectors
+    signal ddram_clk_p_vec : std_logic_vector(0 downto 0);
+    signal ddram_clk_n_vec : std_logic_vector(0 downto 0);
+
    -- Fixup various memory sizes based on generics
    function get_bram_size return natural is
    begin
@ -252,6 +256,9 @@ begin
 	-- but for now, assert it's 100Mhz
 	assert CLK_FREQUENCY = 100000000;

+	ddram_clk_p_vec <= (others => ddram_clk_p);
+	ddram_clk_n_vec <= (others => ddram_clk_n);
+
 	reset_controller: entity work.soc_reset
 	    generic map(
 		RESET_LOW => false,
@ -272,6 +279,7 @@ begin
 		DRAM_ABITS => 26,
 		DRAM_ALINES => 16,
                DRAM_DLINES => 16,
+                DRAM_CKLINES => 1,
                DRAM_PORT_WIDTH => 128,
                PAYLOAD_FILE => RAM_INIT_FILE,
                PAYLOAD_SIZE => PAYLOAD_SIZE
@ -304,8 +312,8 @@ begin
 		ddram_dq	=> ddram_dq,
 		ddram_dqs_p	=> ddram_dqs_p,
 		ddram_dqs_n	=> ddram_dqs_n,
-		ddram_clk_p	=> ddram_clk_p,
-		ddram_clk_n	=> ddram_clk_n,
+		ddram_clk_p	=> ddram_clk_p_vec,
+		ddram_clk_n	=> ddram_clk_n_vec,
 		ddram_cke	=> ddram_cke,
 		ddram_odt	=> ddram_odt,
 		ddram_reset_n	=> ddram_reset_n
--- a/fpga/top-arty.vhdl
+++ b/fpga/top-arty.vhdl
@ -163,6 +163,10 @@ architecture behaviour of toplevel is
    signal gpio_out    : std_ulogic_vector(NGPIO - 1 downto 0);
    signal gpio_dir    : std_ulogic_vector(NGPIO - 1 downto 0);

+    -- ddram clock signals as vectors
+    signal ddram_clk_p_vec : std_logic_vector(0 downto 0);
+    signal ddram_clk_n_vec : std_logic_vector(0 downto 0);
+
    -- Fixup various memory sizes based on generics
    function get_bram_size return natural is
    begin
@ -382,11 +386,15 @@ begin
            end if;
        end process;

+	ddram_clk_p_vec <= (others => ddram_clk_p);
+	ddram_clk_n_vec <= (others => ddram_clk_n);
+
        dram: entity work.litedram_wrapper
            generic map(
                DRAM_ABITS => 24,
                DRAM_ALINES => 14,
                DRAM_DLINES => 16,
+                DRAM_CKLINES => 1,
                DRAM_PORT_WIDTH => 128,
                PAYLOAD_FILE => RAM_INIT_FILE,
                PAYLOAD_SIZE => PAYLOAD_SIZE
@ -419,8 +427,8 @@ begin
                ddram_dq        => ddram_dq,
                ddram_dqs_p     => ddram_dqs_p,
                ddram_dqs_n     => ddram_dqs_n,
-                ddram_clk_p     => ddram_clk_p,
-                ddram_clk_n     => ddram_clk_n,
+                ddram_clk_p     => ddram_clk_p_vec,
+                ddram_clk_n     => ddram_clk_n_vec,
                ddram_cke       => ddram_cke,
                ddram_odt       => ddram_odt,
                ddram_reset_n   => ddram_reset_n
--- a/fpga/top-genesys2.vhdl
+++ b/fpga/top-genesys2.vhdl
@ -97,6 +97,10 @@ architecture behaviour of toplevel is
    signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
    signal spi_sdat_i  : std_ulogic_vector(3 downto 0);

+    -- ddram clock signals as vectors
+    signal ddram_clk_p_vec : std_logic_vector(0 downto 0);
+    signal ddram_clk_n_vec : std_logic_vector(0 downto 0);
+
    -- Fixup various memory sizes based on generics
    function get_bram_size return natural is
    begin
@ -270,11 +274,15 @@ begin
 		rst_out => open
 		);

+	ddram_clk_p_vec <= (others => ddram_clk_p);
+	ddram_clk_n_vec <= (others => ddram_clk_n);
+
 	dram: entity work.litedram_wrapper
 	    generic map(
 		DRAM_ABITS => 25,
 		DRAM_ALINES => 15,
                DRAM_DLINES => 32,
+                DRAM_CKLINES => 1,
                DRAM_PORT_WIDTH => 256,
                PAYLOAD_FILE => RAM_INIT_FILE,
                PAYLOAD_SIZE => PAYLOAD_SIZE
@ -307,8 +315,8 @@ begin
 		ddram_dq	=> ddram_dq,
 		ddram_dqs_p	=> ddram_dqs_p,
 		ddram_dqs_n	=> ddram_dqs_n,
-		ddram_clk_p	=> ddram_clk_p,
-		ddram_clk_n	=> ddram_clk_n,
+		ddram_clk_p	=> ddram_clk_p_vec,
+		ddram_clk_n	=> ddram_clk_n_vec,
 		ddram_cke	=> ddram_cke,
 		ddram_odt	=> ddram_odt,
 		ddram_reset_n	=> ddram_reset_n
--- a/fpga/top-nexys-video.vhdl
+++ b/fpga/top-nexys-video.vhdl
@ -139,6 +139,10 @@ architecture behaviour of toplevel is
    signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
    signal spi_sdat_i  : std_ulogic_vector(3 downto 0);

+    -- ddram clock signals as vectors
+    signal ddram_clk_p_vec : std_logic_vector(0 downto 0);
+    signal ddram_clk_n_vec : std_logic_vector(0 downto 0);
+
    -- Fixup various memory sizes based on generics
    function get_bram_size return natural is
    begin
@ -330,11 +334,15 @@ begin
            end if;
        end process;

+	ddram_clk_p_vec <= (others => ddram_clk_p);
+	ddram_clk_n_vec <= (others => ddram_clk_n);
+
 	dram: entity work.litedram_wrapper
 	    generic map(
 		DRAM_ABITS => 25,
 		DRAM_ALINES => 15,
                DRAM_DLINES => 16,
+                DRAM_CKLINES => 1,
                DRAM_PORT_WIDTH => 128,
                PAYLOAD_FILE => RAM_INIT_FILE,
                PAYLOAD_SIZE => PAYLOAD_SIZE
@ -367,8 +375,8 @@ begin
 		ddram_dq	=> ddram_dq,
 		ddram_dqs_p	=> ddram_dqs_p,
 		ddram_dqs_n	=> ddram_dqs_n,
-		ddram_clk_p	=> ddram_clk_p,
-		ddram_clk_n	=> ddram_clk_n,
+		ddram_clk_p	=> ddram_clk_p_vec,
+		ddram_clk_n	=> ddram_clk_n_vec,
 		ddram_cke	=> ddram_cke,
 		ddram_odt	=> ddram_odt,
 		ddram_reset_n	=> ddram_reset_n
--- a/fpga/top-orangecrab0.2.vhdl
+++ b/fpga/top-orangecrab0.2.vhdl
@ -0,0 +1,512 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity toplevel is
+    generic (
+        MEMORY_SIZE        : integer  := 16384;
+        RAM_INIT_FILE      : string   := "firmware.hex";
+        RESET_LOW          : boolean  := true;
+        CLK_INPUT          : positive := 100000000;
+        CLK_FREQUENCY      : positive := 100000000;
+        HAS_FPU            : boolean  := true;
+        HAS_BTC            : boolean  := false;
+        USE_LITEDRAM       : boolean  := true;
+        NO_BRAM            : boolean  := true;
+        SCLK_STARTUPE2     : boolean := false;
+        SPI_FLASH_OFFSET   : integer := 4194304;
+        SPI_FLASH_DEF_CKDV : natural := 1;
+        SPI_FLASH_DEF_QUAD : boolean := true;
+        LOG_LENGTH         : natural := 0;
+        UART_IS_16550      : boolean  := true;
+        HAS_UART1          : boolean  := false;
+        USE_LITESDCARD     : boolean := true;
+        ICACHE_NUM_LINES   : natural := 64;
+        NGPIO              : natural := 0
+        );
+    port(
+        ext_clk   : in  std_ulogic;
+        ext_rst_n : in  std_ulogic;
+
+        -- UART0 signals:
+        pin_gpio_0 : out std_ulogic;
+        pin_gpio_1 : in  std_ulogic;
+
+        -- LEDs
+        led0_b  : out std_ulogic;
+        led0_g  : out std_ulogic;
+        led0_r  : out std_ulogic;
+
+        -- SPI
+        spi_flash_cs_n   : out std_ulogic;
+        spi_flash_mosi   : inout std_ulogic;
+        spi_flash_miso   : inout std_ulogic;
+        spi_flash_wp_n   : inout std_ulogic;
+        spi_flash_hold_n : inout std_ulogic;
+
+        -- SD card wires
+        sdcard_data   : inout std_ulogic_vector(3 downto 0);
+        sdcard_cmd    : inout std_ulogic;
+        sdcard_clk    : out   std_ulogic;
+        sdcard_cd     : in    std_ulogic;
+
+        -- DRAM wires
+        ddram_a       : out std_ulogic_vector(13 downto 0);
+        ddram_ba      : out std_ulogic_vector(2 downto 0);
+        ddram_ras_n   : out std_ulogic;
+        ddram_cas_n   : out std_ulogic;
+        ddram_we_n    : out std_ulogic;
+        ddram_cs_n    : out std_ulogic;
+        ddram_dm      : out std_ulogic_vector(1 downto 0);
+        ddram_dq      : inout std_ulogic_vector(15 downto 0);
+        ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
+        ddram_clk_p   : out std_ulogic_vector(0 downto 0);
+        -- only the positive differential pin is instantiated
+        --ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
+        --ddram_clk_n   : out std_ulogic_vector(0 downto 0);
+        ddram_cke     : out std_ulogic;
+        ddram_odt     : out std_ulogic;
+        ddram_reset_n : out std_ulogic;
+
+        ddram_gnd      : out std_ulogic_vector(1 downto 0);
+        ddram_vccio    : out std_ulogic_vector(5 downto 0)
+        );
+end entity toplevel;
+
+architecture behaviour of toplevel is
+
+    -- Reset signals:
+    signal soc_rst : std_ulogic;
+    signal pll_rst : std_ulogic;
+
+    -- Internal clock signals:
+    signal system_clk        : std_ulogic;
+    signal system_clk_locked : std_ulogic;
+
+    -- External IOs from the SoC
+    signal wb_ext_io_in        : wb_io_master_out;
+    signal wb_ext_io_out       : wb_io_slave_out;
+    signal wb_ext_is_dram_csr  : std_ulogic;
+    signal wb_ext_is_dram_init : std_ulogic;
+    signal wb_ext_is_sdcard    : std_ulogic;
+
+    -- DRAM main data wishbone connection
+    signal wb_dram_in          : wishbone_master_out;
+    signal wb_dram_out         : wishbone_slave_out;
+
+    -- DRAM control wishbone connection
+    signal wb_dram_ctrl_out    : wb_io_slave_out := wb_io_slave_out_init;
+
+    -- LiteSDCard connection
+    signal ext_irq_sdcard      : std_ulogic := '0';
+    signal wb_sdcard_out       : wb_io_slave_out := wb_io_slave_out_init;
+    signal wb_sddma_out        : wb_io_master_out := wb_io_master_out_init;
+    signal wb_sddma_in         : wb_io_slave_out;
+    signal wb_sddma_nr         : wb_io_master_out;
+    signal wb_sddma_ir         : wb_io_slave_out;
+    -- for conversion from non-pipelined wishbone to pipelined
+    signal wb_sddma_stb_sent   : std_ulogic;
+
+    -- Control/status
+    signal core_alt_reset : std_ulogic;
+
+    -- Status LED
+    signal led0_b_pwm : std_ulogic;
+    signal led0_r_pwm : std_ulogic;
+    signal led0_g_pwm : std_ulogic;
+
+    -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
+    signal pwm_counter  : std_ulogic_vector(8 downto 0);
+
+    -- SPI flash
+    signal spi_sck     : std_ulogic;
+    signal spi_cs_n    : std_ulogic;
+    signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
+    signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
+    signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
+
+    -- GPIO
+    signal gpio_in     : std_ulogic_vector(NGPIO - 1 downto 0);
+    signal gpio_out    : std_ulogic_vector(NGPIO - 1 downto 0);
+    signal gpio_dir    : std_ulogic_vector(NGPIO - 1 downto 0);
+
+    -- Fixup various memory sizes based on generics
+    function get_bram_size return natural is
+    begin
+        if USE_LITEDRAM and NO_BRAM then
+            return 0;
+        else
+            return MEMORY_SIZE;
+        end if;
+    end function;
+
+    function get_payload_size return natural is
+    begin
+        if USE_LITEDRAM and NO_BRAM then
+            return MEMORY_SIZE;
+        else
+            return 0;
+        end if;
+    end function;
+
+    constant BRAM_SIZE    : natural := get_bram_size;
+    constant PAYLOAD_SIZE : natural := get_payload_size;
+
+    COMPONENT USRMCLK
+        PORT(
+            USRMCLKI : IN STD_ULOGIC;
+            USRMCLKTS : IN STD_ULOGIC
+        );
+    END COMPONENT;
+    attribute syn_noprune: boolean ;
+    attribute syn_noprune of USRMCLK: component is true;
+
+begin
+
+    -- Main SoC
+    soc0: entity work.soc
+        generic map(
+            MEMORY_SIZE        => BRAM_SIZE,
+            RAM_INIT_FILE      => RAM_INIT_FILE,
+            SIM                => false,
+            CLK_FREQ           => CLK_FREQUENCY,
+            HAS_FPU            => HAS_FPU,
+            HAS_BTC            => HAS_BTC,
+            HAS_DRAM           => USE_LITEDRAM,
+            DRAM_SIZE          => 256 * 1024 * 1024,
+            DRAM_INIT_SIZE     => PAYLOAD_SIZE,
+            HAS_SPI_FLASH      => true,
+            SPI_FLASH_DLINES   => 4,
+            SPI_FLASH_OFFSET   => SPI_FLASH_OFFSET,
+            SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
+            SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
+            LOG_LENGTH         => LOG_LENGTH,
+            UART0_IS_16550     => UART_IS_16550,
+            HAS_UART1          => HAS_UART1,
+            HAS_SD_CARD        => USE_LITESDCARD,
+            ICACHE_NUM_LINES   => ICACHE_NUM_LINES,
+            HAS_SHORT_MULT     => true,
+            NGPIO              => NGPIO
+            )
+        port map (
+            -- System signals
+            system_clk        => system_clk,
+            rst               => soc_rst,
+
+            -- UART signals
+            uart0_txd         => pin_gpio_0,
+            uart0_rxd         => pin_gpio_1,
+
+	    -- UART1 signals
+	    --uart1_txd         => uart_pmod_tx,
+	    --uart1_rxd         => uart_pmod_rx,
+
+            -- SPI signals
+            spi_flash_sck     => spi_sck,
+            spi_flash_cs_n    => spi_cs_n,
+            spi_flash_sdat_o  => spi_sdat_o,
+            spi_flash_sdat_oe => spi_sdat_oe,
+            spi_flash_sdat_i  => spi_sdat_i,
+
+            -- GPIO signals
+            gpio_in           => gpio_in,
+            gpio_out          => gpio_out,
+            gpio_dir          => gpio_dir,
+
+            -- External interrupts
+            ext_irq_sdcard    => ext_irq_sdcard,
+
+            -- DRAM wishbone
+            wb_dram_in           => wb_dram_in,
+            wb_dram_out          => wb_dram_out,
+
+            -- IO wishbone
+            wb_ext_io_in         => wb_ext_io_in,
+            wb_ext_io_out        => wb_ext_io_out,
+            wb_ext_is_dram_csr   => wb_ext_is_dram_csr,
+            wb_ext_is_dram_init  => wb_ext_is_dram_init,
+            wb_ext_is_sdcard     => wb_ext_is_sdcard,
+
+            -- DMA wishbone
+            wishbone_dma_in      => wb_sddma_in,
+            wishbone_dma_out     => wb_sddma_out,
+
+            alt_reset            => core_alt_reset
+            );
+
+    -- SPI Flash
+    --
+    spi_flash_cs_n   <= spi_cs_n;
+    spi_flash_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
+    spi_flash_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
+    spi_flash_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
+    spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
+    spi_sdat_i(0)    <= spi_flash_mosi;
+    spi_sdat_i(1)    <= spi_flash_miso;
+    spi_sdat_i(2)    <= spi_flash_wp_n;
+    spi_sdat_i(3)    <= spi_flash_hold_n;
+
+    uclk: USRMCLK port map (
+        USRMCLKI => spi_sck,
+        USRMCLKTS => '0'
+        );
+
+    nodram: if not USE_LITEDRAM generate
+        signal ddram_clk_dummy : std_ulogic;
+    begin
+        reset_controller: entity work.soc_reset
+            generic map(
+                RESET_LOW => RESET_LOW
+                )
+            port map(
+                ext_clk => ext_clk,
+                pll_clk => system_clk,
+                pll_locked_in => system_clk_locked,
+                ext_rst_in => ext_rst_n,
+                pll_rst_out => pll_rst,
+                rst_out => soc_rst
+                );
+
+        clkgen: entity work.clock_generator
+            generic map(
+                CLK_INPUT_HZ => CLK_INPUT,
+                CLK_OUTPUT_HZ => CLK_FREQUENCY
+                )
+            port map(
+                ext_clk => ext_clk,
+                pll_rst_in => pll_rst,
+                pll_clk_out => system_clk,
+                pll_locked_out => system_clk_locked
+                );
+
+        led0_b_pwm <= '1';
+        led0_r_pwm <= '1';
+        led0_g_pwm <= '0';
+        core_alt_reset <= '0';
+
+    end generate;
+
+    has_dram: if USE_LITEDRAM generate
+        signal dram_init_done  : std_ulogic;
+        signal dram_init_error : std_ulogic;
+        signal dram_sys_rst    : std_ulogic;
+        signal rst_gen_rst     : std_ulogic;
+    begin
+
+        -- Eventually dig out the frequency from
+        -- litesdram generate.py sys_clk_freq
+        -- but for now, assert it's 48Mhz for orangecrab
+        assert CLK_FREQUENCY = 48000000;
+
+        reset_controller: entity work.soc_reset
+            generic map(
+                RESET_LOW => RESET_LOW,
+                PLL_RESET_BITS => 18,
+                SOC_RESET_BITS => 1
+                )
+            port map(
+                ext_clk => ext_clk,
+                pll_clk => system_clk,
+                pll_locked_in => system_clk_locked,
+                ext_rst_in => ext_rst_n,
+                pll_rst_out => pll_rst,
+                rst_out => rst_gen_rst
+                );
+
+        -- Generate SoC reset
+        soc_rst_gen: process(system_clk)
+        begin
+            if ext_rst_n = '0' then
+                soc_rst <= '1';
+            elsif rising_edge(system_clk) then
+                soc_rst <= dram_sys_rst or not system_clk_locked;
+            end if;
+        end process;
+
+        dram: entity work.litedram_wrapper
+            generic map(
+                DRAM_ABITS => 24,
+                DRAM_ALINES => 14,
+                DRAM_DLINES => 16,
+                DRAM_CKLINES => 1,
+                DRAM_PORT_WIDTH => 128,
+                NUM_LINES => 8, -- reduce from default of 64 to make smaller/timing
+                PAYLOAD_FILE => RAM_INIT_FILE,
+                PAYLOAD_SIZE => PAYLOAD_SIZE
+                )
+            port map(
+                clk_in          => ext_clk,
+                rst             => pll_rst,
+                system_clk      => system_clk,
+                system_reset    => dram_sys_rst,
+                core_alt_reset  => core_alt_reset,
+                pll_locked      => system_clk_locked,
+
+                wb_in           => wb_dram_in,
+                wb_out          => wb_dram_out,
+                wb_ctrl_in      => wb_ext_io_in,
+                wb_ctrl_out     => wb_dram_ctrl_out,
+                wb_ctrl_is_csr  => wb_ext_is_dram_csr,
+                wb_ctrl_is_init => wb_ext_is_dram_init,
+
+                init_done       => dram_init_done,
+                init_error      => dram_init_error,
+
+                ddram_a         => ddram_a,
+                ddram_ba        => ddram_ba,
+                ddram_ras_n     => ddram_ras_n,
+                ddram_cas_n     => ddram_cas_n,
+                ddram_we_n      => ddram_we_n,
+                ddram_cs_n      => ddram_cs_n,
+                ddram_dm        => ddram_dm,
+                ddram_dq        => ddram_dq,
+                ddram_dqs_p     => ddram_dqs_p,
+                ddram_clk_p     => ddram_clk_p,
+                -- only the positive differential pin is instantiated
+                --ddram_dqs_n     => ddram_dqs_n,
+                --ddram_clk_n     => ddram_clk_n,
+                ddram_cke       => ddram_cke,
+                ddram_odt       => ddram_odt,
+
+                ddram_reset_n   => ddram_reset_n
+                );
+
+        ddram_gnd <= "00";
+        -- for power consumption.
+        -- https://github.com/orangecrab-fpga/orangecrab-hardware/issues/19#issuecomment-683479378
+        ddram_vccio <= "111111";
+
+        led0_b_pwm <= not dram_init_done;
+        led0_r_pwm <= dram_init_error;
+        led0_g_pwm <= dram_init_done and not dram_init_error;
+
+    end generate;
+
+
+    -- SD card pmod
+    has_sdcard : if USE_LITESDCARD generate
+        component litesdcard_core port (
+            clk           : in    std_ulogic;
+            rst           : in    std_ulogic;
+            -- wishbone for accessing control registers
+            wb_ctrl_adr   : in    std_ulogic_vector(29 downto 0);
+            wb_ctrl_dat_w : in    std_ulogic_vector(31 downto 0);
+            wb_ctrl_dat_r : out   std_ulogic_vector(31 downto 0);
+            wb_ctrl_sel   : in    std_ulogic_vector(3 downto 0);
+            wb_ctrl_cyc   : in    std_ulogic;
+            wb_ctrl_stb   : in    std_ulogic;
+            wb_ctrl_ack   : out   std_ulogic;
+            wb_ctrl_we    : in    std_ulogic;
+            wb_ctrl_cti   : in    std_ulogic_vector(2 downto 0);
+            wb_ctrl_bte   : in    std_ulogic_vector(1 downto 0);
+            wb_ctrl_err   : out   std_ulogic;
+            -- wishbone for SD card core to use for DMA
+            wb_dma_adr    : out   std_ulogic_vector(29 downto 0);
+            wb_dma_dat_w  : out   std_ulogic_vector(31 downto 0);
+            wb_dma_dat_r  : in    std_ulogic_vector(31 downto 0);
+            wb_dma_sel    : out   std_ulogic_vector(3 downto 0);
+            wb_dma_cyc    : out   std_ulogic;
+            wb_dma_stb    : out   std_ulogic;
+            wb_dma_ack    : in    std_ulogic;
+            wb_dma_we     : out   std_ulogic;
+            wb_dma_cti    : out   std_ulogic_vector(2 downto 0);
+            wb_dma_bte    : out   std_ulogic_vector(1 downto 0);
+            wb_dma_err    : in    std_ulogic;
+            -- connections to SD card
+            sdcard_data   : inout std_ulogic_vector(3 downto 0);
+            sdcard_cmd    : inout std_ulogic;
+            sdcard_clk    : out   std_ulogic;
+            sdcard_cd     : in    std_ulogic;
+            irq           : out   std_ulogic
+            );
+        end component;
+
+        signal wb_sdcard_cyc : std_ulogic;
+        signal wb_sdcard_adr : std_ulogic_vector(29 downto 0);
+
+    begin
+        litesdcard : litesdcard_core
+            port map (
+                clk           => system_clk,
+                rst           => soc_rst,
+                wb_ctrl_adr   => wb_sdcard_adr,
+                wb_ctrl_dat_w => wb_ext_io_in.dat,
+                wb_ctrl_dat_r => wb_sdcard_out.dat,
+                wb_ctrl_sel   => wb_ext_io_in.sel,
+                wb_ctrl_cyc   => wb_sdcard_cyc,
+                wb_ctrl_stb   => wb_ext_io_in.stb,
+                wb_ctrl_ack   => wb_sdcard_out.ack,
+                wb_ctrl_we    => wb_ext_io_in.we,
+                wb_ctrl_cti   => "000",
+                wb_ctrl_bte   => "00",
+                wb_ctrl_err   => open,
+                wb_dma_adr    => wb_sddma_nr.adr,
+                wb_dma_dat_w  => wb_sddma_nr.dat,
+                wb_dma_dat_r  => wb_sddma_ir.dat,
+                wb_dma_sel    => wb_sddma_nr.sel,
+                wb_dma_cyc    => wb_sddma_nr.cyc,
+                wb_dma_stb    => wb_sddma_nr.stb,
+                wb_dma_ack    => wb_sddma_ir.ack,
+                wb_dma_we     => wb_sddma_nr.we,
+                wb_dma_cti    => open,
+                wb_dma_bte    => open,
+                wb_dma_err    => '0',
+                sdcard_data   => sdcard_data,
+                sdcard_cmd    => sdcard_cmd,
+                sdcard_clk    => sdcard_clk,
+                sdcard_cd     => sdcard_cd,
+                irq           => ext_irq_sdcard
+                );
+
+        -- Gate cyc with chip select from SoC
+        wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard;
+
+        wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0);
+
+        wb_sdcard_out.stall <= not wb_sdcard_out.ack;
+
+        -- Convert non-pipelined DMA wishbone to pipelined by suppressing
+        -- non-acknowledged strobes
+        process(system_clk)
+        begin
+            if rising_edge(system_clk) then
+                wb_sddma_out <= wb_sddma_nr;
+                if wb_sddma_stb_sent = '1' or
+                    (wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then
+                    wb_sddma_out.stb <= '0';
+                end if;
+                if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then
+                    wb_sddma_stb_sent <= '0';
+                elsif wb_sddma_in.stall = '0' then
+                    wb_sddma_stb_sent <= wb_sddma_nr.stb;
+                end if;
+                wb_sddma_ir <= wb_sddma_in;
+            end if;
+        end process;
+
+    end generate;
+
+    -- Mux WB response on the IO bus
+    wb_ext_io_out <= wb_sdcard_out when wb_ext_is_sdcard = '1' else
+                     wb_dram_ctrl_out;
+
+    leds_pwm : process(system_clk)
+    begin
+        if rising_edge(system_clk) then
+            pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1);
+            if pwm_counter(8 downto 4) = "00000" then
+                led0_b <= led0_b_pwm;
+                led0_r <= led0_r_pwm;
+                led0_g <= led0_g_pwm;
+            else
+                led0_b <= '0';
+                led0_r <= '0';
+                led0_g <= '0';
+            end if;
+        end if;
+    end process;
+
+end architecture behaviour;
--- a/fpga/top-wukong-v2.vhdl
+++ b/fpga/top-wukong-v2.vhdl
@ -139,6 +139,10 @@ architecture behaviour of toplevel is
    signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
    signal spi_sdat_i  : std_ulogic_vector(3 downto 0);

+    -- ddram clock signals as vectors
+    signal ddram_clk_p_vec : std_ulogic_vector(0 downto 0);
+    signal ddram_clk_n_vec : std_ulogic_vector(0 downto 0);
+
    -- Fixup various memory sizes based on generics
    function get_bram_size return natural is
    begin
@ -331,11 +335,15 @@ begin
            end if;
        end process;

+	ddram_clk_p_vec <= (others => ddram_clk_p);
+	ddram_clk_n_vec <= (others => ddram_clk_n);
+
        dram: entity work.litedram_wrapper
            generic map(
                DRAM_ABITS => 24,
                DRAM_ALINES => 14,
                DRAM_DLINES => 16,
+                DRAM_CKLINES => 1,
                DRAM_PORT_WIDTH => 128,
                PAYLOAD_FILE => RAM_INIT_FILE,
                PAYLOAD_SIZE => PAYLOAD_SIZE
@ -368,8 +376,8 @@ begin
                ddram_dq        => ddram_dq,
                ddram_dqs_p     => ddram_dqs_p,
                ddram_dqs_n     => ddram_dqs_n,
-                ddram_clk_p     => ddram_clk_p,
-                ddram_clk_n     => ddram_clk_n,
+                ddram_clk_p     => ddram_clk_p_vec,
+                ddram_clk_n     => ddram_clk_n_vec,
                ddram_cke       => ddram_cke,
                ddram_odt       => ddram_odt,
                ddram_reset_n   => ddram_reset_n
--- a/fpu.vhdl
+++ b/fpu.vhdl
@ -16,7 +16,7 @@ entity fpu is
        clk : in std_ulogic;
        rst : in std_ulogic;

-        e_in  : in  Execute1toFPUType;
+        e_in  : in  Execute1ToFPUType;
        e_out : out FPUToExecute1Type;

        w_out : out FPUToWritebackType
@ -197,7 +197,7 @@ architecture behaviour of fpu is
    -- Each output value is the inverse of the center of the input
    -- range for the value, i.e. entry 0 is 1 / (1 + 1/512),
    -- entry 1 is 1 / (1 + 3/512), etc.
-    signal inverse_table : lookup_table := (
+    constant inverse_table : lookup_table := (
        -- 1/x lookup table
        -- Unit bit is assumed to be 1, so input range is [1, 2)
        18x"3fc01", 18x"3f411", 18x"3ec31", 18x"3e460", 18x"3dc9f", 18x"3d4ec", 18x"3cd49", 18x"3c5b5",
@ -549,6 +549,10 @@ begin
                r.do_intr <= '0';
                r.fpscr <= (others => '0');
                r.writing_back <= '0';
+                r.dest_fpr <= (others =>'0');
+                r.cr_mask <= (others =>'0');
+                r.cr_result <= (others =>'0');
+                r.instr_tag.valid <= '0';
            else
                assert not (r.state /= IDLE and e_in.valid = '1') severity failure;
                r <= rin;
--- a/gpio.vhdl
+++ b/gpio.vhdl
@ -40,8 +40,8 @@ architecture behaviour of gpio is
    constant GPIO_REG_DATA_CLR : std_ulogic_vector(GPIO_REG_BITS-1 downto 0) := "00101";

    -- Current output value and direction
-    signal reg_data : std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
-    signal reg_dirn : std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
+    signal reg_data : std_ulogic_vector(NGPIO - 1 downto 0);
+    signal reg_dirn : std_ulogic_vector(NGPIO - 1 downto 0);
    signal reg_in1  : std_ulogic_vector(NGPIO - 1 downto 0);
    signal reg_in2  : std_ulogic_vector(NGPIO - 1 downto 0);

--- a/hello_world/head.S
+++ b/hello_world/head.S
@ -60,11 +60,25 @@ _start:

 .global boot_entry
 boot_entry:
+	LOAD_IMM64(%r10,__bss_start)
+	LOAD_IMM64(%r11,__bss_end)
+	subf	%r11,%r10,%r11
+	addi	%r11,%r11,63
+	srdi.	%r11,%r11,6
+	beq	2f
+	mtctr	%r11
+1:	dcbz	0,%r10
+	addi	%r10,%r10,64
+	bdnz	1b
+
 	/* setup stack */
-	LOAD_IMM64(%r1, STACK_TOP - 0x100)
+2:	LOAD_IMM64(%r1,__stack_top)
+	li	%r0,0
+	stdu	%r0,-32(%r1)
 	LOAD_IMM64(%r12, main)
-	mtctr	%r12,
+	mtctr	%r12
 	bctrl
+	attn // terminate on exit
 	b .

 #define EXCEPTION(nr)		\
--- a/hello_world/hello_world.bin
+++ b/hello_world/hello_world.bin
--- a/hello_world/hello_world.elf
+++ b/hello_world/hello_world.elf
--- a/hello_world/hello_world.hex
+++ b/hello_world/hello_world.hex
@ -35,24 +35,24 @@ a64b5a7d14004a39
 a602487d05009f42
 a64b5a7d14004a39
 2402004ca64b7b7d
-3c20000048000004
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-0000000000000000
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+4800000000000200
 0000000000000000
 0000000000000000
 0000000000000000
@ -510,150 +510,150 @@ a64b5a7d14004a39
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 000000004bffffd0
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 0000000000000000
 3c40000100000000
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 3929002060630002
 7c604fea7c0004ac
 000000004e800020
 0000000000000000
-0000000000000010
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-0000001800010c1b
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-000000019f7e4111
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-0000001000010c1b
-fffffc8800000018
-0000000000000084
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-0000002800000000
-fffffd6400000040
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-300e43029e019f00
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--- a/hello_world/powerpc.lds
+++ b/hello_world/powerpc.lds
@ -1,13 +1,27 @@
 SECTIONS
 {
-	_start = .;
 	. = 0;
+	_start = .;
 	.head : {
 		KEEP(*(.head))
- 	}
+	}
 	. = 0x1000;
-	.text : { *(.text) }
+	.text : { *(.text) *(.text.*) *(.rodata) *(.rodata.*) }
 	. = 0x1800;
-	.data : { *(.data) }
-	.bss : { *(.bss) }
+	.data : { *(.data) *(.data.*) *(.got) *(.toc) }
+	. = ALIGN(0x80);
+	__bss_start = .;
+	.bss : {
+		*(.dynsbss)
+		*(.sbss)
+		*(.scommon)
+		*(.dynbss)
+		*(.bss)
+		*(.common)
+		*(.bss.*)
+	}
+	. = ALIGN(0x80);
+	__bss_end = .;
+	. = . + 0x2000;
+	__stack_top = .;
 }
--- a/helpers.vhdl
+++ b/helpers.vhdl
@ -28,7 +28,9 @@ package helpers is

    function bit_reverse(a: std_ulogic_vector) return std_ulogic_vector;
    function bit_number(a: std_ulogic_vector(63 downto 0)) return std_ulogic_vector;
+    function edgelocation(v: std_ulogic_vector; nbits: natural) return std_ulogic_vector;
    function count_left_zeroes(val: std_ulogic_vector) return std_ulogic_vector;
+    function count_right_zeroes(val: std_ulogic_vector) return std_ulogic_vector;
 end package helpers;

 package body helpers is
@ -247,16 +249,50 @@ package body helpers is
        return ret;
    end;

-    -- Count leading zeroes operation
+    -- Assuming the input 'v' is a value of the form 1...10...0,
+    -- the output is the bit number of the rightmost 1 bit in v.
+    -- If v is zero, the result is zero.
+    function edgelocation(v: std_ulogic_vector; nbits: natural) return std_ulogic_vector is
+        variable p: std_ulogic_vector(nbits - 1 downto 0);
+        variable stride: natural;
+        variable b: std_ulogic;
+        variable k: natural;
+    begin
+        stride := 2;
+        for i in 0 to nbits - 1 loop
+            b := '0';
+            for j in 0 to (2**nbits / stride) - 1 loop
+                k := j * stride;
+                b := b or (v(k + stride - 1) and not v(k + (stride/2) - 1));
+            end loop;
+            p(i) := b;
+            stride := stride * 2;
+        end loop;
+        return p;
+    end function;
+
+    -- Count leading zeroes operations
    -- Assumes the value passed in is not zero (if it is, zero is returned)
-    function count_left_zeroes(val: std_ulogic_vector) return std_ulogic_vector is
-        variable rev: std_ulogic_vector(val'left downto val'right);
+    function count_right_zeroes(val: std_ulogic_vector) return std_ulogic_vector is
        variable sum: std_ulogic_vector(val'left downto val'right);
        variable onehot: std_ulogic_vector(val'left downto val'right);
+        variable edge: std_ulogic_vector(val'left downto val'right);
+        variable bn, bn_e, bn_o: std_ulogic_vector(5 downto 0);
+    begin
+        sum := std_ulogic_vector(- signed(val));
+        onehot := sum and val;
+        edge := sum or val;
+        bn_e := edgelocation(std_ulogic_vector(resize(signed(edge), 64)), 6);
+        bn_o := bit_number(std_ulogic_vector(resize(unsigned(onehot), 64)));
+        bn := bn_e(5 downto 2) & bn_o(1 downto 0);
+        return bn;
+    end;
+
+    function count_left_zeroes(val: std_ulogic_vector) return std_ulogic_vector is
+        variable rev: std_ulogic_vector(val'left downto val'right);
    begin
        rev := bit_reverse(val);
-        sum := std_ulogic_vector(- signed(rev));
-        onehot := sum and rev;
-        return bit_number(std_ulogic_vector(resize(unsigned(onehot), 64)));
+        return count_right_zeroes(rev);
    end;
+
 end package body helpers;
--- a/icache.vhdl
+++ b/icache.vhdl
@ -46,8 +46,6 @@ entity icache is
        TLB_SIZE : positive := 64;
        -- L1 ITLB log_2(page_size)
        TLB_LG_PGSZ : positive := 12;
-        -- Number of real address bits that we store
-        REAL_ADDR_BITS : positive := 56;
        -- Non-zero to enable log data collection
        LOG_LENGTH : natural := 0
        );
@ -207,14 +205,13 @@ architecture rtl of icache is
    signal req_tag     : cache_tag_t;
    signal req_is_hit  : std_ulogic;
    signal req_is_miss : std_ulogic;
-    signal req_laddr   : std_ulogic_vector(63 downto 0);
+    signal req_raddr   : real_addr_t;

    signal tlb_req_index : tlb_index_t;
-    signal real_addr     : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
+    signal real_addr     : real_addr_t;
    signal ra_valid      : std_ulogic;
    signal priv_fault    : std_ulogic;
    signal access_ok     : std_ulogic;
-    signal use_previous  : std_ulogic;

    -- Cache RAM interface
    type cache_ram_out_t is array(way_t) of cache_row_t;
@ -251,9 +248,9 @@ architecture rtl of icache is
    end;

    -- Returns whether this is the last row of a line
-    function is_last_row_addr(addr: wishbone_addr_type; last: row_in_line_t) return boolean is
+    function is_last_row_wb_addr(wb_addr: wishbone_addr_type; last: row_in_line_t) return boolean is
    begin
-	return unsigned(addr(LINE_OFF_BITS - ROW_OFF_BITS - 1 downto 0)) = last;
+	return unsigned(wb_addr(LINE_OFF_BITS - ROW_OFF_BITS - 1 downto 0)) = last;
    end;

    -- Returns whether this is the last row of a line
@ -263,15 +260,15 @@ architecture rtl of icache is
    end;

    -- Return the address of the next row in the current cache line
-    function next_row_addr(addr: wishbone_addr_type)
+    function next_row_wb_addr(wb_addr: wishbone_addr_type)
 	return std_ulogic_vector is
 	variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
 	variable result  : wishbone_addr_type;
    begin
 	-- Is there no simpler way in VHDL to generate that 3 bits adder ?
-	row_idx := addr(ROW_LINEBITS - 1 downto 0);
+	row_idx := wb_addr(ROW_LINEBITS - 1 downto 0);
 	row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
-	result := addr;
+	result := wb_addr;
 	result(ROW_LINEBITS - 1 downto 0) := row_idx;
 	return result;
    end;
@ -301,10 +298,9 @@ architecture rtl of icache is
    end;

    -- Get the tag value from the address
-    function get_tag(addr: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
-                     endian: std_ulogic) return cache_tag_t is
+    function get_tag(addr: real_addr_t; endian: std_ulogic) return cache_tag_t is
    begin
-        return endian & addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
+        return endian & addr(addr'left downto SET_SIZE_BITS);
    end;

    -- Read a tag from a tag memory row
@ -400,7 +396,7 @@ begin
                    wr_dat(ii * 8 + 7 downto ii * 8) <= wishbone_in.dat(j * 8 + 7 downto j * 8);
                end loop;
            end if;
-	    do_read <= not (stall_in or use_previous);
+	    do_read <= not stall_in;
 	    do_write <= '0';
 	    if wishbone_in.ack = '1' and replace_way = i then
 		do_write <= '1';
@ -468,7 +464,7 @@ begin
            end if;
            eaa_priv <= pte(3);
        else
-            real_addr <= i_in.nia(REAL_ADDR_BITS - 1 downto 0);
+            real_addr <= addr_to_real(i_in.nia);
            ra_valid <= '1';
            eaa_priv <= '1';
        end if;
@ -506,16 +502,6 @@ begin
 	variable is_hit  : std_ulogic;
 	variable hit_way : way_t;
    begin
-        -- i_in.sequential means that i_in.nia this cycle is 4 more than
-        -- last cycle.  If we read more than 32 bits at a time, had a cache hit
-        -- last cycle, and we don't want the first 32-bit chunk, then we can
-        -- keep the data we read last cycle and just use that.
-        if unsigned(i_in.nia(INSN_BITS+2-1 downto 2)) /= 0 then
-            use_previous <= i_in.req and i_in.sequential and r.hit_valid;
-        else
-            use_previous <= '0';
-        end if;
-
 	-- Extract line, row and tag from request
        req_index <= get_index(i_in.nia);
        req_row <= get_row(i_in.nia);
@ -524,8 +510,7 @@ begin
 	-- Calculate address of beginning of cache row, will be
 	-- used for cache miss processing if needed
 	--
-	req_laddr <= (63 downto REAL_ADDR_BITS => '0') &
-                     real_addr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS)&
+	req_raddr <= real_addr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS) &
 		     (ROW_OFF_BITS-1 downto 0 => '0');

 	-- Test if pending request is a hit on any way
@ -546,7 +531,7 @@ begin
 	end loop;

 	-- Generate the "hit" and "miss" signals for the synchronous blocks
-        if i_in.req = '1' and access_ok = '1' and flush_in = '0' and rst = '0' and use_previous = '0' then
+        if i_in.req = '1' and access_ok = '1' and flush_in = '0' and rst = '0' then
            req_is_hit  <= is_hit;
            req_is_miss <= not is_hit;
        else
@ -570,7 +555,11 @@ begin
 	--       I prefer not to do just yet as it would force fetch2 to know about
 	--       some of the cache geometry information.
 	--
-        i_out.insn <= read_insn_word(r.hit_nia, cache_out(r.hit_way));
+	if r.hit_valid = '1' then
+            i_out.insn <= read_insn_word(r.hit_nia, cache_out(r.hit_way));
+	else
+            i_out.insn <= (others => '0');
+	end if;
 	i_out.valid <= r.hit_valid;
 	i_out.nia <= r.hit_nia;
 	i_out.stop_mark <= r.hit_smark;
@ -580,7 +569,7 @@ begin
        i_out.next_pred_ntaken <= i_in.pred_ntaken;

 	-- Stall fetch1 if we have a miss on cache or TLB or a protection fault
-	stall_out <= not (is_hit and access_ok) and not use_previous;
+	stall_out <= not (is_hit and access_ok);

 	-- Wishbone requests output (from the cache miss reload machine)
 	wishbone_out <= r.wb;
@ -592,8 +581,7 @@ begin
        if rising_edge(clk) then
            -- keep outputs to fetch2 unchanged on a stall
            -- except that flush or reset sets valid to 0
-            -- If use_previous, keep the same data as last cycle and use the second half
-            if stall_in = '1' or use_previous = '1' then
+            if stall_in = '1' then
                if rst = '1' or flush_in = '1' then
                    r.hit_valid <= '0';
                end if;
@ -627,7 +615,7 @@ begin
    icache_miss : process(clk)
 	variable tagset    : cache_tags_set_t;
        variable tag       : cache_tag_t;
-        variable snoop_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
+        variable snoop_addr : real_addr_t;
        variable snoop_tag : cache_tag_t;
        variable snoop_cache_tags : cache_tags_set_t;
    begin
@ -657,8 +645,7 @@ begin
                -- Detect snooped writes and decode address into index and tag
                -- Since we never write, any write should be snooped
                snoop_valid <= wb_snoop_in.cyc and wb_snoop_in.stb and wb_snoop_in.we;
-                snoop_addr := (others => '0');
-                snoop_addr(wb_snoop_in.adr'left + ROW_OFF_BITS downto ROW_OFF_BITS) := wb_snoop_in.adr;
+                snoop_addr := addr_to_real(wb_to_addr(wb_snoop_in.adr));
                snoop_index <= get_index(snoop_addr);
                snoop_cache_tags := cache_tags(get_index(snoop_addr));
                snoop_tag := get_tag(snoop_addr, '0');
@ -709,15 +696,15 @@ begin

 			-- Keep track of our index and way for subsequent stores
 			r.store_index <= req_index;
-			r.store_row <= get_row(req_laddr);
+			r.store_row <= get_row(req_raddr);
                        r.store_tag <= req_tag;
                        r.store_valid <= '1';
-                        r.end_row_ix <= get_row_of_line(get_row(req_laddr)) - 1;
+                        r.end_row_ix <= get_row_of_line(get_row(req_raddr)) - 1;

 			-- Prep for first wishbone read. We calculate the address of
 			-- the start of the cache line and start the WB cycle.
 			--
-			r.wb.adr <= req_laddr(r.wb.adr'left + ROW_OFF_BITS downto ROW_OFF_BITS);
+			r.wb.adr <= addr_to_wb(req_raddr);
 			r.wb.cyc <= '1';
 			r.wb.stb <= '1';

@ -749,12 +736,12 @@ begin
 		    if wishbone_in.stall = '0' and r.wb.stb = '1' then
 			-- That was the last word ? We are done sending. Clear stb.
 			--
-			if is_last_row_addr(r.wb.adr, r.end_row_ix) then
+			if is_last_row_wb_addr(r.wb.adr, r.end_row_ix) then
 			    r.wb.stb <= '0';
 			end if;

 			-- Calculate the next row address
-			r.wb.adr <= next_row_addr(r.wb.adr);
+			r.wb.adr <= next_row_wb_addr(r.wb.adr);
 		    end if;

                    -- Abort reload if we get an invalidation
@ -785,7 +772,7 @@ begin
                when STOP_RELOAD =>
                    -- Wait for all outstanding requests to be satisfied, then
                    -- go to IDLE state.
-                    if get_row_of_line(r.store_row) = get_row_of_line(get_row(r.wb.adr)) then
+                    if get_row_of_line(r.store_row) = get_row_of_line(get_row(wb_to_addr(r.wb.adr))) then
                        r.wb.cyc <= '0';
                        r.state <= IDLE;
                    end if;
@ -837,4 +824,7 @@ begin
        end process;
        log_out <= log_data;
    end generate;
+
+    events <= ev;
+
 end;
--- a/icache_tb.vhdl
+++ b/icache_tb.vhdl
@ -74,6 +74,9 @@ begin
        i_out.req <= '0';
        i_out.nia <= (others => '0');
        i_out.stop_mark <= '0';
+        i_out.priv_mode <= '1';
+        i_out.virt_mode <= '0';
+        i_out.big_endian <= '0';

        m_out.tlbld <= '0';
        m_out.tlbie <= '0';
--- a/litedram/extras/litedram-wrapper-l2.vhdl
+++ b/litedram/extras/litedram-wrapper-l2.vhdl
@ -13,6 +13,7 @@ entity litedram_wrapper is
 	DRAM_ABITS      : positive;
 	DRAM_ALINES     : natural;
 	DRAM_DLINES     : natural;
+	DRAM_CKLINES    : natural;
 	DRAM_PORT_WIDTH : positive;

        -- Pseudo-ROM payload
@ -69,8 +70,8 @@ entity litedram_wrapper is
        ddram_dq      : inout std_ulogic_vector(DRAM_DLINES-1 downto 0);
        ddram_dqs_p   : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
        ddram_dqs_n   : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
-        ddram_clk_p   : out std_ulogic;
-        ddram_clk_n   : out std_ulogic;
+        ddram_clk_p   : out std_ulogic_vector(DRAM_CKLINES-1 downto 0);
+        ddram_clk_n   : out std_ulogic_vector(DRAM_CKLINES-1 downto 0);
        ddram_cke     : out std_ulogic;
        ddram_odt     : out std_ulogic;
        ddram_reset_n : out std_ulogic
@ -93,8 +94,8 @@ architecture behaviour of litedram_wrapper is
        ddram_dq                       : inout std_ulogic_vector(DRAM_DLINES-1 downto 0);
        ddram_dqs_p                    : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
        ddram_dqs_n                    : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
-        ddram_clk_p                    : out std_ulogic;
-        ddram_clk_n                    : out std_ulogic;
+        ddram_clk_p                    : out std_ulogic_vector(DRAM_CKLINES-1 downto 0);
+        ddram_clk_n                    : out std_ulogic_vector(DRAM_CKLINES-1 downto 0);
        ddram_cke                      : out std_ulogic;
        ddram_odt                      : out std_ulogic;
        ddram_reset_n                  : out std_ulogic;
--- a/litedram/extras/sim_litedram.vhdl
+++ b/litedram/extras/sim_litedram.vhdl
@ -102,8 +102,8 @@ entity litedram_core is
 	ddram_dq                       : inout std_ulogic_vector(15 downto 0);
 	ddram_dqs_p                    : inout std_ulogic_vector(1 downto 0);
 	ddram_dqs_n                    : inout std_ulogic_vector(1 downto 0);
-	ddram_clk_p                    : out std_ulogic;
-	ddram_clk_n                    : out std_ulogic;
+	ddram_clk_p                    : out std_ulogic_vector(0 downto 0);
+	ddram_clk_n                    : out std_ulogic_vector(0 downto 0);
 	ddram_cke                      : out std_ulogic;
 	ddram_odt                      : out std_ulogic;
 	ddram_reset_n                  : out std_ulogic;
--- a/litedram/gen-src/acorn-cle-215.yml
+++ b/litedram/gen-src/acorn-cle-215.yml
@ -31,6 +31,7 @@
    "user_ports": {
        "native_0": {
            "type": "native",
+            "block_until_ready": False,
        },
    },
 }
--- a/litedram/gen-src/arty.yml
+++ b/litedram/gen-src/arty.yml
@ -31,6 +31,7 @@
    "user_ports": {
        "native_0": {
            "type": "native",
+            "block_until_ready": False,
        },
    },
 }
--- a/litedram/gen-src/generate.py
+++ b/litedram/gen-src/generate.py
@ -100,7 +100,7 @@ def generate_one(t):

 def main():

-    targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'wukong-v2', 'sim']
+    targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'wukong-v2', 'orangecrab-85-0.2', 'sim']
    for t in targets:
        generate_one(t)
    
--- a/litedram/gen-src/genesys2.yml
+++ b/litedram/gen-src/genesys2.yml
@ -31,6 +31,7 @@
    "user_ports": {
        "native_0": {
            "type": "native",
+            "block_until_ready": False,
        },
    },
 }
--- a/litedram/gen-src/nexys-video.yml
+++ b/litedram/gen-src/nexys-video.yml
@ -31,6 +31,7 @@
    "user_ports": {
        "native_0": {
            "type": "native",
+            "block_until_ready": False,
        },
    },
 }
--- a/litedram/gen-src/orangecrab-85-0.2.yml
+++ b/litedram/gen-src/orangecrab-85-0.2.yml
@ -0,0 +1,39 @@
+# Matt Johnston 2021
+# Based on parameters from Greg Davill's Orangecrab-test-sw
+
+{
+    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
+    "device": "LFE5U-85F-8MG285C",
+    "memtype":    "DDR3",      # DRAM type
+
+    "sdram_module":    "MT41K256M16", # SDRAM modules of the board or SO-DIMM
+    "sdram_module_nb": 2,             # Number of byte groups
+    "sdram_rank_nb":   1,             # Number of ranks
+    "sdram_phy":       "ECP5DDRPHY",    # Type of FPGA PHY
+
+    # Electrical ---------------------------------------------------------------
+    "rtt_nom": "disabled",  # Nominal termination. ("disabled" from orangecrab)
+    "rtt_wr":  "60ohm",  # Write termination. (Default)
+    "ron":     "34ohm",  # Output driver impedance. (Default)
+
+    # Frequency ----------------------------------------------------------------
+    "init_clk_freq":   24e6,
+    "input_clk_freq":   48e6, # Input clock frequency
+    "sys_clk_freq":     48e6, # System clock frequency (DDR_clk = 4 x sys_clk)
+
+    # 0 if freq >64e6 else 100. https://github.com/enjoy-digital/litedram/issues/130
+    "cmd_delay": 100,
+
+    # Core ---------------------------------------------------------------------
+    "cmd_buffer_depth": 16,    # Depth of the command buffer
+
+    "dm_swap": true,
+
+    # User Ports ---------------------------------------------------------------
+    "user_ports": {
+        "native_0": {
+            "type": "native",
+            "block_until_ready": False,
+        },
+    },
+}
--- a/litedram/gen-src/sdram_init/Makefile
+++ b/litedram/gen-src/sdram_init/Makefile
@ -32,6 +32,7 @@ CPPFLAGS += -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(LXINC_DIR)/base -I$(LXSRC_DIR)/lib

 CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include)
 CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks 
+CFLAGS += -Werror
 ASFLAGS = $(CPPFLAGS) $(CFLAGS)
 LDFLAGS = -static -nostdlib -T $(OBJ)/$(PROGRAM).lds --gc-sections

--- a/litedram/gen-src/sim.yml
+++ b/litedram/gen-src/sim.yml
@ -31,6 +31,7 @@
    "user_ports": {
        "native_0": {
            "type": "native",
+            "block_until_ready": False,
        },
    },
 }
--- a/litedram/gen-src/wukong-v2.yml
+++ b/litedram/gen-src/wukong-v2.yml
@ -31,6 +31,7 @@
    "user_ports": {
        "native_0": {
            "type": "native",
+            "block_until_ready": False,
        },
    },
 }
--- a/litedram/generated/acorn-cle-215/litedram_core.init
+++ b/litedram/generated/acorn-cle-215/litedram_core.init
--- a/litedram/generated/acorn-cle-215/litedram_core.v
+++ b/litedram/generated/acorn-cle-215/litedram_core.v
--- a/litedram/generated/arty/litedram_core.init
+++ b/litedram/generated/arty/litedram_core.init
--- a/litedram/generated/arty/litedram_core.v
+++ b/litedram/generated/arty/litedram_core.v
--- a/litedram/generated/genesys2/litedram_core.init
+++ b/litedram/generated/genesys2/litedram_core.init
--- a/litedram/generated/genesys2/litedram_core.v
+++ b/litedram/generated/genesys2/litedram_core.v
--- a/litedram/generated/nexys-video/litedram_core.init
+++ b/litedram/generated/nexys-video/litedram_core.init
--- a/litedram/generated/nexys-video/litedram_core.v
+++ b/litedram/generated/nexys-video/litedram_core.v
--- a/litedram/generated/orangecrab-85-0.2/litedram-initmem.vhdl
+++ b/litedram/generated/orangecrab-85-0.2/litedram-initmem.vhdl
@ -0,0 +1,123 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+use work.utils.all;
+
+entity dram_init_mem is
+    generic (
+        EXTRA_PAYLOAD_FILE : string   := "";
+        EXTRA_PAYLOAD_SIZE : integer  := 0
+        );
+    port (
+        clk     : in std_ulogic;
+        wb_in   : in wb_io_master_out;
+        wb_out  : out wb_io_slave_out
+      );
+end entity dram_init_mem;
+
+architecture rtl of dram_init_mem is
+
+    constant INIT_RAM_SIZE    : integer := 24576;
+    constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
+    constant TOTAL_RAM_SIZE   : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
+    constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE-1);
+    constant INIT_RAM_FILE    : string := "litedram_core.init";
+
+    type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
+
+    -- XXX FIXME: Have a single init function called twice with
+    -- an offset as argument
+    procedure init_load_payload(ram: inout ram_t; filename: string) is
+        file payload_file : text open read_mode is filename;
+        variable ram_line : line;
+        variable temp_word : std_logic_vector(63 downto 0);
+    begin
+        for i in 0 to RND_PAYLOAD_SIZE-1 loop
+            exit when endfile(payload_file);
+            readline(payload_file, ram_line);
+            hread(ram_line, temp_word);
+            ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0);
+            ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32);
+        end loop;
+        assert endfile(payload_file) report "Payload too big !" severity failure;
+    end procedure;
+
+    impure function init_load_ram(name : string) return ram_t is
+        file ram_file : text open read_mode is name;
+        variable temp_word : std_logic_vector(63 downto 0);
+        variable temp_ram : ram_t := (others => (others => '0'));
+        variable ram_line : line;
+    begin
+        report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) &
+            " rounded to:" & integer'image(RND_PAYLOAD_SIZE);
+        report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) &
+            " bytes using " & integer'image(INIT_RAM_ABITS) &
+            " address bits";
+        for i in 0 to (INIT_RAM_SIZE/8)-1 loop
+            exit when endfile(ram_file);
+            readline(ram_file, ram_line);
+            hread(ram_line, temp_word);
+            temp_ram(i*2) := temp_word(31 downto 0);
+            temp_ram(i*2+1) := temp_word(63 downto 32);
+        end loop;
+        if RND_PAYLOAD_SIZE /= 0 then
+            init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE);
+        end if;
+        return temp_ram;
+    end function;
+
+    impure function init_zero return ram_t is
+        variable temp_ram : ram_t := (others => (others => '0'));
+    begin
+        return temp_ram;
+    end function;
+
+    impure function initialize_ram(filename: string) return ram_t is
+    begin
+        report "Opening file " & filename;
+        if filename'length = 0 then
+            return init_zero;
+        else
+            return init_load_ram(filename);
+        end if;
+    end function;
+    signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE);
+
+    attribute ram_style : string;
+    attribute ram_style of init_ram: signal is "block";
+
+    signal obuf : std_ulogic_vector(31 downto 0);
+    signal oack : std_ulogic;
+begin
+
+    init_ram_0: process(clk)
+        variable adr  : integer;
+    begin
+        if rising_edge(clk) then
+            oack <= '0';
+            if (wb_in.cyc and wb_in.stb) = '1' then
+                adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS - 3 downto 0))));
+                if wb_in.we = '0' then
+                   obuf <= init_ram(adr);
+                else
+                    for i in 0 to 3 loop
+                        if wb_in.sel(i) = '1' then
+                            init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
+                                wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
+                        end if;
+                    end loop;
+                end if;
+                oack <= '1';
+            end if;
+            wb_out.ack <= oack;
+            wb_out.dat <= obuf;
+        end if;
+    end process;
+
+    wb_out.stall <= '0';
+
+end architecture rtl;
--- a/litedram/generated/orangecrab-85-0.2/litedram_core.init
+++ b/litedram/generated/orangecrab-85-0.2/litedram_core.init
--- a/litedram/generated/orangecrab-85-0.2/litedram_core.v
+++ b/litedram/generated/orangecrab-85-0.2/litedram_core.v
--- a/litedram/generated/sim/litedram_core.init
+++ b/litedram/generated/sim/litedram_core.init
--- a/litedram/generated/sim/litedram_core.v
+++ b/litedram/generated/sim/litedram_core.v
--- a/litedram/generated/wukong-v2/litedram-initmem.vhdl
+++ b/litedram/generated/wukong-v2/litedram-initmem.vhdl
@ -100,7 +100,7 @@ begin
        if rising_edge(clk) then
            oack <= '0';
            if (wb_in.cyc and wb_in.stb) = '1' then
-                adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
+                adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS - 3 downto 0))));
                if wb_in.we = '0' then
                   obuf <= init_ram(adr);
                else
--- a/litedram/generated/wukong-v2/litedram_core.init
+++ b/litedram/generated/wukong-v2/litedram_core.init
--- a/litedram/generated/wukong-v2/litedram_core.v
+++ b/litedram/generated/wukong-v2/litedram_core.v
--- a/litesdcard/gen-src/generate.sh
+++ b/litesdcard/gen-src/generate.sh
@ -1,6 +1,7 @@
 #!/bin/bash

-VENDORS="xilinx"
+# vendor:sysclk
+VENDORS="xilinx:100 lattice:48"

 ME=$(realpath $0)
 echo ME=$ME
@ -13,8 +14,10 @@ mkdir -p $BUILD_PATH
 GEN_PATH=$PARENT_PATH/generated
 mkdir -p $GEN_PATH

-for i in $VENDORS
+for i_clk in $VENDORS
 do
+    i=$(echo $i_clk | cut -d : -f 1)
+    clk=$(echo $i_clk | cut -d : -f 2)
    TARGET_BUILD_PATH=$BUILD_PATH/$i
    TARGET_GEN_PATH=$GEN_PATH/$i
    rm -rf $TARGET_BUILD_PATH
@ -22,8 +25,8 @@ do
    mkdir -p $TARGET_BUILD_PATH
    mkdir -p $TARGET_GEN_PATH

-    echo "Generating $i in $TARGET_BUILD_PATH"    
-    (cd $TARGET_BUILD_PATH && litesdcard_gen --vendor $i)
+    echo "Generating $i in $TARGET_BUILD_PATH"
+    (cd $TARGET_BUILD_PATH && litesdcard_gen --vendor $i --clk-freq $clk)

    cp $TARGET_BUILD_PATH/build/gateware/litesdcard_core.v $TARGET_GEN_PATH/
 done
--- a/litesdcard/generated/lattice/litesdcard_core.v
+++ b/litesdcard/generated/lattice/litesdcard_core.v
--- a/litesdcard/generated/xilinx/litesdcard_core.v
+++ b/litesdcard/generated/xilinx/litesdcard_core.v
--- a/loadstore1.vhdl
+++ b/loadstore1.vhdl
@ -275,10 +275,27 @@ begin
        if rising_edge(clk) then
            if rst = '1' then
                r1.req.valid <= '0';
+                r1.req.tlbie <= '0';
+                r1.req.is_slbia <= '0';
+                r1.req.instr_fault <= '0';
+                r1.req.load <= '0';
+                r1.req.priv_mode <= '0';
+                r1.req.sprn <= (others => '0');
+                r1.req.xerc <= xerc_init;
+
                r2.req.valid <= '0';
+                r2.req.tlbie <= '0';
+                r2.req.is_slbia <= '0';
+                r2.req.instr_fault <= '0';
+                r2.req.load <= '0';
+                r2.req.priv_mode <= '0';
+                r2.req.sprn <= (others => '0');
+                r2.req.xerc <= xerc_init;
+
                r2.wait_dc <= '0';
                r2.wait_mmu <= '0';
                r2.one_cycle <= '0';
+
                r3.dar <= (others => '0');
                r3.dsisr <= (others => '0');
                r3.state <= IDLE;
@ -286,6 +303,8 @@ begin
                r3.interrupt <= '0';
                r3.stage1_en <= '1';
                r3.convert_lfs <= '0';
+                r3.events.load_complete <= '0';
+                r3.events.store_complete <= '0';
                flushing <= '0';
            else
                r1 <= r1in;
--- a/logical.vhdl
+++ b/logical.vhdl
@ -20,20 +20,7 @@ end entity logical;

 architecture behaviour of logical is

-    subtype twobit is unsigned(1 downto 0);
-    type twobit32 is array(0 to 31) of twobit;
-    signal pc2      : twobit32;
-    subtype threebit is unsigned(2 downto 0);
-    type threebit16 is array(0 to 15) of threebit;
-    signal pc4      : threebit16;
-    subtype fourbit is unsigned(3 downto 0);
-    type fourbit8 is array(0 to 7) of fourbit;
-    signal pc8      : fourbit8;
-    subtype sixbit is unsigned(5 downto 0);
-    type sixbit2 is array(0 to 1) of sixbit;
-    signal pc32     : sixbit2;
    signal par0, par1 : std_ulogic;
-    signal popcnt   : std_ulogic_vector(63 downto 0);
    signal parity   : std_ulogic_vector(63 downto 0);
    signal permute  : std_ulogic_vector(7 downto 0);

@ -109,35 +96,6 @@ begin
        variable negative : std_ulogic;
        variable j : integer;
    begin
-        -- population counts
-        for i in 0 to 31 loop
-            pc2(i) <= unsigned("0" & rs(i * 2 downto i * 2)) + unsigned("0" & rs(i * 2 + 1 downto i * 2 + 1));
-        end loop;
-        for i in 0 to 15 loop
-            pc4(i) <= ('0' & pc2(i * 2)) + ('0' & pc2(i * 2 + 1));
-        end loop;
-        for i in 0 to 7 loop
-            pc8(i) <= ('0' & pc4(i * 2)) + ('0' & pc4(i * 2 + 1));
-        end loop;
-        for i in 0 to 1 loop
-            pc32(i) <= ("00" & pc8(i * 4)) + ("00" & pc8(i * 4 + 1)) +
-                       ("00" & pc8(i * 4 + 2)) + ("00" & pc8(i * 4 + 3));
-        end loop;
-        popcnt <= (others => '0');
-        if datalen(3 downto 2) = "00" then
-            -- popcntb
-            for i in 0 to 7 loop
-                popcnt(i * 8 + 3 downto i * 8) <= std_ulogic_vector(pc8(i));
-            end loop;
-        elsif datalen(3) = '0' then
-            -- popcntw
-            for i in 0 to 1 loop
-                popcnt(i * 32 + 5 downto i * 32) <= std_ulogic_vector(pc32(i));
-            end loop;
-        else
-            popcnt(6 downto 0) <= std_ulogic_vector(('0' & pc32(0)) + ('0' & pc32(1)));
-        end if;
-
        -- parity calculations
        par0 <= rs(0) xor rs(8) xor rs(16) xor rs(24);
        par1 <= rs(32) xor rs(40) xor rs(48) xor rs(56);
@ -178,8 +136,6 @@ begin
                    tmp := not tmp;
                end if;

-            when OP_POPCNT =>
-                tmp := popcnt;
            when OP_PRTY =>
                tmp := parity;
            when OP_CMPB =>
--- a/microwatt.core
+++ b/microwatt.core
@ -18,7 +18,7 @@ filesets:
      - ppc_fx_insns.vhdl
      - sim_console.vhdl
      - logical.vhdl
-      - countzero.vhdl
+      - countbits.vhdl
      - control.vhdl
      - execute1.vhdl
      - fpu.vhdl
--- a/scripts/mw_debug/Makefile
+++ b/scripts/mw_debug/Makefile
@ -1,10 +1,16 @@
 CFLAGS = -O2 -g -Wall -std=c99
 # CFLAGS +=  -I urjtag/urjtag/include/ -L urjtag/urjtag/src/.libs/
+#
+ifeq ($(STATIC_URJTAG), 1)
+	LIBURJTAG=-Wl,-Bstatic -lurjtag -Wl,-Bdynamic -lftdi1 -lusb-1.0 -lreadline
+else
+	LIBURJTAG=-lurjtag
+endif

 all: mw_debug

 mw_debug: mw_debug.c
-	$(CC) -o $@ $^ $(CFLAGS) -lurjtag
+	$(CC) -o $@ $^ $(CFLAGS) $(LIBURJTAG)

 clean:
 	rm -f mw_debug
--- a/scripts/mw_debug/mw_debug.c
+++ b/scripts/mw_debug/mw_debug.c
@ -49,7 +49,7 @@
 static bool debug;

 struct backend {
-	int (*init)(const char *target);
+	int (*init)(const char *target, int freq);
 	int (*reset)(void);
 	int (*command)(uint8_t op, uint8_t addr, uint64_t *data);
 };
@ -67,13 +67,15 @@ static void check(int r, const char *failstr)

 static int sim_fd = -1;

-static int sim_init(const char *target)
+static int sim_init(const char *target, int freq)
 {
 	struct sockaddr_in saddr;
 	struct hostent *hp;
 	const char *p, *host;
 	int port, rc;

+	(void)freq;
+
 	if (!target)
 		target = "localhost:13245";
 	p = strchr(target, ':');
@ -210,22 +212,33 @@ static struct backend sim_backend = {

 static urj_chain_t *jc;

-static int jtag_init(const char *target)
+static int common_jtag_init(const char *target, int freq)
 {
 	const char *sep;
 	const char *cable;
-	char *params[] = { NULL, };
-	urj_part_t *p;
-	uint32_t id;
-	int rc, part;
+	const int max_params = 20;
+	char *params[max_params+1];
+	int rc;

 	if (!target)
 		target = "probe";
-	sep = strchr(target, ':');
+	memset(params, 0x0, sizeof(params));
+	sep = strchr(target, ' ');
 	cable = strndup(target, sep - target);
 	if (sep && *sep) {
-		fprintf(stderr, "jtag cable params not supported yet\n");
-		return -1;
+		char *param_str = strdup(sep);
+		char *s = param_str;
+		for (int i = 0; *s; s++) {
+			if (*s == ' ') {
+				if (i >= max_params) {
+					fprintf(stderr, "Too many jtag cable params\n");
+					return -1;
+				}
+				*s = '\0';
+				params[i] = s+1;
+				i++;
+			}
+		}
 	}
 	if (debug)
 		printf("Opening jtag backend cable '%s'\n", cable);
@ -241,17 +254,35 @@ static int jtag_init(const char *target)
 		char *cparams[] = { NULL, NULL,};
 		rc = urj_tap_cable_usb_probe(cparams);
 		if (rc != URJ_STATUS_OK) {
-			fprintf(stderr, "JTAG cable probe failed\n");
+			fprintf(stderr, "JTAG cable probe failed: %s\n", urj_error_describe());
 			return -1;
 		}
 		cable = strdup(cparams[1]);
 	}
 	rc = urj_tap_chain_connect(jc, cable, params);
 	if (rc != URJ_STATUS_OK) {
-		fprintf(stderr, "JTAG cable detect failed\n");
+		fprintf(stderr, "JTAG cable detect failed: %s\n", urj_error_describe());
 		return -1;
 	}

+	if (freq) {
+		urj_tap_cable_set_frequency(jc->cable, freq);
+	}
+
+	return 0;
+}
+
+static int bscane2_init(const char *target, int freq)
+{
+	urj_part_t *p;
+	uint32_t id;
+	int rc;
+
+	rc = common_jtag_init(target, freq);
+	if (rc < 0) {
+	    return rc;
+	}
+
 	/* XXX Hard wire part 0, that might need to change (use params and detect !) */
 	rc = urj_tap_manual_add(jc, 6);
 	if (rc < 0) {
@ -264,7 +295,7 @@ static int jtag_init(const char *target)
 	}
 	urj_part_parts_set_instruction(jc->parts, "BYPASS");

-	jc->active_part = part = 0;
+	jc->active_part = 0;

 	p = urj_tap_chain_active_part(jc);
 	if (!p) {
@ -300,6 +331,69 @@ static int jtag_init(const char *target)
 	return 0;
 }

+static int ecp5_init(const char *target, int freq)
+{
+	urj_part_t *p;
+	uint32_t id;
+	int rc;
+
+	rc = common_jtag_init(target, freq);
+	if (rc < 0) {
+	    return rc;
+	}
+
+	/* XXX Hard wire part 0, that might need to change (use params and detect !) */
+	rc = urj_tap_manual_add(jc, 8);
+	if (rc < 0) {
+		fprintf(stderr, "JTAG failed to add part! : %s\n", urj_error_describe());
+		return -1;
+	}
+	if (jc->parts == NULL || jc->parts->len == 0) {
+		fprintf(stderr, "JTAG Something's wrong after adding part! : %s\n", urj_error_describe());
+		return -1;
+	}
+	urj_part_parts_set_instruction(jc->parts, "BYPASS");
+
+	jc->active_part = 0;
+
+	p = urj_tap_chain_active_part(jc);
+	if (!p) {
+		fprintf(stderr, "Failed to get active JTAG part\n");
+		return -1;
+	}
+	rc = urj_part_data_register_define(p, "IDCODE_REG", 32);
+	if (rc != URJ_STATUS_OK) {
+		fprintf(stderr, "JTAG failed to add IDCODE_REG register! : %s\n",
+			urj_error_describe());
+		return -1;
+	}
+	// READ_ID = 0xE0 = 11100000, from Lattice TN1260 sysconfig guide
+	if (urj_part_instruction_define(p, "IDCODE", "11100000", "IDCODE_REG") == NULL) {
+		fprintf(stderr, "JTAG failed to add IDCODE instruction! : %s\n",
+			urj_error_describe());
+		return -1;
+	}
+	rc = urj_part_data_register_define(p, "USER2_REG", 74);
+	if (rc != URJ_STATUS_OK) {
+		fprintf(stderr, "JTAG failed to add USER2_REG register !\n");
+		return -1;
+	}
+	// ER1 = 0x32 = 00110010b
+	if (urj_part_instruction_define(p, "USER2", "00110010", "USER2_REG") == NULL) {
+		fprintf(stderr, "JTAG failed to add USER2 instruction !\n");
+		return -1;
+	}
+	urj_part_set_instruction(p, "IDCODE");
+	urj_tap_chain_shift_instructions(jc);
+	urj_tap_chain_shift_data_registers(jc, 1);
+	id = urj_tap_register_get_value(p->active_instruction->data_register->out);
+	printf("Found device ID: 0x%08x\n", id);
+	urj_part_set_instruction(p, "USER2");
+	urj_tap_chain_shift_instructions(jc);
+
+	return 0;
+}
+
 static int jtag_reset(void)
 {
 	return 0;
@ -339,8 +433,14 @@ static int jtag_command(uint8_t op, uint8_t addr, uint64_t *data)
 	return rc;
 }

-static struct backend jtag_backend = {
-	.init	= jtag_init,
+static struct backend bscane2_backend = {
+	.init	= bscane2_init,
+	.reset = jtag_reset,
+	.command = jtag_command,
+};
+
+static struct backend ecp5_backend = {
+	.init	= ecp5_init,
 	.reset = jtag_reset,
 	.command = jtag_command,
 };
@ -662,7 +762,7 @@ static void ltrig_set(uint64_t addr)

 static void usage(const char *cmd)
 {
-	fprintf(stderr, "Usage: %s -b <jtag|sim> <command> <args>\n", cmd);
+	fprintf(stderr, "Usage: %s -b <jtag|ecp5|sim> <command> <args>\n", cmd);

 	fprintf(stderr, "\n");
 	fprintf(stderr, " CPU core:\n");
@ -706,7 +806,7 @@ int main(int argc, char *argv[])
 {
 	const char *progname = argv[0];
 	const char *target = NULL;
-	int rc, i = 1;
+	int rc, i = 1, freq = 0;

 	b = NULL;

@ -717,9 +817,10 @@ int main(int argc, char *argv[])
 			{ "backend",	required_argument, 0, 'b' },
 			{ "target",	required_argument, 0, 't' },
 			{ "debug",	no_argument,       0, 'd' },
+			{ "frequency",	no_argument,       0, 's' },
 			{ 0, 0, 0, 0 }
 		};
-		c = getopt_long(argc, argv, "dhb:t:", lopts, &oindex);
+		c = getopt_long(argc, argv, "dhb:t:s:", lopts, &oindex);
 		if (c < 0)
 			break;
 		switch(c) {
@ -729,8 +830,10 @@ int main(int argc, char *argv[])
 		case 'b':
 			if (strcmp(optarg, "sim") == 0)
 				b = &sim_backend;
-			else if (strcmp(optarg, "jtag") == 0)
-				b = &jtag_backend;
+			else if (strcmp(optarg, "jtag") == 0 || strcmp(optarg, "bscane2") == 0)
+				b = &bscane2_backend;
+			else if (strcmp(optarg, "ecp5") == 0)
+				b = &ecp5_backend;
 			else {
 				fprintf(stderr, "Unknown backend %s\n", optarg);
 				exit(1);
@ -739,15 +842,22 @@ int main(int argc, char *argv[])
 		case 't':
 			target = optarg;
 			break;
+		case 's':
+			freq = atoi(optarg);
+			if (freq == 0) {
+				fprintf(stderr, "Bad frequency %s\n", optarg);
+				exit(1);
+			}
+			break;
 		case 'd':
 			debug = true;
 		}
 	}

 	if (b == NULL)
-		b = &jtag_backend;
+		b = &bscane2_backend;

-	rc = b->init(target);
+	rc = b->init(target, freq);
 	if (rc < 0)
 		exit(1);
 	for (i = optind; i < argc; i++) {
@ -789,7 +899,7 @@ int main(int argc, char *argv[])
 			if ((i+1) >= argc)
 				usage(argv[0]);
 			addr = strtoul(argv[++i], NULL, 16);
-			if (((i+1) < argc) && isdigit(argv[i+1][0]))
+			if (((i+1) < argc) && isxdigit(argv[i+1][0]))
 				count = strtoul(argv[++i], NULL, 16);
 			mem_read(addr, count);
 		} else if (strcmp(argv[i], "mw") == 0) {
@ -807,7 +917,7 @@ int main(int argc, char *argv[])
 			if ((i+1) >= argc)
 				usage(argv[0]);
 			filename = argv[++i];
-			if (((i+1) < argc) && isdigit(argv[i+1][0]))
+			if (((i+1) < argc) && isxdigit(argv[i+1][0]))
 				addr = strtoul(argv[++i], NULL, 16);
 			load(filename, addr);
 		} else if (strcmp(argv[i], "save") == 0) {
--- a/soc.vhdl
+++ b/soc.vhdl
@ -61,6 +61,7 @@ entity soc is
        HAS_BTC            : boolean := true;
        HAS_SHORT_MULT     : boolean := false;
 	DISABLE_FLATTEN_CORE : boolean := false;
+        ALT_RESET_ADDRESS  : std_logic_vector(63 downto 0) := (23 downto 0 => '0', others => '1');
 	HAS_DRAM           : boolean  := false;
 	DRAM_SIZE          : integer := 0;
        DRAM_INIT_SIZE     : integer := 0;
@ -222,15 +223,15 @@ architecture behaviour of soc is
    signal dmi_core_ack   : std_ulogic;

    -- Delayed/latched resets and alt_reset
-    signal rst_core    : std_ulogic := '1';
-    signal rst_uart    : std_ulogic := '1';
-    signal rst_xics    : std_ulogic := '1';
-    signal rst_spi     : std_ulogic := '1';
-    signal rst_gpio    : std_ulogic := '1';
-    signal rst_bram    : std_ulogic := '1';
-    signal rst_dtm     : std_ulogic := '1';
-    signal rst_wbar    : std_ulogic := '1';
-    signal rst_wbdb    : std_ulogic := '1';
+    signal rst_core    : std_ulogic;
+    signal rst_uart    : std_ulogic;
+    signal rst_xics    : std_ulogic;
+    signal rst_spi     : std_ulogic;
+    signal rst_gpio    : std_ulogic;
+    signal rst_bram    : std_ulogic;
+    signal rst_dtm     : std_ulogic;
+    signal rst_wbar    : std_ulogic;
+    signal rst_wbdb    : std_ulogic;
    signal alt_reset_d : std_ulogic;

    -- IO branch split:
@ -239,12 +240,20 @@ architecture behaviour of soc is
                           SLAVE_IO_ICP,
                           SLAVE_IO_ICS,
                           SLAVE_IO_UART1,
-                           SLAVE_IO_SPI_FLASH_REG,
-                           SLAVE_IO_SPI_FLASH_MAP,
+                           SLAVE_IO_SPI_FLASH,
                           SLAVE_IO_GPIO,
-                           SLAVE_IO_EXTERNAL,
-                           SLAVE_IO_NONE);
-    signal slave_io_dbg : slave_io_type;
+                           SLAVE_IO_EXTERNAL);
+    signal current_io_decode : slave_io_type;
+
+    signal io_cycle_none      : std_ulogic;
+    signal io_cycle_syscon    : std_ulogic;
+    signal io_cycle_uart      : std_ulogic;
+    signal io_cycle_uart1     : std_ulogic;
+    signal io_cycle_icp       : std_ulogic;
+    signal io_cycle_ics       : std_ulogic;
+    signal io_cycle_spi_flash : std_ulogic;
+    signal io_cycle_gpio      : std_ulogic;
+    signal io_cycle_external  : std_ulogic;

    function wishbone_widen_data(wb : wb_io_master_out) return wishbone_master_out is
        variable wwb : wishbone_master_out;
@ -328,7 +337,7 @@ begin
            HAS_BTC => HAS_BTC,
            HAS_SHORT_MULT => HAS_SHORT_MULT,
 	    DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
-	    ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
+	    ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
            LOG_LENGTH => LOG_LENGTH,
            ICACHE_NUM_LINES => ICACHE_NUM_LINES,
            ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
@ -465,14 +474,20 @@ begin
        -- Misc
        variable has_top : boolean;
        variable has_bot : boolean;
+        variable do_cyc  : std_ulogic;
+        variable end_cyc : std_ulogic;
+        variable slave_io : slave_io_type;
+        variable match   : std_ulogic_vector(31 downto 12);
    begin
        if rising_edge(system_clk) then
+            do_cyc := '0';
+            end_cyc := '0';
            if (rst) then
                state := IDLE;
                wb_io_out.ack <= '0';
                wb_io_out.stall <= '0';
-                wb_sio_out.cyc <= '0';
                wb_sio_out.stb <= '0';
+                end_cyc := '1';
                has_top := false;
                has_bot := false;
            else
@ -488,7 +503,7 @@ begin
                        wb_io_out.stall <= '1';

                        -- Start cycle downstream
-                        wb_sio_out.cyc <= '1';
+                        do_cyc := '1';
                        wb_sio_out.stb <= '1';

                        -- Copy write enable to IO out, copy address as well
@ -551,8 +566,8 @@ begin
                            -- Wait for new ack
                            state := WAIT_ACK_TOP;
                        else
-                            -- We are done, ack up, clear cyc downstram
-                            wb_sio_out.cyc <= '0';
+                            -- We are done, ack up, clear cyc downstream
+                            end_cyc := '1';

                            -- And ack & unstall upstream
                            wb_io_out.ack <= '1';
@ -576,7 +591,7 @@ begin
                        end if;

                        -- We are done, ack up, clear cyc downstram
-                        wb_sio_out.cyc <= '0';
+                        end_cyc := '1';

                        -- And ack & unstall upstream
                        wb_io_out.ack <= '1';
@ -587,144 +602,149 @@ begin
                    end if;
                end case;
            end if;
+
+            -- Create individual registered cycle signals for the wishbones
+            -- going to the various peripherals
+            if do_cyc = '1' or end_cyc = '1' then
+                io_cycle_none      <= '0';
+                io_cycle_syscon    <= '0';
+                io_cycle_uart      <= '0';
+                io_cycle_uart1     <= '0';
+                io_cycle_icp       <= '0';
+                io_cycle_ics       <= '0';
+                io_cycle_spi_flash <= '0';
+                io_cycle_gpio      <= '0';
+                io_cycle_external  <= '0';
+                wb_sio_out.cyc     <= '0';
+                wb_ext_is_dram_init <= '0';
+                wb_spiflash_is_map <= '0';
+                wb_spiflash_is_reg <= '0';
+                wb_ext_is_dram_csr <= '0';
+                wb_ext_is_eth      <= '0';
+                wb_ext_is_sdcard   <= '0';
+            end if;
+            if do_cyc = '1' then
+                -- Decode I/O address
+                -- This is real address bits 29 downto 12
+                match := "11" & wb_io_in.adr(26 downto 9);
+                slave_io := SLAVE_IO_SYSCON;
+                if    std_match(match, x"FF---") and HAS_DRAM then
+                    slave_io := SLAVE_IO_EXTERNAL;
+                    io_cycle_external <= '1';
+                    wb_ext_is_dram_init <= '1';
+                elsif std_match(match, x"F----") then
+                    slave_io := SLAVE_IO_SPI_FLASH;
+                    io_cycle_spi_flash <= '1';
+                    wb_spiflash_is_map <= '1';
+                elsif std_match(match, x"C8---") then
+                    -- Ext IO "chip selects"
+                    if    std_match(match, x"--00-") and HAS_DRAM then
+                        slave_io := SLAVE_IO_EXTERNAL;
+                        io_cycle_external <= '1';
+                        wb_ext_is_dram_csr <= '1';
+                    elsif (std_match(match, x"--02-") or std_match(match, x"--03-")) and
+                           HAS_LITEETH then
+                        slave_io := SLAVE_IO_EXTERNAL;
+                        io_cycle_external <= '1';
+                        wb_ext_is_eth <= '1';
+                    elsif std_match(match, x"--04-") and HAS_SD_CARD then
+                        slave_io := SLAVE_IO_EXTERNAL;
+                        io_cycle_external <= '1';
+                        wb_ext_is_sdcard <= '1';
+                    else
+                        io_cycle_none <= '1';
+                    end if;
+                elsif std_match(match, x"C0000") then
+                    slave_io := SLAVE_IO_SYSCON;
+                    io_cycle_syscon <= '1';
+                elsif std_match(match, x"C0002") then
+                    slave_io := SLAVE_IO_UART;
+                    io_cycle_uart <= '1';
+                elsif std_match(match, x"C0003") then
+                    slave_io := SLAVE_IO_UART1;
+                    io_cycle_uart1 <= '1';
+                elsif std_match(match, x"C0004") then
+                    slave_io := SLAVE_IO_ICP;
+                    io_cycle_icp <= '1';
+                elsif std_match(match, x"C0005") then
+                    slave_io := SLAVE_IO_ICS;
+                    io_cycle_ics <= '1';
+                elsif std_match(match, x"C0006") then
+                    slave_io := SLAVE_IO_SPI_FLASH;
+                    io_cycle_spi_flash <= '1';
+                    wb_spiflash_is_reg <= '1';
+                elsif std_match(match, x"C0007") then
+                    slave_io := SLAVE_IO_GPIO;
+                    io_cycle_gpio <= '1';
+                else
+                    io_cycle_none <= '1';
+                end if;
+                current_io_decode <= slave_io;
+                wb_sio_out.cyc <= '1';
+            end if;
        end if;
    end process;
            
-    -- IO wishbone slave intercon.
+    -- IO wishbone slave interconnect.
    --
-    slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
-                               wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
-                               wb_spiflash_out)
-	variable slave_io : slave_io_type;
-
-        variable match : std_ulogic_vector(31 downto 12);
-        variable ext_valid : boolean;
+    slave_io_intercon: process(all)
    begin
-
-	-- Simple address decoder.
-	slave_io := SLAVE_IO_NONE;
-        match := "11" & wb_sio_out.adr(27 downto 10);
-        if    std_match(match, x"FF---") and HAS_DRAM then
-	    slave_io := SLAVE_IO_EXTERNAL;
-        elsif std_match(match, x"F----") then
-	    slave_io := SLAVE_IO_SPI_FLASH_MAP;
-	elsif std_match(match, x"C0000") then
-	    slave_io := SLAVE_IO_SYSCON;
-	elsif std_match(match, x"C0002") then
-	    slave_io := SLAVE_IO_UART;
-	elsif std_match(match, x"C0003") then
-	    slave_io := SLAVE_IO_UART1;
-	elsif std_match(match, x"C8---") then
-	    slave_io := SLAVE_IO_EXTERNAL;
-	elsif std_match(match, x"C0004") then
-	    slave_io := SLAVE_IO_ICP;
-	elsif std_match(match, x"C0005") then
-	    slave_io := SLAVE_IO_ICS;
-	elsif std_match(match, x"C0006") then
-	    slave_io := SLAVE_IO_SPI_FLASH_REG;
-        elsif std_match(match, x"C0007") then
-            slave_io := SLAVE_IO_GPIO;
-	end if;
-        slave_io_dbg <= slave_io;
 	wb_uart0_in <= wb_sio_out;
-	wb_uart0_in.cyc <= '0';
+	wb_uart0_in.cyc <= io_cycle_uart;
 	wb_uart1_in <= wb_sio_out;
-	wb_uart1_in.cyc <= '0';
+	wb_uart1_in.cyc <= io_cycle_uart1;
+
 	wb_spiflash_in <= wb_sio_out;
-	wb_spiflash_in.cyc <= '0';
-        wb_spiflash_is_reg <= '0';
-        wb_spiflash_is_map <= '0';
+	wb_spiflash_in.cyc <= io_cycle_spi_flash;
+        -- Clear top bits so they don't make their way to the
+        -- flash chip.
+        wb_spiflash_in.adr(27 downto 26) <= "00";
+
        wb_gpio_in <= wb_sio_out;
-        wb_gpio_in.cyc <= '0';
+        wb_gpio_in.cyc <= io_cycle_gpio;

 	 -- Only give xics 8 bits of wb addr (for now...)
 	wb_xics_icp_in <= wb_sio_out;
 	wb_xics_icp_in.adr <= (others => '0');
 	wb_xics_icp_in.adr(5 downto 0) <= wb_sio_out.adr(5 downto 0);
-	wb_xics_icp_in.cyc  <= '0';
+	wb_xics_icp_in.cyc  <= io_cycle_icp;
 	wb_xics_ics_in <= wb_sio_out;
 	wb_xics_ics_in.adr <= (others => '0');
 	wb_xics_ics_in.adr(9 downto 0) <= wb_sio_out.adr(9 downto 0);
-	wb_xics_ics_in.cyc  <= '0';
+	wb_xics_ics_in.cyc  <= io_cycle_ics;

 	wb_ext_io_in <= wb_sio_out;
-	wb_ext_io_in.cyc <= '0';
+	wb_ext_io_in.cyc <= io_cycle_external;

 	wb_syscon_in <= wb_sio_out;
-	wb_syscon_in.cyc <= '0';
-
-	wb_ext_is_dram_csr   <= '0';
-	wb_ext_is_dram_init  <= '0';
-	wb_ext_is_eth        <= '0';
-        wb_ext_is_sdcard     <= '0';
+	wb_syscon_in.cyc <= io_cycle_syscon;

-        -- Default response, ack & return all 1's
-        wb_sio_in.dat <= (others => '1');
-        wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
-        wb_sio_in.stall <= '0';
-
-	case slave_io is
+	case current_io_decode is
 	when SLAVE_IO_EXTERNAL =>
-            -- Ext IO "chip selects"
-            --
-            -- DRAM init is special at 0xFF* so we just test the top
-            -- bit. Everything else is at 0xC8* so we test only bits
-            -- 23 downto 16 (21 downto 14 in the wishbone addr).
-            --
-            ext_valid := false;
-            if wb_sio_out.adr(27) = '1' and HAS_DRAM then  -- DRAM init is special
-                wb_ext_is_dram_init <= '1';
-                ext_valid := true;
-            elsif wb_sio_out.adr(21 downto 14) = x"00" and HAS_DRAM then
-                wb_ext_is_dram_csr  <= '1';
-                ext_valid := true;
-            elsif wb_sio_out.adr(21 downto 14) = x"02" and HAS_LITEETH then
-                wb_ext_is_eth       <= '1';
-                ext_valid := true;
-            elsif wb_sio_out.adr(21 downto 14) = x"03" and HAS_LITEETH then
-                wb_ext_is_eth       <= '1';
-                ext_valid := true;
-            elsif wb_sio_out.adr(21 downto 14) = x"04" and HAS_SD_CARD then
-                wb_ext_is_sdcard    <= '1';
-                ext_valid := true;
-            end if;
-            if ext_valid then
-                wb_ext_io_in.cyc <= wb_sio_out.cyc;
-                wb_sio_in <= wb_ext_io_out;
-            end if;
-
+            wb_sio_in <= wb_ext_io_out;
 	when SLAVE_IO_SYSCON =>
-	    wb_syscon_in.cyc <= wb_sio_out.cyc;
 	    wb_sio_in <= wb_syscon_out;
 	when SLAVE_IO_UART =>
-	    wb_uart0_in.cyc <= wb_sio_out.cyc;
 	    wb_sio_in <= wb_uart0_out;
 	when SLAVE_IO_ICP =>
-	    wb_xics_icp_in.cyc <= wb_sio_out.cyc;
 	    wb_sio_in <= wb_xics_icp_out;
 	when SLAVE_IO_ICS =>
-	    wb_xics_ics_in.cyc <= wb_sio_out.cyc;
 	    wb_sio_in <= wb_xics_ics_out;
 	when SLAVE_IO_UART1 =>
-	    wb_uart1_in.cyc <= wb_sio_out.cyc;
 	    wb_sio_in <= wb_uart1_out;
-	when SLAVE_IO_SPI_FLASH_MAP =>
-            -- Clear top bits so they don't make their way to the
-            -- fash chip.
-            wb_spiflash_in.adr(27 downto 26) <= "00";
-	    wb_spiflash_in.cyc <= wb_sio_out.cyc;
+	when SLAVE_IO_SPI_FLASH =>
 	    wb_sio_in <= wb_spiflash_out;
-            wb_spiflash_is_map <= '1';
-	when SLAVE_IO_SPI_FLASH_REG =>
-	    wb_spiflash_in.cyc <= wb_sio_out.cyc;
-	    wb_sio_in <= wb_spiflash_out;
-            wb_spiflash_is_reg <= '1';
        when SLAVE_IO_GPIO =>
-            wb_gpio_in.cyc <= wb_sio_out.cyc;
            wb_sio_in <= wb_gpio_out;
-	when others =>
 	end case;

+        -- Default response, ack & return all 1's
+        if io_cycle_none = '1' then
+            wb_sio_in.dat <= (others => '1');
+            wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
+            wb_sio_in.stall <= '0';
+        end if;
+
    end process;

    -- Syscon slave
--- a/spi_flash_ctrl.vhdl
+++ b/spi_flash_ctrl.vhdl
@ -50,7 +50,7 @@ architecture rtl of spi_flash_ctrl is
    constant SPI_REG_INVALID      : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "111";

    -- Control register
-    signal ctrl_reg    : std_ulogic_vector(15 downto 0) := (others => '0');
+    signal ctrl_reg    : std_ulogic_vector(15 downto 0);
    alias  ctrl_reset  : std_ulogic is ctrl_reg(0);
    alias  ctrl_cs     : std_ulogic is ctrl_reg(1);
    alias  ctrl_rsrv1  : std_ulogic is ctrl_reg(2);
@ -58,7 +58,7 @@ architecture rtl of spi_flash_ctrl is
    alias  ctrl_div    : std_ulogic_vector(7 downto 0) is ctrl_reg(15 downto 8);

    -- Auto mode config register
-    signal auto_cfg_reg     : std_ulogic_vector(29 downto 0) := (others => '0');
+    signal auto_cfg_reg     : std_ulogic_vector(29 downto 0);
    alias  auto_cfg_cmd     : std_ulogic_vector(7 downto 0) is auto_cfg_reg(7 downto 0);
    alias  auto_cfg_dummies : std_ulogic_vector(2 downto 0) is auto_cfg_reg(10 downto 8);
    alias  auto_cfg_mode    : std_ulogic_vector(1 downto 0) is auto_cfg_reg(12 downto 11);
@ -126,9 +126,9 @@ architecture rtl of spi_flash_ctrl is
    signal auto_latch_adr : std_ulogic;

    -- Automatic mode latches
-    signal auto_data      : std_ulogic_vector(wb_out.dat'left downto 0) := (others => '0');
-    signal auto_cnt       : integer range 0 to 63 := 0;
-    signal auto_state     : auto_state_t := AUTO_BOOT;
+    signal auto_data      : std_ulogic_vector(wb_out.dat'left downto 0);
+    signal auto_cnt       : integer range 0 to 63;
+    signal auto_state     : auto_state_t;
    signal auto_last_addr : std_ulogic_vector(31 downto 0);

 begin
@ -351,6 +351,8 @@ begin
            if rst = '1' then
                auto_last_addr <= (others => '0');
                auto_state <= AUTO_BOOT;
+                auto_cnt <= 0;
+                auto_data  <= (others => '0');
            else
                auto_state <= auto_next;
                auto_cnt   <= auto_cnt_next;
--- a/spi_rxtx.vhdl
+++ b/spi_rxtx.vhdl
@ -126,10 +126,10 @@ architecture rtl of spi_rxtx is
    signal dat_ack_l : std_ulogic;

    -- Delayed recv signal for the read machine
-    signal sck_recv_d : std_ulogic := '0';
+    signal sck_recv_d : std_ulogic;

    -- Input shift register (use fifo ?)
-    signal ireg       : std_ulogic_vector(7 downto 0) := (others => '0');
+    signal ireg       : std_ulogic_vector(7 downto 0);

    -- Bit counter
    signal bit_count  : std_ulogic_vector(2 downto 0);
@ -157,7 +157,7 @@ architecture rtl of spi_rxtx is
    end;

    type state_t is (STANDBY, DATA);
-    signal state : state_t := STANDBY;
+    signal state : state_t;
 begin

    -- We don't support multiple data lines at this point
@ -349,6 +349,9 @@ begin
    shift_in: process(clk)
    begin
        if rising_edge(clk) then
+            if rst = '1' then
+                ireg <= (others => '0');
+            end if;

            -- Delay the receive signal to match the input latch
            if state = DATA then
--- a/wishbone_bram_wrapper.vhdl
+++ b/wishbone_bram_wrapper.vhdl
@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
 end entity wishbone_bram_wrapper;

 architecture behaviour of wishbone_bram_wrapper is
-    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
+    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE-1) - 3;

    -- RAM interface
    signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);
--- a/wishbone_types.vhdl
+++ b/wishbone_types.vhdl
@ -15,6 +15,9 @@ package wishbone_types is
    subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);
    subtype wishbone_sel_type  is std_ulogic_vector(wishbone_sel_bits-1  downto 0);

+    function addr_to_wb(addr: std_ulogic_vector) return wishbone_addr_type;
+    function wb_to_addr(wb_addr: wishbone_addr_type) return std_ulogic_vector;
+
    type wishbone_master_out is record
        adr : wishbone_addr_type;
        dat : wishbone_data_type;
@ -38,6 +41,7 @@ package wishbone_types is
    --
    -- IO Bus to a device, 30-bit address, 32-bits data
    --
+
    type wb_io_master_out is record
        adr : std_ulogic_vector(29 downto 0);
        dat : std_ulogic_vector(31 downto 0);
@ -56,3 +60,19 @@ package wishbone_types is
    end record;
    constant wb_io_slave_out_init : wb_io_slave_out := (ack => '0', stall => '0', others => (others => '0'));
 end package wishbone_types;
+
+package body wishbone_types is
+    function addr_to_wb(addr: std_ulogic_vector) return wishbone_addr_type is
+    begin
+        assert addr'length >= (wishbone_addr_type'length + wishbone_log2_width);
+        assert addr'right = 0;
+        return addr(wishbone_addr_type'left + wishbone_log2_width downto wishbone_log2_width);
+    end;
+    function wb_to_addr(wb_addr: wishbone_addr_type) return std_ulogic_vector is
+        variable ret  : std_ulogic_vector(63 downto 0);
+    begin
+        ret := (others => '0');
+        ret(wishbone_addr_type'left + wishbone_log2_width downto wishbone_log2_width) := wb_addr;
+        return ret;
+    end;
+end wishbone_types;
--- a/xics.vhdl
+++ b/xics.vhdl
@ -54,9 +54,6 @@ architecture behaviour of xics_icp is

    signal r, r_next : reg_internal_t;

-    -- hardwire the hardware IRQ priority
-    constant HW_PRIORITY : std_ulogic_vector(7 downto 0) := x"80";
-
    -- 8 bit offsets for each presentation
    constant XIRR_POLL : std_ulogic_vector(7 downto 0) := x"00";
    constant XIRR      : std_ulogic_vector(7 downto 0) := x"04";
@ -207,12 +204,14 @@ use ieee.numeric_std.all;

 library work;
 use work.common.all;
+use work.utils.all;
 use work.wishbone_types.all;
+use work.helpers.all;

 entity xics_ics is
    generic (
        SRC_NUM    : integer range 1 to 256  := 16;
-        PRIO_BITS  : integer range 1 to 8    := 8
+        PRIO_BITS  : integer range 1 to 8    := 3
        );
    port (
        clk          : in std_logic;
@ -228,12 +227,16 @@ end xics_ics;

 architecture rtl of xics_ics is

+    constant SRC_NUM_BITS : natural := log2(SRC_NUM);
+
    subtype pri_t is std_ulogic_vector(PRIO_BITS-1 downto 0);
    type xive_t is record
        pri : pri_t;
    end record;
    constant pri_masked : pri_t := (others => '1');

+    subtype pri_vector_t is std_ulogic_vector(2**PRIO_BITS - 1 downto 0);
+
    type xive_array_t is array(0 to SRC_NUM-1) of xive_t;
    signal xives : xive_array_t;

@ -262,8 +265,15 @@ architecture rtl of xics_ics is
    end function;

    function prio_pack(pri8: std_ulogic_vector(7 downto 0)) return pri_t is
+        variable masked : std_ulogic_vector(7 downto 0);
    begin
-        return pri8(PRIO_BITS-1 downto 0);
+        masked := x"00";
+        masked(PRIO_BITS - 1 downto 0) := (others => '1');
+        if unsigned(pri8) >= unsigned(masked) then
+            return pri_masked;
+        else
+            return pri8(PRIO_BITS-1 downto 0);
+        end if;
    end function;

    function prio_unpack(pri: pri_t) return std_ulogic_vector is
@ -276,8 +286,27 @@ architecture rtl of xics_ics is
            r(PRIO_BITS-1 downto 0) := pri;
        end if;
        return r;
-   end function;
+    end function;

+    function prio_decode(pri: pri_t) return pri_vector_t is
+        variable v: pri_vector_t;
+    begin
+        v := (others => '0');
+        v(to_integer(unsigned(pri))) := '1';
+        return v;
+    end function;
+
+    -- Assumes nbits <= 6; v is 2^nbits wide
+    function priority_encoder(v: std_ulogic_vector; nbits: natural) return std_ulogic_vector is
+        variable h: std_ulogic_vector(2**nbits - 1 downto 0);
+        variable p: std_ulogic_vector(5 downto 0);
+    begin
+        -- Set the lowest-priority (highest-numbered) bit
+        h := v;
+        h(2**nbits - 1) := '1';
+        p := count_right_zeroes(h);
+        return p(nbits - 1 downto 0);
+    end function;

 -- Register map
    --     0  : Config
@ -391,35 +420,33 @@ begin
    end process;

    irq_gen: process(all)
-        variable max_idx : integer range 0 to SRC_NUM-1;
+        variable max_idx : std_ulogic_vector(SRC_NUM_BITS - 1 downto 0);
        variable max_pri : pri_t;
-
-        -- A more favored than b ?
-        function a_mf_b(a: pri_t; b: pri_t) return boolean is
-            variable a_i : unsigned(PRIO_BITS-1 downto 0);
-            variable b_i : unsigned(PRIO_BITS-1 downto 0);
-        begin
-            a_i := unsigned(a);
-            b_i := unsigned(b);
-            report "a_mf_b a=" & to_hstring(a) &
-                " b=" & to_hstring(b) &
-                " r=" & boolean'image(a < b);
-            return a_i < b_i;
-        end function;
+        variable pending_pri : pri_vector_t;
+        variable pending_at_pri : std_ulogic_vector(SRC_NUM - 1 downto 0);
    begin
-        -- XXX FIXME: Use a tree
-        max_pri := pri_masked;
-        max_idx := 0;
+        -- Work out the most-favoured (lowest) priority of the pending interrupts
+        pending_pri := (others => '0');
        for i in 0 to SRC_NUM - 1 loop
-            if int_level_l(i) = '1' and a_mf_b(xives(i).pri, max_pri) then
-                max_pri := xives(i).pri;
-                max_idx := i;
+            if int_level_l(i) = '1' then
+                pending_pri := pending_pri or prio_decode(xives(i).pri);
            end if;
        end loop;
+        max_pri := priority_encoder(pending_pri, PRIO_BITS);
+
+        -- Work out which interrupts are pending at that priority
+        pending_at_pri := (others => '0');
+        for i in 0 to SRC_NUM - 1 loop
+            if int_level_l(i) = '1' and xives(i).pri = max_pri then
+                pending_at_pri(i) := '1';
+            end if;
+        end loop;
+        max_idx := priority_encoder(pending_at_pri, SRC_NUM_BITS);
+
        if max_pri /= pri_masked then
-            report "MFI: " & integer'image(max_idx) & " pri=" & to_hstring(prio_unpack(max_pri));
+            report "MFI: " & integer'image(to_integer(unsigned(max_idx))) & " pri=" & to_hstring(prio_unpack(max_pri));
        end if;
-        icp_out_next.src <= std_ulogic_vector(to_unsigned(max_idx, 4));
+        icp_out_next.src <= max_idx;
        icp_out_next.pri <= prio_unpack(max_pri);
    end process;