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@ -46,8 +46,6 @@ entity icache is
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TLB_SIZE : positive := 64;
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-- L1 ITLB log_2(page_size)
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TLB_LG_PGSZ : positive := 12;
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-- Number of real address bits that we store
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REAL_ADDR_BITS : positive := 56;
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-- Non-zero to enable log data collection
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LOG_LENGTH : natural := 0
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);
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@ -207,10 +205,10 @@ architecture rtl of icache is
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signal req_tag : cache_tag_t;
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signal req_is_hit : std_ulogic;
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signal req_is_miss : std_ulogic;
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signal req_laddr : std_ulogic_vector(63 downto 0);
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signal req_raddr : real_addr_t;
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signal tlb_req_index : tlb_index_t;
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signal real_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
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signal real_addr : real_addr_t;
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signal ra_valid : std_ulogic;
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signal priv_fault : std_ulogic;
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signal access_ok : std_ulogic;
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@ -251,9 +249,9 @@ architecture rtl of icache is
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end;
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-- Returns whether this is the last row of a line
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function is_last_row_addr(addr: wishbone_addr_type; last: row_in_line_t) return boolean is
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function is_last_row_wb_addr(wb_addr: wishbone_addr_type; last: row_in_line_t) return boolean is
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begin
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return unsigned(addr(LINE_OFF_BITS - ROW_OFF_BITS - 1 downto 0)) = last;
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return unsigned(wb_addr(LINE_OFF_BITS - ROW_OFF_BITS - 1 downto 0)) = last;
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end;
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-- Returns whether this is the last row of a line
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@ -263,15 +261,15 @@ architecture rtl of icache is
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end;
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-- Return the address of the next row in the current cache line
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function next_row_addr(addr: wishbone_addr_type)
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function next_row_wb_addr(wb_addr: wishbone_addr_type)
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return std_ulogic_vector is
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variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
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variable result : wishbone_addr_type;
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begin
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-- Is there no simpler way in VHDL to generate that 3 bits adder ?
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row_idx := addr(ROW_LINEBITS - 1 downto 0);
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row_idx := wb_addr(ROW_LINEBITS - 1 downto 0);
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row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
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result := addr;
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result := wb_addr;
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result(ROW_LINEBITS - 1 downto 0) := row_idx;
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return result;
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end;
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@ -301,10 +299,9 @@ architecture rtl of icache is
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end;
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-- Get the tag value from the address
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function get_tag(addr: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
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endian: std_ulogic) return cache_tag_t is
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function get_tag(addr: real_addr_t; endian: std_ulogic) return cache_tag_t is
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begin
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return endian & addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
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return endian & addr(addr'left downto SET_SIZE_BITS);
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end;
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-- Read a tag from a tag memory row
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@ -468,7 +465,7 @@ begin
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end if;
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eaa_priv <= pte(3);
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else
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real_addr <= i_in.nia(REAL_ADDR_BITS - 1 downto 0);
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real_addr <= addr_to_real(i_in.nia);
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ra_valid <= '1';
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eaa_priv <= '1';
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end if;
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@ -524,8 +521,7 @@ begin
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-- Calculate address of beginning of cache row, will be
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-- used for cache miss processing if needed
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--
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req_laddr <= (63 downto REAL_ADDR_BITS => '0') &
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real_addr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS)&
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req_raddr <= real_addr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS) &
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(ROW_OFF_BITS-1 downto 0 => '0');
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-- Test if pending request is a hit on any way
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@ -627,7 +623,7 @@ begin
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icache_miss : process(clk)
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variable tagset : cache_tags_set_t;
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variable tag : cache_tag_t;
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variable snoop_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
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variable snoop_addr : real_addr_t;
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variable snoop_tag : cache_tag_t;
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variable snoop_cache_tags : cache_tags_set_t;
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begin
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@ -657,8 +653,7 @@ begin
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-- Detect snooped writes and decode address into index and tag
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-- Since we never write, any write should be snooped
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snoop_valid <= wb_snoop_in.cyc and wb_snoop_in.stb and wb_snoop_in.we;
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snoop_addr := (others => '0');
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snoop_addr(wb_snoop_in.adr'left + ROW_OFF_BITS downto ROW_OFF_BITS) := wb_snoop_in.adr;
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snoop_addr := addr_to_real(wb_to_addr(wb_snoop_in.adr));
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snoop_index <= get_index(snoop_addr);
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snoop_cache_tags := cache_tags(get_index(snoop_addr));
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snoop_tag := get_tag(snoop_addr, '0');
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@ -709,15 +704,15 @@ begin
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-- Keep track of our index and way for subsequent stores
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r.store_index <= req_index;
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r.store_row <= get_row(req_laddr);
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r.store_row <= get_row(req_raddr);
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r.store_tag <= req_tag;
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r.store_valid <= '1';
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r.end_row_ix <= get_row_of_line(get_row(req_laddr)) - 1;
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r.end_row_ix <= get_row_of_line(get_row(req_raddr)) - 1;
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-- Prep for first wishbone read. We calculate the address of
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-- the start of the cache line and start the WB cycle.
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--
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r.wb.adr <= req_laddr(r.wb.adr'left + ROW_OFF_BITS downto ROW_OFF_BITS);
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r.wb.adr <= addr_to_wb(req_raddr);
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r.wb.cyc <= '1';
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r.wb.stb <= '1';
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@ -749,12 +744,12 @@ begin
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if wishbone_in.stall = '0' and r.wb.stb = '1' then
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-- That was the last word ? We are done sending. Clear stb.
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--
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if is_last_row_addr(r.wb.adr, r.end_row_ix) then
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if is_last_row_wb_addr(r.wb.adr, r.end_row_ix) then
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r.wb.stb <= '0';
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end if;
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-- Calculate the next row address
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r.wb.adr <= next_row_addr(r.wb.adr);
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r.wb.adr <= next_row_wb_addr(r.wb.adr);
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end if;
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-- Abort reload if we get an invalidation
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@ -785,7 +780,7 @@ begin
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when STOP_RELOAD =>
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-- Wait for all outstanding requests to be satisfied, then
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-- go to IDLE state.
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if get_row_of_line(r.store_row) = get_row_of_line(get_row(r.wb.adr)) then
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if get_row_of_line(r.store_row) = get_row_of_line(get_row(wb_to_addr(r.wb.adr))) then
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r.wb.cyc <= '0';
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r.state <= IDLE;
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end if;
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