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@ -82,33 +82,42 @@ architecture bypass of clock_generator is
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CLKINTFB : out std_logic );
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end component;
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signal clkos : std_ulogic;
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signal clkop : std_logic;
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signal lock : std_logic;
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-- PLL constants based on prjtrellis example
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constant PLL_IN : natural := 2000000;
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constant PLL_OUT : natural := 600000000;
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-- PLL constants
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-- According to the datasheet, PLL_IN needs to be between 10 and 400 MHz
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-- PLL_OUT needs to be between 400 and 800 MHz
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-- PLL_IN is chosen based on 12 and 48 MHz being common values
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-- for the reference clock.
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constant PLL_IN : natural := 12000000;
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constant PLL_OUT : natural := 480000000;
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-- Configration for ECP5 PLL
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constant PLL_CLKOP_DIV : natural := PLL_OUT/CLK_OUTPUT_HZ;
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constant PLL_CLKFB_DIV : natural := CLK_OUTPUT_HZ/PLL_IN;
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constant PLL_CLKOS_DIV : natural := 2;
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constant PLL_CLKFB_DIV : natural := PLL_OUT/PLL_CLKOS_DIV/PLL_IN;
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constant PLL_CLKI_DIV : natural := CLK_INPUT_HZ/PLL_IN;
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begin
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pll_clk_out <= clkop;
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pll_locked_out <= not lock; -- FIXME: EHXPLLL lock signal active low?!?
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pll_locked_out <= lock;
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clkgen: EHXPLLL
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generic map(
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CLKOP_CPHASE => 11, -- FIXME: Copied from prjtrells.
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CLKOP_DIV => PLL_CLKOP_DIV,
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CLKOS_ENABLE => "ENABLED",
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CLKOS_DIV => PLL_CLKOS_DIV,
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CLKFB_DIV => PLL_CLKFB_DIV,
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CLKI_DIV => PLL_CLKI_DIV
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CLKI_DIV => PLL_CLKI_DIV,
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FEEDBK_PATH => "CLKOS"
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)
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port map (
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CLKI => ext_clk,
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CLKOP => clkop,
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CLKFB => clkop,
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CLKOS => clkos,
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CLKFB => clkos,
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LOCK => lock,
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RST => pll_rst_in,
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PHASESEL1 => '0',
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@ -118,8 +127,8 @@ begin
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PHASELOADREG => '0',
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STDBY => '0',
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PLLWAKESYNC => '0',
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ENCLKOP => '0',
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ENCLKOS => '0',
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ENCLKOP => '1',
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ENCLKOS => '1',
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ENCLKOS2 => '0',
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ENCLKOS3 => '0'
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);
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